Instruction/ maintenance manual of the product ChipScope PLB46 IBA v1.00a Xilinx
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DS619 April 7, 2009 www .xilinx.com 1 Product Specification © 2009 Xilinx, Inc. X ilinx, Inc. XILINX, the Xilinx lo go, V i rtex, Spartan, ISE and other designate d brands included herein are trademarks of Xilinx in th e United States and other countries.
2 www .xilinx.com DS619 April 7, 2009 Product Specification ChipScope PLB46 IBA I/O Signals T able 1: IBA_PLBv46 Pin Descriptions Port MU Signal Name Interface I/O Description P1 CONTROL ICON I/O Icon.
DS619 April 7, 2009 www .xilinx.com 3 Product Specification P32 MU_2B PLB_masterID[0: C_PLBV46_MID_WIDTH-1] Slave I PLB current ma ster identifier P33 MU_2B PLB_BE[0: C_PLBV46_DWIDTH/8-1] Slave I PLB .
4 www .xilinx.com DS619 April 7, 2009 Product Specification P54 MU_9 Sl_MWrErr[0: C_PLBV46_NUM_SLA VES *C_PLBV46_NUM_MASTERS-1] Slave I Slave write error indicator PLB Arbitr ation Signals P55 MU_10 M.
DS619 April 7, 2009 www .xilinx.com 5 Product Specification The IBA_PLBv46 por ts listed in Ta b l e 1 connect to the PLBv46 bus. The core divides related ports into 13 match unit groups (MUs) as shown i n the second column of the table. Each m atch unit group can conn ect to a trigger port of the IBA.
6 www .xilinx.com DS619 April 7, 2009 Product Specification When these match units are enabled, all slaves or master s are enabled. Y ou canno t individually enable a particular master . The match units 7, 8, and 9 are slave side signals for BUSY , READ, and WRITE error controls going to the mas- ter .
DS619 April 7, 2009 www .xilinx.com 7 Product Specification G13 Enable T rigger Out C_ENAB LE_TRIGGER_OUT 1,0 0 Integer T rigger In, PLB Reset, and PLB Erro r S tatus G14 Use system rese t and error s.
8 www .xilinx.com DS619 April 7, 2009 Product Specification G32 1=Enable storing MU 3 signals in the data sample storage buffer . 0=Disable C_USE_MU_3A_ABUS or must C_USE_MU_3B_UABUS be 1 in order to store.
DS619 April 7, 2009 www .xilinx.com 9 Product Specification G46 1=Enable storing MU 6 signals in the data sample storage buffer . 0=Disable C_USE_MU_6A_SL V_CTL or C_USE_MU_6B_SL V_SZ_W ADD R must be 1 in order to store.
10 www .xilinx.com DS619 April 7, 2009 Product Specification Ta b l e 2 lists the IBA PLBv46 parameterized feat ures, which c ontrol the ports attached to the IBA trigger and stor- age units. They also are used to co nfigure the storage and match unit op tions available for each trigger port.
DS619 April 7, 2009 www .xilinx.com 11 Product Specification Every match unit group has a match type and mat ch counter width parameter . The match unit type describes the type of compare operation that can be done on a match unit. Th e valid values for this type are defined for each match unit.
12 www .xilinx.com DS619 April 7, 2009 Product Specification Design Implementation The ChipScope PLB IBA desi gn is implemented in a T cl script. Wh en the EDK Platgen tool is run, thi s T cl script is called and it internally calls the ChipScope Pro Core generator in command line mode providin g a generated argument (.
DS619 April 7, 2009 www .xilinx.com 13 Product Specification Revision History Notice of Disclaimer Xilinx is providing this design, code, or inform ation (collectively , the “Information”) to you “ AS-IS ” with no warranty of any kind, express or implied.
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