Instruction/ maintenance manual of the product RS-232 SYNCHRONOUS Quatech
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MPA-100 RS-232 SYNCHRONOUS ADAPTER CARD User's Manual QUATECH, INC. TEL: (330) 665-9000 5675 Hudson Industrial Parkway FAX: (330) 665-9010 Hudson, Ohio 44236 http://www.
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Warranty Information Quatech Inc. warrants the MPA-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc.
Table of Contents 13-1 13. SPECIFICATIONS ............................................... . 12-1 12. DEFINITION OF INTERFACE SIGNALS ........................ . 11-6 11. EXTERNAL CONNECTIONS .................................... . 10-3 10.2 DCE Configuration .
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1. INTRODUCTION The Quatech MPA-100 is a single channel, synchronous RS-232 compatible serial communication port for systems utilizing the architecture of the IBM AT personal computer or compatible. Figure 1 depicts the layout of th e MPA-100. Figure 1 MPA-100 Board Layout Quatech, Inc.
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2. HARDWARE INSTALLATION If the default address and interrupt settin gs are sufficient, the MPA-100 can be quickly installed and put to use. The factory default settings are listed below in Table 1. Table 1 Default Resource Settings DMA/DRQ 1 DMA/DRQ 3 IRQ 5 300 hex RxDMA TxDMA Interrupt Address 1.
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3. ADDRESSING The MPA-100 occupies a continuous 8 byte block of I/O addresses. For example, if the base address is set to 300H, then the MPA-100 will occupy address locations 300H-307H.
The first four bytes, Base+0 through Base+3, of address space on the MPA-100 contain the internal registers of the SCC. The next two locations Base+4 and Base+5 contain the Communications Register and the Configuration Register. The last two address port locations are reserved for future use.
4. INTERRUPTS The MPA-100 supports eleven interrupt levels: IRQ2 -7, IRQ10 - 12, and IRQ14 - 15, and selects which interrupt level is in use through jumper packs J5 and J6. The MPA-100 has three interrupt sources: interrupt on terminal count, interrupt on test mode, and interrupt from the SCC.
4.1 Using Terminal Count to Generate Interrupts The MPA-100 allows the option of generating an interrupt whenever the Terminal Count (TC) signal is asserted. Terminal Count is an indicator generated by the system’s DMA controller, which signals that the number of transfers programed into the DMA controller’s transfer register have occurred.
5. JUMPER CONFIGURATIONS The MPA-100 utilizes various jumper blocks which allow the user to customize their hardware configuration. The following sections explain the function and setting of each of the jumper blocks on the MPA-100.
5.3 Interrupt Level Selection - J5 & J6 Jumper blocks J5 and J6 select the interrupt level that the MPA-100 utilizes. Interrupt levels IRQ2 - IRQ7 reside on J5, while interrupt levels IRQ10 - IRQ12 and IRQ14 - IRQ15 reside on J6. Table 5 and Table 6 summarize the jumper block selections for J5 and J6.
5.4 Transmit DMA Selection - J8 J8 Selects the DMA channel to be used for Transmit DMA. Three channels (1 - 3) are available on the MPA-100 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected.
NOTE: Since it is illegal to perform DMA on transmit and receive on the same DMA channel, jumper blocks J7 and J8 should never have the same pins connected. This could result in damage to the system. 5.6 SYNCA to RLEN Control - J7 J7 controls the signal path from the RLEN bit in the Communications Register to the SYNCA input to the SCC.
6. SCC GENERAL INFORMATION The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPA-100 provides a single channel for communications, however, to provide full DMA capabilities with complete modem control line support, both channels of the SCC can be utilized.
6.1 Accessing the Registers The mode of communication desired is established and monitored through the bit values of the internal read and write registers.
Example 2: Monitoring the status of the transmit and receive buffers in RR0 of Channel A. Register 0 is addressed by default if no register number is written to WR0 first. mov dx,base ; load base address add dx,ContA ; add control reg A offset (1) in ax,dx ; read the status Example 3: Write data into the transmit buffer of channel A.
and receive clocks. These clocks can be programmed in WR11 to come from the RTXC pin, the TRXC pin, the output of the BRG, or the transmit output of the DPLL. Programming of the clocks should be done before enabling the receiver, transmitter, BRG, or DPLL.
6.2 Baud Rate Generator Programming The baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bit down counter, two 8-bit time constant registers, and an output divide-by-two. The time constant for the BRG is programmed into WR12 (least significant byte) and WR13 (most significant byte).
6.3 SCC Data Encoding Methods The SCC provides four different data encoding methods, selected by bits D6 and D5 in WR10. These four include NRZ, NRZI, FM1 and FM0. The SCC also features a digital phase-locked loop (DPLL) that can be programmed to operate in NRZI or FM modes.
7. DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a way of transferring data on the ISA bus directly to and from memory, resulting in high data transfer rates with very low CPU overhead. The ISA bus DMA channel(s) to be used are selected through jumper packs J6 and J7.
When using the channel A DTR/REQ pin for transmit DMA the SCC must be programmed so that the request release timing of this pin is identical to the WAIT/REQ timing.
8. CONFIGURATION REGISTER The MPA-100 is equipped with an onboard register used for configuring information such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed description of the Configuration Register. The address of this register is Base+5.
D1 -RXSRC, RECEIVE DMA SOURCE: When set (logic 1), this bit allows the source for Receive DMA to come from the W/REQB pin of channel B on the SCC. When cleared (logic 0), the source for Receive DMA comes from the W/REQA pin of channel A on the SCC.
9. COMMUNICATIONS REGISTER The MPA-100 is equipped with an onboard Communications Register which gives the user options pertaining to the clocks and testing. The user can specify the source and type of clock to be transmitted or received. Test mode bits pertain only to the DTE versions and can be ignored if using a DCE configured MPA-100.
D4 -REMOTE LOOPBACK ENABLE : When set (logic 1), this bit allows the DTE to test the transmission path up to and through the remote DCE to the DTE interface and the similar return transmission path.
10. DTE/DCE CONFIGURATION As indicated earlier in this manual, the MPA-100 can be configured as either a Data Terminal Equipment (DTE) or a Data Communications Equipment (DCE) device. The differences between these configurations include signal definitions, connector pin out , and clocking options.
10.1 DTE Configuration The MPA-100 is configured as a DTE device by correctly setting jumper packs J2, J11 and J12. See Section 5, Table 3 for this configuration information. The control signals the DTE can generate are Request To Send (RTS) and Data Terminal Ready (DTR).
The testing signals the DTE can generate are the Local Loopback Test (LL) and the Remote Loopback Test (RL). These signals are generated from the onboard Communications Register. When a Test Mode (TM) condition is received, an interrupt can be generated on the DTE.
Control signals the DCE can generate are the Clear to Send (CTS), Carrier Detect (CD), and Data Set Ready (DSR). It can receive the signals D ata Terminal Ready (DTR) and Ready to Send (RTS).
Table 17 DCE Signals INTM or Bit D7 of Comm Reg X TM Bit D4 of Comm Reg X RL Bit D5 of Comm. Reg X LL RTXC/TRXCB pin of SCC X X RxCLK TRXCA pin of SCC X TxCLK DTR/REQB pin of SCC X CD DTR/REQA pin of .
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11. EXTERNAL CONNECTIONS The MPA-100 is designed to meet the RS-232 standard through a D-25 connector. The MPA-100 uses a D-25 short body male connector (labeled CN1) for both the DTE and DCE configurations. Jumper blocks J2, J11, and J12 configure the connector pin out.
Table 19 DCE Connector Pin Definitions D7 of COMM REG X TEST MODE 25 RTXC pins on SCC X TXCLK (DTE) 24 - - - N/C 23 - - - N/C 22 D4 of COMM REG X RL 21 DCDB on SCC X DTR 20 - - - N/C 19 D5 of COMM REG.
Figure 6 MPA-100 DTE Output Connector Configuration 25 Test Mode (Output) 24 TxCLK (DTE) 23 N/C 22 N/C 21 RLBK (Output) 20 DTR 19 N/C 18 LLBK (Output) 17 RxCLK (DCE) 16 N/C 15 TxCLK (DCE) 14 N/C N/C 1.
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12. DEFINITION OF INTERFACE SIGNALS CIRCUIT AB - Signal Ground CONNECTOR NOTATION: DGND DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground.
CIRCUIT DD - Receiver Signal Element Timing (RxClk - DCE Source) CONNECTOR NOTATION: RXCLK (DCE) DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted by the DCE.
CIRCUIT RL - Remote Loopback CONNECTOR NOTATION: RLBK DIRECTION: To DCE This signal provides a means whereby a DTE or a facility test center may check the transmission path up to and through the remote DCE to the DTE interface and the similar return transmission path.
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13. SPECIFICATIONS Bus interface: IBM AT 16-bit bus Controller: Serial Communications Controller, 10 MHz (determined by user, typically an AMD 85C30). Interface: DTE: male D-25 connector Transmit driv.
MPA-100 User's Manual Version 4.12 March 2004 Part No. 940-0037-412 MPA-100 User's Manual 13-2.
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