Instruction/ maintenance manual of the product uPD78053Y NEC
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µ PD78054, 78054Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLERS µ PD78052 µ PD78052Y µ PD78053 µ PD78053Y µ PD78054 µ PD78054Y µ PD78P054 µ PD78055Y µ PD78055 µ PD78056Y µ PD78056 µ PD78058Y µ PD78058 µ PD78P058Y µ PD78P058 µ PD78052(A) µ PD78053(A) µ PD78054(A) Document No.
2 [MEMO].
3 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
4 FIP, EEPROM, IEBus, QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
5 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips.
6 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors.
7 Major Revisions in This Edition Page Description Throughout Addition of µ PD78052(A),78053(A), 78054(A) to the applicable types Deletion of µ PD78P054Y from the applicable types Deletion of the fo.
8 [MEMO].
9 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78054 and 78054Y Subseries and design and develop its application systems and programs. The target products are the products of the following subseries.
10 How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For users who use this document as the manual for the µ P.
11 Chapter Organization : This manual divides the descriptions for the µ PD78054 and 78054Y Subseries into different chapters as shown below. Read only the chapters related to the device you use.
12 Differences between µ PD78054 and µ PD78054Y Subseries: The µ PD78054 and µ PD78054Y Subseries are different in the following functions of the serial interface channel 0.
13 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
14 Development Tool Documents (User’s Manuals) Document name Document No. Japanese English RA78K0 Assembler Package Operation U11802J U11802E Assembly Language U11801J U11801E Structured Assembly U1.
15 Documents for Embedded Software (User’s Manual) Document name Document No. Japanese English 78K/0 Series Real-Time OS Basics U11537J U11537E Installation U11536J U11536E OS for 78K/0 Series MX78K0 Basics U12257J U12257E Other Documents Document name Document No.
16 [MEMO].
17 T ABLE OF CONTENTS CHAPTER 1 GENERAL ( µ PD78054 Subseries) ............................................................................ 37 1.1 Features ..............................................................................................
18 3.2.18 V DD ....................................................................................................................................... 70 3.2.19 V SS .....................................................................................
19 5.3.3 T able indirect addressing ..................................................................................................... 120 5.3.4 Register addressing ...................................................................................
20 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................. 175 8.1 Outline of Timers Incorporated in the µ PD78054, 78054Y Subseries .......................... 175 8.2 16-Bit Timer/Event Counter Functions .
21 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .................................................................... 261 13.1 Buzzer Output Control Circuit Functions ............................................................................. 261 13.2 Buzzer Output Control Circuit Configuration .
22 CHAPTER 18 SERIAL INTERF ACE CHANNEL 1 ............................................................................ 393 18.1 Serial Interface Channel 1 Functions .............................................................................. 393 18.
23 23.2 Standby Function Operations .......................................................................................... 527 23.2.1 HAL T mode ......................................................................................................
24 B.4 OS for IBM PC ................................................................................................................... 589 B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A .................. 589 APPENDIX C EMBEDDED SOFTW ARE .
25 LIST OF FIGURES (1/8) Figure No. T itle Page 3-1. Pin Input/Output Circuit of List ....................................................................................................... 73 4-1. Pin Input/Output Circuit of List ....................
26 LIST OF FIGURES (2/8) Figure No. T itle Page 6-18. P130 and P131 Block Diagram ..................................................................................................... 149 6-19. Port Mode Register Format ...............................
27 LIST OF FIGURES (3/8) Figure No. T itle Page 8-23. T iming of Pulse W idth Measurement Operation by Free-Running Counter and T wo Capture Registers (with Rising Edge Specified) .................................................................... 202 8-24.
28 LIST OF FIGURES (4/8) Figure No. T itle Page 12-1. Remote Controlled Output Application Example ........................................................................... 255 12-2. Clock Output Control Circuit Block Diagram .......................
29 LIST OF FIGURES (5/8) Figure No. T itle Page 16-17. Data ............................................................................................................................................... 312 16-18. Acknowledge Signal .................
30 LIST OF FIGURES (6/8) Figure No. T itle Page 17-26. Slave Wait Release (Reception) .................................................................................................... 387 17-27. SCK0/SCL/P27 Pin Configuration ......................
31 LIST OF FIGURES (7/8) Figure No. T itle Page 19-12. 3-Wire Serial I/O Mode T iming ...................................................................................................... 472 19-13. Circuit of Switching in T ransfer Bit Order .......
32 LIST OF FIGURES (8/8) Figure No. T itle Page 23-3. HAL T Mode Release by RESET Input .......................................................................................... . 529 23-4. ST OP Mode Release by Interrupt Request Generation .........
33 LIST OF T ABLES (1/3) T able No. T itle Page 1-1. Differences between Standard Quality Grade Products and (A) Products .................................... 48 1-2. Mask Options of Mask ROM V ersions .................................................
34 LIST OF T ABLES (2/3) T able No. T itle Page 9-8. 8-Bit T imer/Event Counters 1 and 2 Square-W ave Output Ranges .............................................. 232 9-9. Interval T imes when 2-Channel 8-Bit T imer/ Event Counters (TM1 and TM2) are Used as 16-Bit T imer/Event Counter .
35 LIST OF T ABLES (3/3) T able No. T itle Page 19-7. Receive Error Causes ................................................................................................................... 465 20-1. Real-time Output Port Configuration ..............
36 [MEMO].
37 CHAPTER 1 GENERAL ( µ PD78054 Subseries) 1.1 Features On-chip high-capacity ROM and RAM Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).
38 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.2 Applications µ PD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058: Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc.
39 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.4 Quality Grade Part number Package Quality grade µ PD78052GC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Standard µ PD78052GK- ××× -BE9 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Standard µ PD78053GC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
40 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
41 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) Pin Identifications A8 to A15 : Address Bus P130, P131 : Port13 AD0 to AD7 : Address/Data Bus PCL : Programmable Clock ANI0 to ANI7 : Analog Input RD : Rea.
42 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78P054GC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
43 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names.
44 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) The following shows the major differences between subseries products. Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O V DD Externa l Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A MIN.
45 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P054, 78P058.
46 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.8 Outline of Function ROM Mask ROM PROM Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 3 Note 3 High-.
47 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) Vectored Maskable Internal: 13 External: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.0 to 6.0 V Operating ambient temperature T A = –40 to +85 ° C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness : 2.
48 CHAPTER 1 OUTLINE ( µ PD78054 Subseries) 1.9 Differences between Standard Quality Grade Products and (A) Products Table 1-1 shows the differences between the standard quality grade products ( µ PD78052, 78053, 78054) and (A) products ( µ PD78052(A), 78053(A), 78054(A)).
49 CHAPTER 2 GENERAL ( µ PD78054Y Subseries) 2.1 Features On-chip high-capacity ROM and RAM Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).
50 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.2 Applications Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number Package Internal ROM µ PD78052YGC- ××× -8BT 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
51 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.5 Pin Configuration (Top View) (1) Normal operating mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.
52 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) Pin Identifications A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RESET : Reset ANI0 to ANI7 : Analog Input RD : Read Str.
53 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) (2) PROM programming mode • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78P058YGC-8BT • 80-pin ceramic WQFN (14 × 14 mm) µ PD78P058YKK-T Cautions 1. (L) : Connect individually to V SS via a pull-down resistor.
54 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names.
55 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) Major differences among Y subseries are tabulated below. Function ROM Configuration of Serial Interface I /O V DD Subseries Capacity MIN. Control µ PD78078Y 48K to 60K 3-wire/2-wire/I 2 C : 1 ch 88 1.8 V 3-wire with automatic transmit/receive function : 1 ch µ PD78070AY — 3-wire/UART : 1 ch 61 2.
56 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P058.
57 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) 2.8 Outline of Function ROM Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 512 bytes 1024 bytes.
58 CHAPTER 2 OUTLINE ( µ PD78054Y Subseries) Maskable Internal: 13 Vectored External: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.0 to 6.0 V Operating ambient temperature T A = –40 to +85 ° C Package • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.
59 Input Input/ output CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Function After Reset Alternate Function P00 Input Input only Input INTP0/TI00 P01 Input/output mode can be specified INTP1/TI01 P02 in 1-bit units.
60 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Input P40 to P47 Input AD0 to AD7 (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified in 1-bit units.
61 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
62 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 External interrupt request inputs with specifiable valid edges (rising P02 INTP3 Input edge, falling edge, both rising and falling edges).
63 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Output Input ASTB Output Input P67 V PP — —— Crystal connection for subsystem clock oscillation (2) Pins other than port pins (2/2) Pin Name Inp.
64 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as.
65 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified in 1-bit units.
66 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires.
67 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge.
68 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units.
69 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified in 1-bit units.
70 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) 3.2.13 AV DD Analog power supply pin of A/D converter. Always use the same voltage as that of the V DD pin even when A/D converter is not used. 3.2.14 AV SS This is a ground voltage pin of A/D converter and D/A converter.
71 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Input/Output Circuit Type P00/INTP0/TI00 2 Input Connect to V SS . P01/INTP1/TI01 P02/INTP2 P03/INTP3 Individually connect to V SS via a resistor. P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 16 Input Connect to V DD .
72 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Pin Name Input/Output Recommended Connection of Unused Pins 5-A Table 3-1. Pin Input/Output Circuit Types (2/2) Input/Output Circuit Type P60 to P63 (Mask ROM version) 13-B Input/output Individually connect to V DD via a resistor.
73 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Figure 3-1. Pin Input/Output Circuit of List (1/2) IN pullup enable V DD P-ch IN/OUT input enable output disable data V DD P-ch N-ch Type 2 Type 5-A S.
74 CHAPTER 3 PIN FUNCTION ( µ PD78054 Subseries) Type 12-A Type 13-B Type 13-D output disable V DD N-ch IN/OUT RD medium breakdown input buffer data P-ch XT2 XT1 feedback cut-off P-ch Type 16 output .
75 Input Input/ output CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/3) Pin Name Input/Output Function After Reset Alternate Function P00 Input Input only Input INTP0/TI00 P01 Input/output mode can be specified INTP1/TI01 P02 in 1-bit units.
76 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) P70 SI2/RxD P71 Input SO2/TxD P72 SCK2/ASCK Input P40 to P47 Input AD0 to AD7 N-ch open drain input/output port. On-chip pull-up resistor can be specified by mask option. (Mask ROM version only). LEDs can be driven directly.
77 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function Input/ Port 12. output 8-bit input/output port. Input/output mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be used by software.
78 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) (2) Pins other than port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 P00/TI00 INTP1 P01/TI01 INTP2 External interrupt request inputs with specifiable valid edges (rising P02 INTP3 Input edge, falling edge, both rising and falling edges).
79 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) (2) Pins other than port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus .
80 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function a.
81 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified in 1-bit units.
82 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output, and buzzer output. The following operating modes can be specified in 1-bit units.
83 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified in 1-bit units.
84 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified in 1-bit units.
85 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.10 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified in 1-bit units.
86 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 4.2.16 X1 and X2 Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2. 4.2.17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation.
87 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) Input/Output Circuit Type P00/INTP0/TI00 2 Input Connect to V SS . P01/INTP1/TI01 8-A P02/INTP2 P03/INTP3 Individually connect to V SS via a resistor. P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 16 Input Connect to V DD .
88 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) 5-A Table 4-1. Pin Input/Output Circuit Types (2/2) Input/Output Circuit Type P60 to P63 (Mask ROM version) 13-B Input/output Individually connect to V DD via a resistor. P60 to P63 (PROM version) 13-D P64/RD Input/output Individually connect to V DD or V SS via a resistor.
89 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (1/2) IN pullup enable V DD P-ch IN/OUT input enable output disable data V DD P-ch N-ch Type 2 Type 5-A .
90 CHAPTER 4 PIN FUNCTION ( µ PD78054Y Subseries) Figure 4-1. Pin Input/Output Circuit of List (2/2) Type 12-A Type 13-B Type 13-D output disable V DD N-ch IN/OUT RD medium breakdown input buffer dat.
91 CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Each product of the µ PD78054 and 78054Y Subseries can access the memory space of 64 Kbytes. Figures 5-1 to 5-8 show memory maps.
92 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD78053, 78053Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 24576 × 8 bits 5FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH.
93 CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( µ PD78054, 78054Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 32768 × 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH.
94 CHAPTER 5 CPU ARCHITECTURE Figure 5-4. Memory Map ( µ PD78P054) 0000H Data memory space Internal PROM 32768 × 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area C.
95 CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Memory Map ( µ PD78055, 78055Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 40960 × 8 bits 9FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH.
96 CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Memory Map ( µ PD78056, 78056Y) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 49152 × 8 bits BFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH.
97 CHAPTER 5 CPU ARCHITECTURE Figure 5-7. Memory Map ( µ PD78058, 78058Y) Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56K bytes by the memory size switching register (IMS).
98 CHAPTER 5 CPU ARCHITECTURE Figure 5-8. Memory Map ( µ PD78P058, µ PD78P058Y) Note When internal PROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56K bytes by the memory size switching register (IMS).
99 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC). Each product of the µ PD78054 and 78054Y Subseries has the internal ROM (or PROM) of the size shown below.
100 CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD78054 and 78054Y subseries units incorporate the following RAMs. (1) Internal high-speed RAM The µ PD78054 and 78054Y Subseries are provided with the internal high-speed RAM as shown below.
101 CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing.
102 CHAPTER 5 CPU ARCHITECTURE Figure 5-10. Data Memory Addressing ( µ PD78053, 78053Y) 0000H General Registers 32 × 8 bits Internal ROM 24576 × 8 bits Internal Buffer RAM 32 × 8 bits External Mem.
103 CHAPTER 5 CPU ARCHITECTURE Figure 5-11. Data Memory Addressing ( µ PD78054, 78054Y) 0000H General Registers 32 × 8 bits Internal ROM 32768 × 8 bits Internal Buffer RAM 32 × 8 bits External Mem.
104 CHAPTER 5 CPU ARCHITECTURE Figure 5-12. Data Memory Addressing ( µ PD78P054) 0000H General Registers 32 × 8 bits Internal PROM 32768 × 8 bits Internal Buffer RAM 32 × 8 bits External Memory 31.
105 CHAPTER 5 CPU ARCHITECTURE Figure 5-13. Data Memory Addressing ( µ PD78055, 78055Y) 0000H General Registers 32 × 8 bits Internal ROM 40960 × 8 bits Internal Buffer RAM 32 × 8 bits External Mem.
106 CHAPTER 5 CPU ARCHITECTURE Figure 5-14. Data Memory Addressing ( µ PD78056, 78056Y) 0000H General Registers 32 × 8 bits Internal ROM 49152 × 8 bits Internal Buffer RAM 32 × 8 bits External Mem.
107 CHAPTER 5 CPU ARCHITECTURE Figure 5-15. Data Memory Addressing ( µ PD78058, 78058Y) Note When internal ROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56K bytes by the memory size switching register.
108 CHAPTER 5 CPU ARCHITECTURE Figure 5-16. Data Memory Addressing ( µ PD78P058, 78P058Y) Note When internal PROM size is 60K bytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56K bytes by the memory size switching register (IMS).
109 CHAPTER 5 CPU ARCHITECTURE 70 IE PSW Z RBS1 AC RBS0 0 ISP CY 5.2 Processor Registers The µ PD78054 and 78054Y subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory.
110 CHAPTER 5 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts.
111 CHAPTER 5 CPU ARCHITECTURE Figure 5-19. Stack Pointer Configuration The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-20 and 5-21.
112 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register.
113 CHAPTER 5 CPU ARCHITECTURE BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEF7H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16-Bit Processing 8-Bit Processing FEF0H FEEFH FEE8H FEE7H Figure 5-22.
114 CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
115 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF00H Port0 P0 √√ — FF01H Port1 P1 √√ — FF02H Port2 P2 √√ — FF03H Port3 P3 √√ .
116 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF38H FF39H FF3AH FF3BH FF40H Timer clock select register 0 TCL0 √√ — FF41H Timer clock select .
117 CHAPTER 5 CPU ARCHITECTURE IF0L IF0H MK0L MK0H PR0L PR0H Address Special-Function Register (SFR) Name Symbol R/W After Reset FFD0H to FFDFH FFE0H Interrupt request flag register 0L √√ FFE1H In.
118 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 876 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start address of the instruction after the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents.
119 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
120 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched.
121 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution.
122 CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code.
123 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word.
124 CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH.
125 CHAPTER 5 CPU ARCHITECTURE 15 0 SFR Effective Address 1 111111 87 0 7 OP code sfr-offset 1 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.
126 CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.
127 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition.
128 CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition.
129 Port 6 Port 0 Port 7 8 Port 1 Port 2 P00 P60 P67 P70 P72 P10 P07 P17 P20 P27 Port 13 Port 3 Port 4 P120 P127 P130 Port 12 P131 P30 P37 P40-P47 Port 5 P50 P57 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78054 and 78054Y subseries units incorporate two input ports and sixty-seven input/output ports.
130 CHAPTER 6 PORT FUNCTIONS P10 to P17 ANI0 to ANI7 Pin Name Function Alternate Function P00 Input only INTP0/TI00 P01 INTP1/TI01 P02 Input/output mode can be specified in 1-bit INTP2 P03 Port 0. units. INTP3 P04 8-bit input/output port. When used as an input port, an on-chip INTP4 P05 pull-up resistor can be used by software.
131 CHAPTER 6 PORT FUNCTIONS P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK P120 to P127 RTP0 to RTP7 P130 and P131 ANO0, ANO1 Table 6-1. Port Functions ( µ PD78054 subseries) (2/2) Pin Name Function Alternate Function P60 N-ch open-drain input/output port. P61 On-chip pull-up resistor can be specified by P62 Port 6.
132 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD78054Y subseries) (1/2) Pin Name Function Alternate Function P00 Input only INTP0/TI00 P01 INTP1/TI01 P02 Input/output mode can be specified in 1-bit INTP2 P03 Port 0. units. INTP3 P04 8-bit input/output port.
133 CHAPTER 6 PORT FUNCTIONS P120 to P127 RTP0 to RTP7 P130 and P131 ANO0, ANO1 P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK Table 6-2. Port Functions ( µ PD78054Y subseries) (2/2) Pin Name Function Alternate Function P60 N-ch open drain input/output port. P61 On-chip pull-up resistor can be specified by P62 Port 6.
134 CHAPTER 6 PORT FUNCTIONS Control register 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Port mode register (PMm: m = 0 to 3, 5 .
135 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD P01/INTP1/TI01. P02/INTP2 P06/INTP6 Selector PUO0 Output Latch (P01 to P06) PM01-PM06 Internal bus P00/INTP0/TI00, P07/XT1 RD Internal bus Figure 6-2. P00 and P07 Block Diagram Figure 6-3.
136 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD P10/ANI0, P17/ANI7 Selector PUO1 Output Latch (P10 to P17) PM10-PM17 Internal bus 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1).
137 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23-P26) PM20, PM21 PM23-PM26 Internal bus Alternate Function P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0, P26/SO0/SB1 6.2.3 Port 2 ( µ PD78054 Subseries) Port 2 is an 8-bit input/output port with output latch.
138 CHAPTER 6 PORT FUNCTIONS Figure 6-6. P22 and P27 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal P-ch WR PM WR PORT RD.
139 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P20, P21, P23 to P26) PM20, PM21 PM23 to PM26 Internal bus Alternate Function P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1 6.2.4 Port 2 ( µ PD78054Y Subseries) Port 2 is an 8-bit input/output port with output latch.
140 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch (P22 and P27) PM22, PM27 Internal bus Alternate Function P22/SCK1, P27/SCK0/SCL Figure 6-8.
141 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO3 Output Latch (P30 to P37) PM30-PM37 Internal bus Alternate Function P30/TO0 P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch.
142 CHAPTER 6 PORT FUNCTIONS P40 P41 P42 P43 P44 P45 P46 P47 Falling Edge Detection Circuit KRMK KRIF Set Signal Standby Release Signal P-ch WR MM WR PORT RD WR PUO V DD Selector PUO4 Output Latch (P40 to P47) MM Internal bus P40/AD0 P47/AD7 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch.
143 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO5 Output Latch (P50 to P57) PM50-PM57 Internal bus P50/A8 P57/A15 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5).
144 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below.
145 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO6 Output Latch (P64 to P67) PM64-PM67 Internal bus P64/RD, P65/WR, P66/WAIT, P67/ASTB WR PM WR PORT RD V DD Selector Output Latch (P60 to P63) PM60-PM63 Internal bus P60-P63 Mask Option Resistor Mask ROM products only.
146 CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).
147 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO7 Output Latch (P71 and P72) PM71, PM72 Internal bus Alternate Function P71/SO2/TxD, P72/SCK2/ASCK Figure 6-16.
148 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO12 Output Latch (P120 to P127) PM120-PM127 Internal bus P120/RTP0 P127/RTP7 6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12).
149 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO13 Output Latch (P130 and P131) PM130, PM131 Internal bus P130/ANO0, P131/ANO1 6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13).
150 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resis.
151 CHAPTER 6 PORT FUNCTIONS Table 6-5. Port Mode Register and Output Latch Settings when Using Dual-Functions P00 INTP0 Input 1 (Fixed) None TI00 Input 1 (Fixed) None P01 INTP1 Input 1 × TI01 Input .
152 CHAPTER 6 PORT FUNCTIONS Figure 6-19. Port Mode Register Format PM0 PM1 PM2 1 PM06 PM03 PM02 PM01 1 76 54 3 210 Symbol PM3 PM5 FF20H FF21H FF22H FF23H FF25H FFH FFH FFH FFH FFH R/W R/W R/W R/W R/W.
153 CHAPTER 6 PORT FUNCTIONS PUO7 PUO6 PUO5 PUO4 PUO2 PUO1 PUO0 PUOL PUOm Pm Internal Pull-up Resistor Selection (m=0 to 7, 12, 13) 0 1 Internal pull-up resistor not used Internal pull-up resistor use.
154 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction.
155 CHAPTER 6 PORT FUNCTIONS KRIF Key Return Signal Detection Flag 0 1 Not Detected Detected (Falling edge detection of port 4) 00 0 0 KRM FFF6H 76 5 4 3 2 Symbol <1> 0 KRMK KRIF <0> 0 KRM.
156 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
157 CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again.
158 [MEMO].
159 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.
160 CHAPTER 7 CLOCK GENERATOR Subsystem Clock Oscillator Main System Clock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock .
161 CHAPTER 7 CLOCK GENERATOR FRC P-ch Feedback resistor XT1 XT2 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control regi.
162 CHAPTER 7 CLOCK GENERATOR MCC FRC CLS CSS PCC2 PCC1 PCC0 PCC CLS 0 1 Main system clock Subsystem clock FFFBH 04H R/W Note 1 <7> <5> <4> Symbol Address After Reset R/W 0 <6>.
163 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78054 and 78054Y Subseries is executed with two clocks of the CPU clock. Therefore, relationships between the CPU clock (f CPU ) and the minimum instruction execution time are as shown in Table 7-2.
164 CHAPTER 7 CLOCK GENERATOR Write to OSMS (MCS 0) f XX Max. 2/f X Operating at f XX = f X /2 (MCS = 0) Operating at f XX = f X /2 (MCS = 0) MCS Main System Clock Scaler Control 0 1 Scaler used Scale.
165 CHAPTER 7 CLOCK GENERATOR Crystal or Ceramic Resonator IC X1 X2 X1 PD74HCU04 µ X2 External Clock 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.
166 CHAPTER 7 CLOCK GENERATOR IC X2 X1 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator.
167 CHAPTER 7 CLOCK GENERATOR IC X1 X2 IC X2 X1 High Current Figure 7-8. Examples of Incorrect Oscillator Connection (2/2) (c) Changing high current is too near a (d) Current flows through the groundi.
168 CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
169 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode.
170 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock L L Oscillation does not stop. MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.
171 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.
172 CHAPTER 7 CLOCK GENERATOR Table 7-3. Maximum Time Required for CPU Clock Switchover × × ×× 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 CSS 0 0 0 0 × PCC0 PCC1 PCC2 1 × 1 PCC0 CSS PCC2 PCC1 0 0 0 0 1 1 0.
173 CHAPTER 7 CLOCK GENERATOR V DD RESET Interrupt Request Signal System Clock CPU Clock Wait (26.2 ms : 5.0 MHz) Internal Reset Operation Minimum Speed Operation Maximum Speed Operation Subsystem Clock Operation f XX f XX f XT f XX High-Speed Operation 7.
174 [MEMO].
175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated in the µ PD78054, 78054Y Subseries This chapter explains 16-bit timer/event counter. Before that, the timers incorporated into the µ PD78054, 78054Y Subseries and related circuits are outlined below.
176 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operations Interval timer 2 channels Note 3 2 channels 1 channel Note 1 1 channel Note 2 External event counter √√ —— Ti.
177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width me.
178 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse .
179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware.
180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram Remark The circuitry enclosed by the dotted line is the output control circuit.
181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0 (CRC0).
182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Caution If the valid edge of the TIO0/P00 pin is input while CR01 is read, CR01 does not perform the capture operation and retains the current data. However, the interrupt request flag (PIF0) is set. (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses.
183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 < 7 > 65 43 21 0 Symbol TCL0 TCL03 TCL02 TCL01 TCL00 00 00 f XT (32.768 kHz) 01 01 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 01 10 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.
184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 00 00 TMC03 TMC02 TMC01 OVF0 76 54 32 1 < 0 > Symbol TMC0 FF48H 00H R/W Address After Reset R/W OVF0 16-Bit Timer Register Overflow Detection 0 Overflow .
186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H.
187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 7 <6> <5> 4 <3> <2> 1 <0> Symbol TOC0 FF4EH 00H R/W Address After Reset R/W TOE0 16-Bit Ti.
188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 76 54 32 10 Symbol PM3 FF23H FFH R/W Address After Reset R/W PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units.
189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ES31 ES30 ES21 ES20 ES11 ES10 0 0 76 54 32 10 Symbol INTM0 FFECH 00H R/W Address After Reset R/W ES11 INTP0 Valid Edge Selection ES10 0 Falling edge 0 0 Rising.
190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0 SCS1 SCS0 76 54 32 10 Symbol SCS FF47H 00H R/W Address After Reset R/W SCS1 SCS0 00 01 10 11 INTP0 Sampling Clock Selection MCS = 1 MCS = 0 f XX /2 N f X /2 7 (39.1 kHz) f XX /2 7 f X /2 8 (19.5 kHz) f X /2 5 (156.
191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0/1 0/1 0 CRC02 CRC01 CRC00 CRC0 CR00 set as compare register 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer.
192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 16-Bit Capture/Compare Register 00 (CR00) 16-Bit Timer Register (TM0) Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 TI00/P00/INTP0 OVF0 Clear Circuit INTTM00 Figure 8-11. Interval Timer Configuration Diagram Figure 8-12.
193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 000.
194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOE0 TOC01 LVR0 LVS0 TOC04 OSPE OSPT TOC0 1 0/1 × × × × × 0 TO0 Output Enabled Specifies Active Level CRC00 CRC01 CRC02 CRC0 0 0/1 0/1 0 0 0 0 0 CR00 set as compare register TMC0 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8-13.
195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PD78054, 78054Y µ TO0/P30 V SS 8.2 k Ω 8.2 k Ω 100 pF 22 k Ω +110 V 2SC 2352 47 k Ω 47 k Ω 47 k Ω 0.
196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 1 0 0 0 TOE0 TOC01 LVR0 LVS0 Inversion of output on match of TM0 and CR00 TOC04 OSPE OSPT TO0 Output Enabled Specified TO0 output F/F initial .
197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode CRC0 0 0/1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as capture register 8.
198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) OVF0 INTP0 Internal Bus TI00/P00/INTP00 Coun.
199 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 .
200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) × t (10000H – D1 + D2) × t (10000H – D1 + (D2 + 1)) × t (D3 – D2) × t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8-21.
201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 .
202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1-D0) × t (10000H-D1 + D2) × t (D3-D2) × t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8-23.
203 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 0 .
204 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0/1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register TMC0 0 0/1 1 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear & start with match of TM0 and CR00 8.
205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TI00 Pin Input TM0 Count Value CR00 INTTM0 N 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 INTP0 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) Internal Bus TI00 Valid Edge OVF0 Figure 8-27.
206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 0 0 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial .
207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR00 INTTM0 TO0 Pin Output 0000 0001 0002 N-1 N 0000 0001 0002 N-1 N 0000 N Figure 8-30.
208 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial .
209 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 OSPT INTTM00 TO0 Pin Output 0000 0001 N N+1 0000 N-1 N M-1 M 0000 0001 0002 N M N M N M N M Set 0CH to TMC0 (TM0 count start) Figure 8-32.
210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as compare register TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 LVS0 OSPT OSPE TOC0.
211 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value CR01 Set Value CR00 Set Value INTTM01 TI00 Pin Input INTTM00 TO0 Pin Output 0000 0001 0000 N N+1 N+2 M–2 M–1 M M+1 M+2 M+3 N M N M N M N M Set 08H to TMC0 (TM0 count start) Figure 8-34.
212 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 Count Value X-1 X FFFFH 0000H 0001H 0002H M N Timer Start Count Pulse TM0 Count Value 0000H 0001H 0002H 0003H 0004H 8.
213 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse TM0 Count Value Edge Input Interrupt Request Flag Capture Read Signal CR01 Captured Value Capture Operation Ignored X N+1 N N+1 N+2 M M+1 M+2 (4) C.
214 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH.
215 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available.
216 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Mi.
217 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
218 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals.
219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output.
220 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations The 8-bit timer/event counters 1 and 2 consist of the following hardware.
221 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-1. 8-Bit Timer/Event Counters 1 and 2 Block Diagram Note Refer to Figures 9-2 and 9-3 for details of 8-bit timer/event counters 1 and 2 output control circuits 1 and 2, respectively.
222 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Remarks 1.
223 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value.
224 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-4. Timer Clock Select Register 1 Format Caution When rewriting TCL1 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
225 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2.
227 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
228 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 a.
229 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS.
230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-7. 8-Bit Timer/Event Counter 2 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS.
231 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2).
232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare register 10 and 20 (CR10, CR20).
233 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Square-Wave Output Operation Timing Note The initial value of TO1 pin output can be set with the bits 2 and 3 (LVR1, LVS1) of 8-bit timer output control register (TOC1).
234 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set.
235 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum .
236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2- channel 8-bit timer registers 1 and 2 (TM1 and TM2).
237 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10, CR20). When setting the count value, set the value of higher 8 bits to CR20 and the value of lower 8 bits to CR10.
238 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-13. Square-Wave Output Operation Timing Note The initial value of TO2 pin output can be set with the bits 6 and 7 (LVR2, LVS2) of 8-bit timer output control register (TOC1).
239 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit compare register 10 and 20 setting The 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out.
240 [MEMO].
241 CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.
242 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration Counter 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.
243 CHAPTER 10 WATCH TIMER TMC21 Prescaler Selector INTWT 5-Bit Counter f W 2 14 f W 2 13 INTTM3 To 16-Bit Timer/ Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TM.
244 CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
245 CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction.
246 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval.
247 CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time).
248 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.
249 CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Timer clock select register 2 (TCL2) Watchdog timer mode control register (WDTM) Figure 11-1.
250 CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
251 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
252 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 11-3.
253 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway.
254 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
255 CLOE PCL/P35 Pin Output ** CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI.
256 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Internal Bus f XX f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XT CLOE TCL03 TCL02 TCL01 TCL00 P35 Output Latch Synchronizing Circuit 4 PM35 Selector Timer Clock Select Register 0 Port Mode Register 3 PCL / P35 12.
257 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock.
258 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CLOE <7> TCL06 6 TCL05 TCL04 4 TCL03 3210 FF40H Address TCL0 Symbol TCL02 TCL01 TCL00 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 1 Other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 TCL03 TCL02 TCL01 f XT (32.
259 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5.
260 [MEMO].
261 Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.
262 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
263 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
264 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3210 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R/W R/W PM3n 0 1 P3n Pin Input /Output Mode Selection (n=0 to.
265 CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
266 CHAPTER 14 A/D CONVERTER ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Selector A /D Converter Mode Register 3 Trigger Enable ES40, ES41 Note 3 Sample & Hold Circuit .
267 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB).
268 CHAPTER 14 A/D CONVERTER (7) AV REF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV REF0 and AV SS .
269 CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter .
270 CHAPTER 14 A/D CONVERTER Figure 14-3. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.
271 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports.
272 CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction.
273 CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
274 CHAPTER 14 A/D CONVERTER Figure 14-6. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software.
275 CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.
276 CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode Select one analog input channel from ANI0 to ANI7 with A/D converter input select register (ADIS) and A/D converter mode register (ADM), and start A/D conversion. The following two ways are available to start A/D conversion.
277 CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
278 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock.
279 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF0 and ANI0 to ANI7.
280 CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. If an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may have been set immediately before the ADM rewrite.
281 CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method.
282 CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 15-1.
283 CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values to determine analog voltage output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions.
284 CHAPTER 15 D/A CONVERTER 0 7 0 6 DAM5 DAM4 4 0 3 2 <1> <0> FF98H Address DAM Symbol 0 DACE1 DACE0 5 00H After Reset R/W R/W DAM5 0 1 D/A Converter Channel 1 Operating Mode Normal mode .
285 CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D/A converter mode register (DAM), respectively.
286 CHAPTER 15 D/A CONVERTER PD78054, 78054Y ANOn R R 1 C • The input impedance of the buffer amplifier is R 1 . • If R 1 is not connected, the output becomes undefined when RESET is low.
287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) The µ PD78054 subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes.
289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1).
290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware.
291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-2. Serial Interface Channel 0 Block Diagram Remark Output Control performs selection between CMOS output and N-ch open-drain output.
292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled also by software. In the SBI mode, this latch is set upon termination of the 8th serial clock.
294 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0.
295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2.
296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal.
297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-4. Serial Operating Mode Register 0 Format (2/2) Notes 1. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register (SINT) to 0. 2.
298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-5. Serial Bus Interface Control Register Format (2/2) Note The busy mode can be canceled by start of serial interface transfer.
300 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 16.
302 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.
303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock.
306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus.
307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function.
308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports.
309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.
310 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output).
311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses 8-bit data following bus release and command signals is defined as an “address”.
312 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands Figure 16-17.
313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver.
314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception.
315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT).
316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. The shaded area is used in the SBI mode.
317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Note Busy mode can be cleared by start of serial interface transfer. However, BSYE flag is not cleared to 0.
318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2.
319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) Figure 16-21.
320 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-22. ACKT Operation Caution Do not set ACKT before termination of transfer. SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set.
321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer (b) When set after completion of transfer (c) When ACKE = .
322 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 (b) When ACK signal is output after 9th clock of SCK0 (c) Clear timing when transfer start is instructed in BUSY Figure 16-25.
323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) <1 > ACKE = 1 <2 > ACKT set Table 16-3. Various Signals in SBI Mode (1/2) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal CMD signal is output to indicate that transmit data is an address.
324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal Synchronous clock to output address/command/ data, ACK signal, synchronous BUSY signal, etc.
325 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master .
326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware.
327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1) 1 2 3 4 5 6 7 8 9 SCK0 Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK.
328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-28. Command Transmission from Master Device to Slave Device 123456789 SCK0 Pin C7 C6 C5 C4 C3 C2 C1 C0 ACK BUSY SB0 (SB1) Pi.
329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-29. Data Transmission from Master Device to Slave Device 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB.
330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) Figure 16-30. Data Transmission from Slave Device to Master Device 123456789 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin P.
331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
332 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (10) Discrimination of slave busy state When device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation.
333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (1) Register setting The 2-wire serial I/O mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT).
335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2.
337 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock.
338 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
339 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78054 Subseries) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software.
340 [MEMO].
341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) The µ PD78054Y subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes.
343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus format.
344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware.
345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-2. Serial Interface Channel 0 Block Diagram Remark Output Control selects between CMOS output and N-ch open drain output.
346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (6) Interrupt request signal generator This circuit controls interrupt request signal generation.
348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0.
349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2.
350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal.
351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for transmission.
352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT.
354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction.
355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 0.
356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •I 2 C (Inter IC) bus mode 17.
357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K series.
358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock.
360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus.
361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Notes 1. Bit 6 (COI) is a read-only bit.
363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2.
365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock.
366 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices.
368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal.
370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer.
371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data.
372 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (3) Register setting The I 2 C mode is set with the serial operating mode register 0 (CSIM0), t he serial bus interface control register (SBIC), and the interrupt timing specify register (SINT).
373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1.
374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) R/W ACKE Acknowledge Signal Automatic Output Control Note 1 0 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting data. Note 2 1 Enabled.
375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction.
376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 17-4. Table 17-4.
377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin.
378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (7) Error detection In the I 2 C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device.
379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Ad.
380 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2 of 3) (b) Data L L L L 1 D5 D4 .
381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3 of 3) (c) Stop Condition L L 1 .
382 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1 of 3) (a) Start Condition to Ad.
383 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2 of 3) (b) Data L L L L H H L 1 .
384 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3 of 3) (c) Stop Condition L L 1 .
385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal.
386 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction.
387 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed.
388 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1).
389 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.
390 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock.
391 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78054Y Subseries) Figure 17-29. Logic Circuit of SCL Signal Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit.
392 [MEMO].
393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode •.
394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1.
395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram RE ARLD ERCE ERR TRF STRB BUSY 1 BUSY 0 Internal Bus Automatic Data Transmit/Receive Control Register Se.
396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock.
397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1.
398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3.
399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
400 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic transmit/receive enable/disable, the operating mode, strobe output enable/ disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection.
401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction.
402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Notes 1. The interval is dependent only on CPU processing.
404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.
406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K series.
407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units.
408 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus.
409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software.
410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY 1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as port function.
411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H. Notes 1. Bits 3 and 4 (TRF and ERR) are Read-Only bits.
412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
414 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address.
417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units.
418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interva.
419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD=0, RE=1) in basic transmit/receive mode, buffer RAM operates as follows.
420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception (c) Completion .
421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.
422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify.
423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-13 (a)) After any da.
424 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point (c) Completion of transmission Transm.
425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1).
426 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specif.
427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD=1, RE=0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (Refer to Figure 18-16 (a)) After any d.
428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes (c) 7th byte transmis.
429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0.
430 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization Control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving.
431 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19.
432 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20. Busy Signal and Wait Cancel (when BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device.
433 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timings when Using Busy & Strobe Control Option (BUSY0 = 0) Caution When TRF is cleared, the SO1 pin becomes low level.
434 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock.
435 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
436 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the auto send and receive function is operated by the internal clock, interval timing by CPU processing is as follows.
437 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is set.
438 [MEMO].
439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
440 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1.
441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1. Serial Interface Channel 2 Block Diagram Note See Figure 19-2 for the baud rate generator configuration.
442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2. Baud Rate Generator Block Diagram TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Cou.
443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers.
445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. 2.
446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmitter is used.
447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 19-6.
449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f XX /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.
450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.
453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
454 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.
455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Caution The serial transmit/receive operation must be stopped before changing the operating mode.
456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated.
457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.
459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
460 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame consists of the following bits.
462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS).
464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When the bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM.
465 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interrupt request (INTSER) is generated.
466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared and the transmission operation is stopped during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 before executing the next transmission.
467 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc.
468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H.
470 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0000 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0101 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0110 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.
471 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the 3-wire serial I/O mode is used, set BRGC as described below. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
472 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
473 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus.
474 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Limitations when UART mode is used In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception error interrupt request (INTSER) has occurred and then cleared.
475 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 • In case of parity error Disable the receive buffer register (RXB) from being read for a certain time (T1 + T2 in Figure 19-15) after the reception error interrupt request (INTSER) has occurred. Figure 19-15.
476 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] Occurrence of INTSER EI Main processing 7 clocks of CPU clock (MIN.) (time from interrupt request to servicing) Instructions equivalent to 2205 CPU clocks (MIN.
477 CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt requests or external interrupt request generation, then output externally.
478 CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1.
479 CHAPTER 20 REAL-TIME OUTPUT PORT Operating Mode Register to be Manipulated 4 Bits × 2 Channels 8 Bits × 1 Channel (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2.
480 CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output.
481 CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger.
482 CHAPTER 20 REAL-TIME OUTPUT PORT [MEMO].
483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status.
484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration Interrupt sources includes total of 22 non-maskbale, maskable, software interrupts (refer to Table 21-1 ).
485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Interrupt Source Name Trigger Reference time interval signal from watch timer Generation of 16-bit timer register, c.
486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal Bus IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Sampling Clock Edge Detector S.
487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal Bus Priority Control Circuit Vector Table Address Generator Interrupt Request External Interrupt Mode Register (INTM0, INTM1) Edge Detector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 21-1.
488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions.
489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PIF6 Symbol IF0L <6> PIF5 <5> PIF4 <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> TMIF4 Address FFE0H 00H After.
490 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PMK6 Symbol MK0L <6> PMK5 <5> PMK4 <4> PMK3 <3> PMK2 <2> PMK <1> PMK <0> TMMK4 Address FFE4H FFH After R.
491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS <7> PPR6 Symbol PR0L <6> PPR5 <5> PPR4 <4> PPR3 <3> PPR2 <2> PPR1 <1> PPR0 <0> TMPR4 Address FFE8H FFH After.
492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES.
493 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES.
494 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FF47H 00H After Reset R/W R/W 0 0 1 1 INTP0 Sampling Clock Selection f xx /2 N f xx /2 7 f xx /2 5 f xx /2 6 SCS1 7 0 Symbol SCS 6 0 5 0 4 0 3 0 2 0 1 SCS1 0 SCS0 0 1 0 1 SCS0 MCS = 1 MCS = 0 f x /2 7 (39.
495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS t SMP Sampling Clock INTP0 PIF0 "L" Because INTP0 level is not high level at the time of sampling, PIF0 flag remains at low level. t SMP Sampling Clock INTP0 PIF0 <1> <2> Because the sampled INTP0 level is high level twice in succession in <2>, PIF0 flag is set to 1.
496 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
497 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state.
498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt request selected)? Interrupt request generation WDT inter.
499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt se.
500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm ×× IF : Interrupt request flag ×× MK : Interrupt mask flag ×× PR : Priority specify f.
502 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) Remark 1 clock : (f CPU : CPU clock) Figure 21-15.
503 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution.
504 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing EI INTxx (PR=1) INTyy (PR=0) IE=0 EI RETI INTxx Servicing INTzz (PR=0) IE=0 EI RETI INTyy Servicing IE=0 RETI INTzz Servicing Figure 21-16.
505 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing INTxx Servicing INTyy Servicing INTxx (PR=0) 1 Instruction Execution IE=0 INTyy (PR=0) IE=0 RETI RETI EI Figure 21-16.
506 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve In some cases, the acknowledgment of the interrupt request is reserved even an interrupt request is generated during processing of the instruction until the execution of the next instruction is completed.
507 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal bus MK IF Test input signal Standby release signal 21.5 Test Functions Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4, the corresponding test input flag is set (1) and a standby release signal is generated.
508 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input.
509 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 0 Symbol KRM 6 0 5 0 4 0 3 0 2 0 <1> KRMK <0> KRIF Address FFF6H 02H When Reset R/W R/W 0 1 Key Return Signal Not detected Detected (port 4 fa.
510 [MEMO].
511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6.
512 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map when Using External Device Expansion Function (1.
513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (2/4) (c) Memory map of µ PD78P054, 78P058, (d) Memory map of µ PD78P058, 78P0.
514 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (3/4) (e) Memory map of µ PD78P058, 78P058Y when the µ PD78056, 78056Y and int.
515 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (4/4) (f) µ PD78058, 78058Y, 78P058, 78P058Y Memory (g) µ PD78058, 78058Y, 78P.
516 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 7 0 Symbol MM 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H 10H When Reset R/W R/W MM2 MM1 MM0 Single-chip/ Memory Expansion Mode Selection P40-.
517 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 1 1 48 Kbytes 56 Kbytes 1 1 0 1 0 0 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H Note After Reset R/W R/W Internal RO.
518 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin.
519 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, P.
520 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) .
521 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1).
522 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1,.
523 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION µ PD43256B CS OE A0-A14 I/O1-I/O8 WE Address Bus V DD µ PD78054 µ PD74HC573 LE D0-D7 Q0-Q7 OE RD WR A8-A14 ASTB AD0-AD7 Data Bus V DD 22.4 Example of Connection with Memory This section provides µ PD78054 and external memory connection examples in Figure 22-8.
524 [MEMO].
525 CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode.
526 CHAPTER 23 STANDBY FUNCTION Address FFFAH 04H After Reset R/W R/W 0 0 0 0 1 Selection of Oscillation Stabilization Time when STOP Mode is Released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx OSTS2 7 0 Symbol OSTS 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 0 0 1 1 0 Other than above OSTS1 MCS = 1 MCS = 0 2 12 /f x (819 s) 2 14 /f x (3.
527 CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below.
528 CHAPTER 23 STANDBY FUNCTION HALT Instruction Interrupt Request Wait Standby Release Signal Operating Mode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following four types of sources.
529 CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input When a RESET signal is input, the HALT mode is released, and as is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Remarks 1.
530 CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
531 CHAPTER 23 STANDBY FUNCTION STOP Instruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status Operating Mode Oscillation Operationg Mode STOP Mode Oscillation Stop Oscillation Standby Release Signal Clock Interrupt Request (2) STOP mode release The STOP mode can be cleared with the following three types of sources.
532 CHAPTER 23 STANDBY FUNCTION RESET Signal Operating Mode Clock Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Operating Mode Oscillation Wait (2 17 /f x : 26.2 ms) STOP Instruction Oscillation (c) Release by RESET input When a RESET signal is input, the STOP mode is released.
533 RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over- flow Reset Signal Interrupt Function CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal.
534 CHAPTER 24 RESET FUNCTION RESET Internal Reset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Proc.
535 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (1/2) Hardware Status after Reset Program counter (PC) Note1 The contents of reset vector tables (0000H and 0001H) are set.
536 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (2/2) Hardware Status after Reset Watch timer Mode control register (TMC2) 00H Clock select register (TCL2) 00H Mode register (WDT.
537 Match CORENn CORSTn Program counter (PC) Comparator Correction address register (CORADn) Internal bus Correction control register Correction branch request signal (BR !7FDH) CHAPTER 25 ROM CORRECTION 25.
538 CHAPTER 25 ROM CORRECTION FF3AH/FF3BH 0000H Symbol 15 CORAD0 0 Address FF38H/FF39H State after reset 0000H R/W R/W CORAD1 R/W (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM.
539 CHAPTER 25 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH State after reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address r.
540 CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM TM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well.
541 CHAPTER 25 ROM CORRECTION No Yes Initialization Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Is ROM correction used ? Note ROM correction Main program (2) Assemble in advance the initialization routine as shown in Figure 25-6 to correct the program.
542 CHAPTER 25 ROM CORRECTION No Yes Internal ROM program start Does fetch address match with correction address? Set correction status flag Correction branch (branch to address F7FDH) Correction program execution ROM correction Figure 25-7.
543 CHAPTER 25 ROM CORRECTION ADD A, #2 BR !1002H BR !F702H ADD A, #1 MOV B, A 0000H 0080H Program start 1000H 1002H Internal ROM Internal expansion RAM F400H F702H F7FDH F7FFH (1) (2) (3) EFFFH 25.
544 CHAPTER 25 ROM CORRECTION Correction place Internal ROM Internal ROM JUMP FFFFH F7FFH F7FDH xxxxH 0000H (1) (2) (3) BR !JUMP Correction program 25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used.
545 CHAPTER 25 ROM CORRECTION Internal ROM Correction place 1 Internal ROM JUMP Internal ROM (1) (2) (3) (4) (5) (6) (7) (8) FFFFH F7FFH F7FDH yyyyH xxxxH 0000H BR !JUMP Destination judge program Correction program 2 Correction program 1 Correction place 2 Figure 25-10.
546 CHAPTER 25 ROM CORRECTION 25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored.
547 CHAPTER 26 µ PD78P054, 78P058 The µ PD78054, 78054Y subseries include the µ PD78P054, 78P058, 78P058Y as PROM versions. For purposes of simplification, in this chapter, the description of the µ PD78P058 applies to both the µ PD78P058 and 78P058Y.
548 CHAPTER 26 µ PD78P054, 78P058 Notes 1. The internal ROM and internal high-speed RAM capacities are set as follows by RESET input: Internal PROM: 32K bytes ( µ PD78P054), 60K bytes ( µ PD78P058) Internal high-speed RAM: 1024 bytes 2. The internal expansion RAM is set to 1024 bytes by RESET input.
549 CHAPTER 26 µ PD78P054, 78P058 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H C8H After Reset R/W R/W 1 Internal ROM Capacity selection 32 Kbytes ROM3 0 ROM2 0 ROM1 .
550 CHAPTER 26 µ PD78P054, 78P058 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H CFH After Reset R/W R/W 1 Internal ROM Capacity selection 32 Kbytes ROM3 0 ROM2 0 ROM1 .
551 CHAPTER 26 µ PD78P054, 78P058 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal extension RAM capacity selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 10 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 11 00 26.
552 CHAPTER 26 µ PD78P054, 78P058 26.4 PROM Programming The µ PD78P054 and 78P058 incorporate a 32-Kbyte and 60-Kbyte PROM as program memory, respectively. To write a program into the µ PD78P054 or 78P058 PROM, make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as specified.
553 CHAPTER 26 µ PD78P054, 78P058 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
554 CHAPTER 26 µ PD78P054, 78P058 Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1-ms program pulse Verify 4 Bytes Pass Address = N? No Pass V DD = 4.
555 CHAPTER 26 µ PD78P054, 78P058 Figure 26-5. Page Program Mode Timing Page Data Latch Page Program Program Verify Data Input Data Output A2-A16 A0, A1 D0-D7 V PP V DD V PP V DD +1.
556 CHAPTER 26 µ PD78P054, 78P058 Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.5 to 5.
557 CHAPTER 26 µ PD78P054, 78P058 Figure 26-7. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing V PP . 2. V PP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.
558 CHAPTER 26 µ PD78P054, 78P058 Address Input A0-A16 CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 26.4.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin.
559 CHAPTER 26 µ PD78P054, 78P058 26.5 Erasure Procedure ( µ PD78P054KK-T and 78P058KK-T Only) With the µ PD78P054KK-T or 78P058KK-T, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory.
560 [MEMO].
561 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µ PD78054 and 78054Y subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series User’s Manual, Instruction (U12326E) .
562 CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail).
563 CHAPTER 27 INSTRUCTION SET 27.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register .
564 CHAPTER 27 INSTRUCTION SET 27.2 Operation List Clock Flag Note 1 Note 2 ZA C C Y r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 12 – .
565 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp.
566 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A, CY ← A – byte ×× × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×× × A, r Note 3 2 4 – A, CY ←.
567 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A ← A ∨ byte × saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte × A, r Note 3 24 – A ← A ∨ r × r, A 2 4 .
568 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y ADDW AX, #word 3 6 – AX, CY ← AX + word ×× × SUBW AX, #word 3 6 – AX, CY ← AX – word ×× × CMPW AX, #word 3 6 – AX –.
569 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y CY, saddr.bit 3 6 7 CY ← CY ∧ (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY ∧ sfr.bit × AND1 CY, A.bit 2 4 – CY ← CY ∧ A.bit × CY, PSW.bit 3 – 7 CY ← CY ∧ PSW.bit × CY, [HL].
570 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y (SP – 1) ← (PC + 3) H , (SP – 2) ← (PC + 3) L , PC ← addr16, SP ← SP – 2 (SP – 1) ← (PC + 2) H , (SP – 2) ← (PC +.
571 CHAPTER 27 INSTRUCTION SET sfr.bit, $addr16 4 – 12 A.bit, $addr16 3 8 – PSW.bit, $addr16 4 – 12 ×× × [HL].bit, $addr16 3 10 12 + n + m B, $addr16 2 6 – DBNZ C, $addr16 2 6 – saddr. $addr16 3 8 10 Clock Flag Note 1 Note 2 ZA C C Y saddr.
572 CHAPTER 27 INSTRUCTION SET 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, .
573 CHAPTER 27 INSTRUCTION SET Second Operand [HL + byte] #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None First Operand [HL + C] A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC X.
574 CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand 1st Operand AX ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVW Note .
575 CHAPTER 27 INSTRUCTION SET AX !addr16 !addr11 [addr5] $addr16 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand B.
576 [MEMO].
577 APPENDIX A DIFFERENCES BETWEEN µ PD78054, 78054Y SUBSERIES AND µ PD78058F, 78058FY SUBSERIES Table A-1 shows the major differences between the µ PD78054, 78054Y Subseries and µ PD78058F, 78058FY Subseries.
578 APPENDIX A DIFFERENCES BETWEEN µ PD78054, 78054Y SUBSERIES AND µ PD78058F, 78058FY SUBSERIES Table A-1. Majo r differences between µ PD78054, 78054Y Subseries and µ PD78058F, 78058FY Subseries.
579 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78054 and 78054Y subseries.
580 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS PROM programming tool • PG-1500 controller Language processing softwar.
581 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Remark The parts s hown within broke n lines differ depending on the developing environment.
582 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process. Provided with functions to automatically perform generation of symbol table, optimizing processing of branch instructions, etc.
583 APPENDIX B DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and OS used. µ Sxxxx RA78K0 µ Sxxxx CC78K0 µ Sxxxx DF78078 µ Sxxxx CC78K0-L xxxx Host Machine OS Supply Media AA13 PC-9800 series Japanese Windows Notes 1, 2 3.
584 APPENDIX B DEVELOPMENT TOOLS PG-1500 PROM Programmer PA-78P054GC PA-78P054GK PA-78P054KK-T PROM Programmer Adapter A PROM programmer that, by connecting the attached board and separately available.
585 APPENDIX B DEVELOPMENT TOOLS IE-78K0-NS Note In-circuit Emulator IE-70000-MC-PS-B Power Supply Adapter IE-70000-98-IF-C Note Interface Adapter IE-70000-CD-IF Note PC Card Interface IE-70000-PC-IF-.
586 APPENDIX B DEVELOPMENT TOOLS An in-circuit emulator to debug hardware and software when developing application systems that use the 78K/0 Series. Supports integrated debugger (ID78K0). Used in combination with an interface adapter to connect to an emulation probe and the host machine.
587 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 Capable of debugging in C source level or assembler level while simulating System Simulator the operation of the target system on the host machine.
588 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0-NS Note Integrated debugger (supporting in-circuit emulator IE-78K0-NS) ID78K0 Integrated Debugger (supporting in-circuit emulator IE-78001-R-A) Note Under development Remark xxxx in the part number differs depending on the host machine and OS used.
589 APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs are supported for IBM PC. Table B-1. OS for IBM PC OS Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note IBM DOS™ J5.02/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.
590 APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawing (For Reference Only) A F D 1 No.1 pin index E EV-9200GC-80 B C M N O L K S R Q P I H J G EV-9200GC-80-G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M O N P Q R S 18.
591 APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprint (For Reference Only) A F D E C B G J K L H I 0.026 × 0.748=0.486 0.026 × 0.748=0.486 EV-9200GC-80-P1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L 19.7 15.0 15.0 19.7 6.0 ± 0.05 6.
592 APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawing (For Reference) (unit: mm) ITEM MILLIMETERS INCHES b 0.25 0.010 c 5.3 0.209 a 0.5x19=9.5±0.10 0.020x0.748=0.374±0.004 d 5.3 0.209 h 1.85±0.2 0.
593 APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µ PD78054, 78054Y Subseries, the following embedded software is available.
594 APPENDIX C REGISTER INDEX Real-time OS (2/2) MX78K0 A µ ITRON specification subset OS. Added with MX78K0 nucleus. OS Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one executed next.
595 APPENDIX D REGISTER INDEX D.1 Register Index 8-bit timer mode control register (TMC1) .......................................................................................................... 22 5 8-bit timer output control register (TOC1) ......
596 APPENDIX D REGISTER INDEX [I] IF0H: Interrupt request flag register 0H ................................................................................................... 4 89 IF0L: Interrupt request flag register 0L ..............................
597 APPENDIX D REGISTER INDEX PR0H: Priority specify flag register 0H ...................................................................................................... 4 91 PR0L: Priority specify flag register 0L .................................
598 [MEMO].
599 APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version Revised Chapters 2nd P40/AD0-P47/AD7 pin I/O circuit types were changed. CHAPTER 2 Pin Functions Connection method of unused AV REF1 pin was changed.
600 APPENDIX E REVISION HISTORY Edition Major revisions from previous version Revised Chapters 4th Addition of following package to all devices: Throughout edition • 80-pin plastic QFP (14 × 14 mm, resin thickness: 1.
601 APPENDIX E REVISION HISTORY Edition Major revisions from previous version Revised Chapters 4th The µ PD78052(A),78053(A), and 78054(A) were added to the Throughout edition applicable types.
602 [MEMO].
Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.
An important point after buying a device NEC uPD78053Y (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought NEC uPD78053Y yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data NEC uPD78053Y - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, NEC uPD78053Y you will learn all the available features of the product, as well as information on its operation. The information that you get NEC uPD78053Y will certainly help you make a decision on the purchase.
If you already are a holder of NEC uPD78053Y, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime NEC uPD78053Y.
However, one of the most important roles played by the user manual is to help in solving problems with NEC uPD78053Y. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device NEC uPD78053Y along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
