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User’s Manual µ µ µ µ PD789800 µ µ µ µ PD78F9801 µ µ µ µ PD789800 Subseries 8-Bit Single-Chip Microcontrollers Printed in Japan Document No.
User’s Manual U12978E J3V0UD 2 [MEMO].
User’s Manual U12978E J3V0UD 3 NOTES FOR CMOS DE VICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation.
User’s Manual U12978E J3V0UD 4 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. The information in this document is current as of September, 2002.
User ’ s Manual U12978EJ3V0UD 5 Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development en.
User’s Manual U12978E J3V0UD 6 Major Revisions in This Edition Page Contents Deletion of CU-t ype and GB-3B S type pac kages Throughout Deletion of indicati on “under development ” for µ PD78F9801 p. 21 Modific ation of operat ing ambient temperature when f lash memory is writ ten in 1.
User’s Manual U12978E J3V0UD 7 INTRODUCTION Readers This manual is intended for users w ho wish to understand the functions of the µ PD789800 Subseries and who design and develop its application systems and programs.
User’s Manual U12978E J3V0UD 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not m arked as such.
User’s Manual U12978E J3V0UD 9 Other Related Documents Document Nam e Document No. SEMI CONDUCTOR SELECT ION GUIDE - P roducts and Packages - (CD-ROM) X13769X Semic onductor Devi ce Mounti ng Techno.
User’s Manual U12978E J3V0UD 10 TABLE OF CONTENTS CHAPTER 1 GENERAL .......................................................................................................... ................ 21 1.1 Features .........................................
User’s Manual U12978E J3V0UD 11 3.3.4 Register addressing ....................................................................................................... ...............50 3.4 Operand Address Addressing.......................................
User’s Manual U12978E J3V0UD 12 CHAPTER 7 WATCHDOG TIMER .................................................................................................. ...... 91 7.1 Watchdog Timer Functions ......................................................
User’s Manual U12978E J3V0UD 13 11.4.2 Maskable interrupt acknowledgment operation ........................................................................... 173 11.4.3 Multiplexed interrupt servicing ...............................................
User’s Manual U12978E J3V0UD 14 B.1 Register Index (Alphabetic Order of Regist er Name) ........................................................... 229 B.2 Register Index (Alphabetic Order of Regist er Symbol) .......................................
User’s Manual U12978E J3V0UD 15 LIST OF FIGURES (1/4) Figure No. Title Page 2-1 Pin I/O Circuits ............................................................................................................ ............................. 34 3-1 Memory M ap ( µ PD789800) .
User’s Manual U12978E J3V0UD 16 LIST OF FIGURES ( 2/4) Figure No. Title Page 6-7 Interval Timer Operation Timing of 8-Bit Tim er/Event Counter 01 ............................................................ 8 6 6-8 Timing of External Event Counter Operation (with Rising Edge Specified) .
User’s Manual U12978E J3V0UD 17 LIST OF FIGURES (3/4) Figure No. Title Page 8-31 Flow Chart of NRZI Encoder O peration ....................................................................................... .......... 150 8-32 Tim ing of Bit Stuffing/Strip Controller Operation .
User’s Manual U12978E J3V0UD 18 LIST OF FIGURES ( 4/4) Figure No. Title Page 14-3 Exam ple of Connection with Dedicated Flash Programmer ................................................................... 193 14-4 V PP Pin Connection Example .......
User’s Manual U12978E J3V0UD 19 LIST OF TABLES (1/2) Table No. Title Page 2-1 Type of Pin I/O Circuit Recommended Connection of Unused Pins ........................................................ 33 3-1 Vector Table ................................
User’s Manual U12978E J3V0UD 20 LIST OF TABLES (2/2) Table No. Title Page 12-3 STO P Mode Operation Status ................................................................................................. ............... 183 12-4 O peration After Release of STOP Mode .
User’s Manual U12978E J3V0UD 21 CHAPTER 1 GENERAL 1.1 Features • On-chip USB functions • Implements a USB (U niversal Serial Bus) by connecting to Hub and Host. • Transfer speed: 1.5 Mbps (at 6.0 MHz operation w ith system clock) • On-chip regulator • Controls the USB port voltage by using a bus power supply (V REG = 3.
CHAPTER 1 GE NERAL User’s Manual U12978E J3V0UD 22 1.4 P in Configuration (Top View) • 44-pin plastic LQFP (10 × 10) µ PD789800GB- ××× -8ES, µ PD78F9801GB-8ES P04 P03 P02 P01 P00 V DD1 V SS1.
CHAPTER 1 GE NERAL User’s Manual U12978E J3V0UD 23 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
CHAPTER 1 GE NERAL User ’ s Manual U12978EJ3V0UD 24 The major differences between subseries are shown below . Series for General-Purpose and LCD Drive Timer V DD Function Subseries ROM Capacity (Bytes ) 8-Bit 16-Bit Watc h WDT 8-Bit A/D 10-Bit A/D Seria l Interfa ce I/O MIN.
CHAPTER 1 GE NERAL User ’ s Manual U12978EJ3V0UD 25 Series for ASSP Timer V DD Function Subseries ROM Capacity (Bytes ) 8-Bit 16-Bit Watc h WDT 8-Bit A/D 10-Bit A/D Seria l Interfa ce I/O MIN.Value Remarks USB µ PD789800 8 K 2 ch −− 1 ch −− 2 ch (USB: 1ch) 31 4.
CHAPTER 1 GE NERAL User ’ s Manual U12978EJ3V0UD 26 1.6 Block Diagram Key return 0 8-bit timer 00 8-bit timer/event counter 01 Watchdog timer Regulator USB function 0 Serial interface 1 Interrupt co.
CHAPTER 1 GE NERAL User’s Manual U12978E J3V0UD 27 1.7 Functions Product Item µ PD789800 µ PD78F9801 Intern al memo ry ROM Mask ROM 8 KB Flash memory 16 KB High-speed RAM 256 bytes Minimum instruc tion exec ution ti me 0.
User’s Manual U12978E J3V0UD 28 CHAPTER 2 PIN FUNCTIONS 2.1 Lis t of Pin Functions (1) Port pins Pin Name I/O Function After Res et Alt ernate Function P0 0 to P0 7 I/O Port 0 8-bit I/ O port Input/out put can be s pecifi ed in 1-bit unit s.
CHAPTER 2 P IN FUNCTI ONS User’s Manual U12978E J3V0UD 29 (2) Non-port pins Pin Name I/O Function After Res et Alternat e Function INTP0 Input External interrupt reques t input f or which v alid edg.
CHAPTER 2 P IN FUNCTI ONS User’s Manual U12978E J3V0UD 30 2.2 P in Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to the input or output port mode in 1-bit units by using port mode register 0 (PM0).
CHAPTER 2 P IN FUNCTI ONS User’s Manual U12978E J3V0UD 31 2.2.4 P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins. The following operation modes can be specified in 1-bit units.
CHAPTER 2 P IN FUNCTI ONS User’s Manual U12978E J3V0UD 32 2.2.12 V PP ( µ µ µ µ PD78F9801 only) A high voltage should be applied to this pin when the flash mem ory programming m ode is set and when the program is written or verified. Handle this pin in either of the following ways.
CHAPTER 2 P IN FUNCTI ONS User ’ s Manual U12978EJ3V0UD 33 2.3 P in I/O Circuits and Rec ommended Connection of Unused P ins Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of I/O circuit.
CHAPTER 2 P IN FUNCTI ONS User ’ s Manual U12978EJ3V0UD 34 Figure 2-1. Pin I/O Circuits Type 2 Type 5-R Type 8-F Type 24-A Type 8-C IN Schmitt-triggered input with hysteresis characteristics Pull-up.
User’s Manual U12978E J3V0UD 35 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789800 Subseries can access 64 KB of memory space. Figures 3-1 and 3-2 show the memory m aps.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 36 Figure 3-2. Memory Map ( µ µ µ µ PD78F9801) Reserved Flash memory 16,384 × 8 bits Internal high-speed RAM 256 × 8 bits Special fun.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 37 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The following areas are allocated to the internal program mem ory space.
CHAPTER 3 CP U ARCHITECT URE User’s Manual U12978E J3V0UD 38 3.1.4 Data memory addressing The µ PD789800 Subseries provides a variety of addressing modes which take account of m emory manipulability, etc.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 39 Figure 3-4. Data Memory Addr essing ( µ µ µ µ PD78F9801) Special function registers (SFR) 256 × 8 bits Internal high-speed RAM 256 .
CHAPTER 3 CP U ARCHITECT URE User’s Manual U12978E J3V0UD 40 3.2 Processor Registers The µ PD789800 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence, statuses and stack mem ory.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 41 (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU . When 0, the IE flag is set to the interrupt disabled status (DI), and interrupt requests other than non- maskable interrupts are all disabled.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 42 (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the m emory stack area.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 43 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 44 3.2.3 Special function registers (SFRs) Unlike general-purpose registers, each special function register has a special function. The special function registers are allocated in the 256-byte area FF00H to FFFFH.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 45 Table 3-2. Special Function Register List (1/3) Address Special Function Regis ter (SFR) Nam e Symbol R/W Manipulatabl e Bit Unit Af ter.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 46 Table 3-2. Special Function Register List (2/3) Address Special Function Regis ter (SFR) Nam e Symbol R/W Manipulatabl e Bit Unit Af ter.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 47 Table 3-2. Special Function Register List (3/3) Address Special Function Regis ter (SFR) Nam e Symbol R/W Manipulatabl e Bit Unit Af ter.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 48 3.3 Instruction Address Ad dressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the num ber of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 49 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 50 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 51 3.4 Operand Address Add ressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 52 3.4.2 Short direct addressing [Function] The memory to be m anipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 53 3.4.3 Special function register (SFR) addressing [Function] The memory-m apped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH .
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 54 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code or function name in the instruction code.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 55 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, mem ory is manipulated according to the contents of a register pair specified as an operand.
CHAPTER 3 CP U ARCHITECT URE User ’ s Manual U12978EJ3V0UD 56 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the m emory. Addition is performed by expanding the offset data as a positive number to 16 bits.
User’s Manual U12978E J3V0UD 57 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789800 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 58 Table 4-1. Functions of Ports Pin Name I/O Function After Res et Alt ernate Function P00 to P07 I/O Port 0 8-bit I/ O port Input/out put can be s pecifi ed in 1-bit unit s.
CHAPTER 4 P ORT FUNCTI ONS User’s Manual U12978E J3V0UD 59 4.2 Port Configuration Ports consists the following hardware. Table 4-2. Configuration of Port Parameter Conf iguration Control regis ters .
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 60 4.2.1 Port 0 This is an 8-bit I/O port w i th an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port m ode register 0 (PM0).
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 61 4.2.2 Port 1 This is an 8-bit I/O port w i th an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port m ode register 1 (PM1).
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 62 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2).
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 63 Figure 4-5. Block Diagram of P21 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 2 read signal WR: Port 2 write si.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 64 Figure 4-6. Block Diagram of P22 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 2 read signal WR: Port 2 write si.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 65 Figure 4-7. Block Diagram of P23 and P24 Internal bus WR PU0 RD WR PORT WR PM PU02 Output latch (P23, P24) PM23, PM24 V DD0 P-ch P23, P24 .
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 66 Figure 4-8. Block Diagram of P25 RD V DD0 P25 WR POM1 WR PU0 WR PORT WR PM Output latch (P25) PM25 PU02 P-ch P-ch N-ch V DD0 POM125 Intern.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 67 Figure 4-9. Block Diagram of P26 RD V DD0 P26 WR POM1 WR PU0 WR PORT WR PM Output latch (P26) PM26 PU02 P-ch P-ch N-ch V DD0 POM126 Intern.
CHAPTER 4 P ORT FUNCTI ONS User’s Manual U12978E J3V0UD 68 4.2.4 Port 4 This is an 8-bit I/O port w i th an output latch. Port 4 can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4).
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 69 4.3 Registers Controlling P ort Function The following three types of registers control the ports.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 70 Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Secondary Func tion Name Input/ Output P26 TO01 Out.
CHAPTER 4 P ORT FUNCTI ONS User’s Manual U12978E J3V0UD 71 (3) Port output mode registers (POM0 and POM 1) The port output mode registers (POM 0 and POM1) are used to switch from CMOS output to N-ch open-drain output for port 0, port 1, pin P25, and pin P26.
CHAPTER 4 P ORT FUNCTI ONS User ’ s Manual U12978EJ3V0UD 72 4.4 Port Function Oper ation The operation of a port differs depending on w hether the port is set to the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction.
User’s Manual U12978E J3V0UD 73 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Gener ator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • • • • System clock oscillator This circuit oscillates at 6.
CHAPTER 5 CLOCK GE NERATOR User ’ s Manual U12978EJ3V0UD 74 5.3 Register Controlling Cloc k Generator The clock generator is controlled by the following register. • Processor clock control register (PCC) (1) Processor clock control register (PC C) PCC selects the CPU clock and sets the of division ratio.
CHAPTER 5 CLOCK GE NERATOR User ’ s Manual U12978EJ3V0UD 75 5.4 System Clock Oscillat ors 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal resonator (6.0 MHz TYP. ) connected across the X1 and X2 pins. An external clock can also be input to the circuit.
CHAPTER 5 CLOCK GE NERATOR User ’ s Manual U12978EJ3V0UD 76 5.4.2 Examples of incorrect resonator connection Figure 5-4 shows examples of incorrect resonator connection.
CHAPTER 5 CLOCK GE NERATOR User ’ s Manual U12978EJ3V0UD 77 Figure 5-4. Examples of Incorrect Resonator C onnection (2/2) (e) Signals are fetched V SS0 X1 X2 5.4.3 Frequency divider The frequency divider divides the output of the system clock oscillator (f X ) to generate various clocks.
CHAPTER 5 CLOCK GE NERATOR User ’ s Manual U12978EJ3V0UD 78 5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PC C).
User’s Manual U12978E J3V0UD 79 CHAPTER 6 8-BIT TIMER/EVENT CO UNTERS 00 AND 01 6.1 Functions of 8-Bit Timer/E vent Counters 00 and 01 The 8-bit timer/event counters (TM00 and TM 01) have the following functions.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User’s Manual U12978E J3V0UD 80 (3) Square wave output A square wave of arbitrary frequency can be output. Table 6-3. Square Wave Output Range of 8-Bit Timer/Event Counter 01 Minimum Pulse Widt h Max imum P ulse Width R esoluti on 2 4 /f X (2.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 81 Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 01 Internal bus 8-bit compare register 01 (CR01) Match TO01.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 82 6.3 Registers Contr olling 8-Bit Timer/Eve nt Counters 00 a nd 01 The following two types of registers are used to control 8-bit timer/event counters 00 and 01.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 83 (2) 8-bit timer mode control register 01 (TMC 01) TMC01 determines w hether to enable or disable 8-bit timer counter 01 (TM01), specifies the count clock for the 8-bit timer/event counter, and controls the operation of the output controller.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 84 (3) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P26/TO01/INTP0/TI01 pin for timer output, set P26 and the output latch of P26 to 0.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User’s Manual U12978E J3V0UD 85 6.4 Operation of 8-Bit Timer /Event Counter s 00 and 0 1 6.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00 and 01 (CR00 and CR01) in advance.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 86 Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00 Clear Clear Interrupt acknowledged Interrupt acknowl.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 87 6.4.2 Operation as external event counter (timer 01 only) The external event counter counts the number of external clock pulses input to the TI01/P26/INTP0/TO01 pin by using timer counter 01 (TM01).
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User’s Manual U12978E J3V0UD 88 6.4.3 Operation as square-wave output (timer 01 only) The 8-bit tim er/event counter can generate output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 01 (CR01) in advance.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 89 Figure 6-9. Timing of Square-Wave Output Clear Clear Interrupt acknowledged Interrupt acknowledged Count start Cou.
CHAPTER 6 8-BI T TIM ER/ EVENT COUNT ERS 00 AND 01 User ’ s Manual U12978EJ3V0UD 90 6.5 Notes on Using 8-Bit Timer /Event Counte rs 00 and 0 1 (1) Error on starting timer An error of up to 1 clock occurs after the timer is started until a match signal is generated.
User’s Manual U12978E J3V0UD 91 CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM).
CHAPTER 7 WATCHDOG T IMER User’s Manual U12978E J3V0UD 92 7.2 Watchdog Timer Configur ation The watchdog timer consists of the following hardware. Table 7-3. Configuration of Watchdog Timer Item Confi guration Control regis ter Timer clock s elect register 2 (TCL2) Watchdog ti mer mode regist er (WDTM) Figure 7-1.
CHAPTER 7 WATCHDOG T IMER User ’ s Manual U12978EJ3V0UD 93 7.3 Registers Contr olling Watchdog Timer The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WD TM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
CHAPTER 7 WATCHDOG T IMER User ’ s Manual U12978EJ3V0UD 94 (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. The WDTM is set with a 1-bit or 8-bit m emory manipulation instruction.
CHAPTER 7 WATCHDOG T IMER User ’ s Manual U12978EJ3V0UD 95 7.4 Watchdog Timer Ope ration 7.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer m ode register (WDTM) is set to 1.
CHAPTER 7 WATCHDOG T IMER User ’ s Manual U12978EJ3V0UD 96 7.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM 3) of the watchdog timer mode register (WD TM) are set to 0 and 1, res.
User’s Manual U12978E J3V0UD 97 CHAPTER 8 USB FUNCTION 8.1 USB Overview The USB (Universal Serial Bus) is suitable for connecting personal computers and external devices such as audio equipment, keyboards, pointing devices, and telephones. Two data transfer rates, 12 Mbps and 1.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 98 8.2 USB Function Featur es The features of the on-chip USB function provided for the µ PD789800 Subseries are described below. (1) Video display devices and hum an interface devices are assumed to be the target applications.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 99 Figure 8-2. Block Diagram of USB Function Internal bus Internal bus USBDP USBDM • Handshake pac ket • SYNC pack et USB clock Overflo w IN.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 100 Figure 8-3. Block Diagram of US B Timer Internal bus UWDERR INTUSBTM f X USBCLK RESUME RX Note Clear circuit Clock controller Shift register.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 101 (1) Receive bank switching ID detection buffer (internal buffer ) This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID during packet reception and determines the store bank of a packet.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 102 (3) Receive token bank (a) Receive token PID (USBRTP) This is the receive token packet ID area. The data input to the token PID compare register (TIDCMP) is stored here. USBRTP is read with an 8-bit mem o ry manipulation instruction.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 103 (4) Receive data bank (a) Receive data PID (USBRD) This is the receive data packet ID area. The data input to the data/handshake PID compare register (DIDCMP) is stored here. USBRD is read with an 8-bit m emory manipulation instruction.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 104 (5) Transmit data banks 0 and 1 (a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1) USBTD0 and USBTD1 correspond to the transmit buffer 0 ID area and transmit buffer 1 ID area, respectively.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 105 Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1) Data area (8 bytes) USBPOW address ID area USBPOB address USBTD1 Symbol 07H 06H.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 106 (6) Data/handshake packet receive byte number counter (DR XCON) This register sets the number of data of the data/handshake packet to be received.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 107 (9) Token address compare register (ADRCMP) This register sets the address specified from the host during control transfer.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 108 (10) Data/handshake PID compar e register (DIDCM P) This register sets the data/handshake packet ID to be received.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 109 8.4 Registers Controlling US B Function The following nine registers are used to control the USB function.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 110 Figure 8-11. Format of Data/Handshake Packet Receive M ode Register Symbol 6 7 5 4 3 <2> <1> <0> 000 00 RESMOD DINTEN DWRMSK RESMOD USB reset signal detection mode setting 0 1 FF66H Address URXMOD After reset 00H R/W R/W Reject USB reset signal less than 3.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 111 (3) Packet receive status register (RXSTAT) This register indicates the receive status of each packet. Bits 0 to 2 (TOSTAT, DASTAT, and HSSTAT) are flags that indicate that a token packet, data packet, or handshake packet is currently being received.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 112 Figure 8-12. Format of Packet Receive Status Register Symbol 6 7 5 432 10 UWDERR RESMRX SE0RX URESRX EOPRX HSSTAT DASTAT TOSTAT UWDERR USB timer inadvertent program loop detection 0 1 FF67H Address RXSTAT After reset 00H R/W R/W No USB timer inadvertent program loop was detected.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 113 Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume signal during the bus idle state and bus suspend state.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 114 Figure 8-14. Format of Token Packet Receive Result Store R egister Symbol <6> <7> <5> <4> <3> <2> <1&g.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 115 (6) Data packet transmit reservation register (D TXRSV) This register sets the bank where the data packet to be transmitted is stored. By setting each flag of this register, the stored data is transmitted following normal reception of the IN token packet.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 116 (7) Handshake packet transmit reservation register (H TXRSV) This register sets the handshake packet to be transmitted. By setting each flag of this register, a handshake packet is transm itted following normal reception of an IN packet, or normal or abnormal reception of a data packet.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 117 Figure 8-16. Format of Handshake Packet Transmit Reser vation Register (2/2) ACKEN ACK packet transmit reservation flag after data packet reception 0 1 No data is transmitted. ACK handshake is transmitted when all the following conditions are satisfied in EOP during data packet reception.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 118 Table 8-3. Conditions in Transmit Reservation (2/2) (b) Transmit reservation for Endpoint1 and IN token packet Type of Reserv ation DT01EN D.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 119 Figure 8-17. Configuration of Handshake Packet Transmit Reser vation Register END1RX END0RX TIDRST ADRRST DIDRST DBYER DBITER TBYER TBITER C.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 120 (8) USB timer start reservation contr ol register (USBTCL) This register reserves USB timer start after reception of a SETUP/O UT packet or transmission of a data packet. USBTCL is set with a 1-bit or 8-bit mem ory manipulation instruction.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 121 (9) Remote wake-up control register (REM WUP) This register transmits the Resume signal to perform remote wakeup. Remote wakeup m ust be performed after confirming that bus idle has continued longer than 5 ms.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 122 8.5 USB Function Opera tion 8.5.1 USB timer operation The USB timer is a 7-bit counter that performs tim e management during packet transmission and reception and inadvertent program loop detection of the USB clock.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 123 Figure 8-20. Flowchart of USB Timer Operation (1/2) SYNC detected? EOP received? SET ORX (internal signal) = 1? T ransmit data transf err ing.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 124 Figure 8-20. Flowchart of USB Timer Operation (2/2) 2 INTUSBTM occurred High-speed mode ov erflow? 3 N Y N Y 1 Next SYNC detected? USB timer.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 125 8.5.2 Remote wakeup control operation Figure 8-21. Flow Chart of Remote Wakeup Control Operation Idle state Y N Y 10 ms to 15 ms elapsed? N .
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 126 Notes 1. Be sure to follow the exact instruction sequence when the Resume signal ( “ K ” state) is output. SET1 REMWUP.3 ; (PULLDM ← 1) CLR1 REMWUP.2 ; (PULL DP ← 0) MOV A, #00000111B ; (A ← 00000111B) SET1 REMWUP.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 127 8.6 Interrupt Reques t from USB Function 8.6.1 Interrupt sources Interrupt request sources generated by the USB function fall into the following five categories.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 128 (3) Data/handshake packet transmit interrupt (INTU SBST) Upon EOP detection during data/handshake packet transmission, an interrupt request signal is generated and an interrupt request flag (USBSTIF) is set.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 129 8.6.2 Cautions when using interrupts Pay attention to the following when using an interrupt request generated by the USB function. (1) Because USBR EIF is set by transition from the J state to the K state on the bus, it is also set during sync detection or packet reception.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 130 8.7 USB Function Control 8.7.1 Relationship between packets and operation modes The relationship between packets and operation modes in the USB function is as follows.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 131 (2) Control transfer (OUT) (Transfer byte count: 9 bytes or more) Request Operation of host controller OUT packet SETUP DATA0 ACK Packet fro.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 132 (3) Control transfer (IN) (Tr ansfer byte count: 8 bytes or less) Request Operation of host controller IN packet SETUP DATA0 ACK Packet from.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 133 (4) Control transfer (IN) (Transfer byte count: 9 bytes or more) Request Operation of host controller IN packet SETUP DATA0 ACK Packet from h.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 134 (5) No data control Request Operation of host controller IN packet SETUP DATA0 ACK Packet from host controller Packet from PD789800 Setup st.
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 135 (6) Interrupt transfer Operation of host controller IN packet IN NAK Packet from host controller Packet from PD789800 NAK IN DATA1 • NAK tr.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 136 8.7.2 Interrupt servicing flow (1) USB token packet reception interrupt ser vicing INTUSBRT occurrence RETI Receive error occurred? Receive .
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 137 (2) Data/handshake packet reception interrupt servicing INTUSBRD occurrence RETI Planned packet was received? USB_MODE is SETUP? USB_MODE is .
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 138 (3) USB timer inadvertent program loop detection interrupt servicing INTUSBTM occurrence RETI Processing for each operation mode when ACK is .
CHAPTER 8 US B FUNCTION User’s Manual U12978E J3V0UD 139 (4) 1 ms timer interrupt servicing INTTM00 occurrence RETI REMOTE WAKEUP? Standby detected? Communication operating? RESET received? Waiting .
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 140 8.8 USB Function Inte rnal Circuit Ope rations 8.8.1 Operation of transmit/receive pointer Figure 8-25.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 141 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (2/7) (1) Token packet reception (2/2) Y Y Y EOP Y N N N 2 USBPOW = 05H? USBPOB.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 142 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (3/7) (2) Data/Handshake packet reception (1/2) N Y Y Y N Y N EOP Y Y N 1 Y EOP.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 143 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (4/7) (2) Data/Handshake packet reception (2/2) Y Y Y EOP Y N N N N 2 1 USBPOB .
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 144 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (5/7) (3) Data packet transmit (1/2) Y Y Transmit buffer N Handshake Y Y N N 1 .
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 145 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (6/7) (3) Data packet transmit (2/2) Y Y N N N 2 3 3 USBPOB overflow? Y N USBPO.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 146 Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (7/7) (4) Handshake packet transmission Y Y Handshake Transmit buffer Y N N 1 Y.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 147 8.8.2 Receive bank switching ID detection buffer operation Figure 8-26. Flowchart of Receive Bank Sw itching ID Detection Buffer Oper ation .
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 148 8.8.3 Sync detection/USBCLK detector operation This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In addition, it contains an NRZI decoder that decodes receive packets and detects the last bit of the sync part.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 149 Figure 8-29. Flowchart of Sync Detection/USB CLK Detector Oper ation N Y N Y N Y Y N Idle state USB clock oscillation start Detect last Sync.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 150 8.8.4 NRZI encoder operation This circuit performs NRZI encoding of data to be transm itted. Figure 8-30. Timing of NRZI Encoder Operation Data before encoding USB clock generation NRZI encoding Transmit packet Sync pattern Data/handshake packet Figure 8-31.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 151 8.8.5 Bit stuffing/strip controller operation This circuit counts the number of “ logic 1 ” of transmit/receive packets. If six successive logic 1s are detected, it outputs an increment disable signal to the transmit/receive pointer (USBPOB).
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 152 Figure 8-33. Flow Chart of Bit Stuffing Control Operation Y Y Y N N Idle state Idle state Transmit bit input Shift bit stuffing register Dis.
CHAPTER 8 US B FUNCTION User ’ s Manual U12978EJ3V0UD 153 Figure 8-34. Flow Chart of Bit Strip Control Operation Y Y Y N N Idle state Idle state Receive bit input Shift bit stuffing register Receive.
User’s Manual U12978E J3V0UD 154 CHAPTER 9 SERIAL INTERFACE 10 9.1 Functions of Serial Interface 10 Serial interface 10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out.
CHAPTER 9 S ERIAL I NTERFACE 10 User’s Manual U12978E J3V0UD 155 9.2 Con figuratio n of Serial Int erface 10 Serial interface 10 consists of the following hardware.
CHAPTER 9 S ERIAL I NTERFACE 10 User’s Manual U12978E J3V0UD 156 Figure 9-1. Block Diagram of Serial Inter face 10 Internal bus CSIE10 TPS100 DIR10 Serial operation mode register 10 (CSIM10) CSCK10 .
CHAPTER 9 S ERIAL I NTERFACE 10 User ’ s Manual U12978EJ3V0UD 157 9.3 Regist er Controllin g Serial Interface 10 The following register is used to control serial interface 10.
CHAPTER 9 S ERIAL I NTERFACE 10 User ’ s Manual U12978EJ3V0UD 158 Table 9-2. Operating Mode Settings of Serial Inter face 10 (1) Operation stop mode CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22.
CHAPTER 9 S ERIAL I NTERFACE 10 User ’ s Manual U12978EJ3V0UD 159 9.4 Op eration of Serial Interface 10 Serial interface 10 provides the following two modes. • Operation stop mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced.
CHAPTER 9 S ERIAL I NTERFACE 10 User’s Manual U12978E J3V0UD 160 9.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/O s and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.
CHAPTER 9 S ERIAL I NTERFACE 10 User ’ s Manual U12978EJ3V0UD 161 (2) Communication operation In the 3-wire serial I/O mode, data transm ission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock.
User’s Manual U12978E J3V0UD 162 CHAPTER 10 REGULATOR The µ PD789800 incorporates a regulator that powers the USB driver/receiver. The features are as follows. • Generates V REG (3.3 ± 0.3 V) from V DD0 , V DD1 (4.0 to 5.5 V) and outputs it to the RE GC pin.
User’s Manual U12978E J3V0UD 163 CHAPTER 11 INTERRUPT FUNCTIONS 11.1 Interrupt Func tion Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does no undergo interrupt priority control and is given top priority over all other interrupt requests.
CHAPTER 11 I NTERRUPT FUNCTIONS User’s Manual U12978E J3V0UD 164 Table 11-1. Interrupt Source List Type of Int errupt Priority Note 1 Int errupt Source Name Trigger Nonmaskabl e - INTWDT Watchdog ti.
CHAPTER 11 I NTERRUPT FUNCTIONS User’s Manual U12978E J3V0UD 165 Figure 11-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Interrupt request Vector tabl.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 166 11.3 Registers Controlling Inte rrupt Function The following five registers are used to control the interrupt functions.
CHAPTER 11 I NTERRUPT FUNCTIONS User’s Manual U12978E J3V0UD 167 (1) Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 w hen the corresponding interrupt request is generated or an instruction is executed.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 168 (2) Interrupt mask flag registers (MK 0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set w ith a 1-bit or 8-bit memory m anipulation instruction.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 169 (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped here.
CHAPTER 11 I NTERRUPT FUNCTIONS User’s Manual U12978E J3V0UD 170 (5) Key return mode register 00 (K RM00) This register sets the pin that detects a key return signal (rising edge of port 4). KRM00 is set with a 1-bit an 8-bit m emory manipulation instruction.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 171 11.4 Interrupt Se rvicing Opera tion 11.4.1 Non-maskable interrupt acknowledgment oper ation The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 172 Figure 11-8. Flowchart of Non-M askable Interrupt Request Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval .
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 173 11.4.2 Maskable interrupt acknow ledgment operation A maskable interrupt can be acknow ledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 174 Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r) Clock CPU MOV A,r Saving PSW and PC, and jump to inter.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 175 11.4.3 Multiplexed interrupt servicing Servicing in w hich another interrupt is acknowledged while an interrupt is being processed is called m ultiplexed interrupt servicing.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 176 Figure 11-14. Example of Multiplexed Interrupt Ser vicing Example 1. Acknowledging multiplexed interrupts INTyy EI Main processing E.
CHAPTER 11 I NTERRUPT FUNCTIONS User ’ s Manual U12978EJ3V0UD 177 11.4.4 Interrupt request hold If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested w hen a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed.
User’s Manual U12978E J3V0UD 178 CHAPTER 12 STANDBY FUNCTION 12.1 Standby Function and Configur ation 12.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruction is executed.
CHAPTER 12 S TANDBY FUNCTI ON User’s Manual U12978E J3V0UD 179 12.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS).
CHAPTER 12 S TANDBY FUNCTI ON User ’ s Manual U12978EJ3V0UD 180 12.2 Standby Function Ope ration 12.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HA LT instruction. The operation status in the HALT mode is shown in the follow ing table.
CHAPTER 12 S TANDBY FUNCTI ON User ’ s Manual U12978EJ3V0UD 181 (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unm asked interrupt request.
CHAPTER 12 S TANDBY FUNCTI ON User ’ s Manual U12978EJ3V0UD 182 (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started.
CHAPTER 12 S TANDBY FUNCTI ON User ’ s Manual U12978EJ3V0UD 183 12.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STO P instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to V DD to suppress the current leakage of the crystal oscillator block.
CHAPTER 12 S TANDBY FUNCTI ON User’s Manual U12978E J3V0UD 184 (2) Releasing STOP mode The STOP mode can be released by the follow ing two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unm asked interrupt request.
CHAPTER 12 S TANDBY FUNCTI ON User ’ s Manual U12978EJ3V0UD 185 (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 12-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Wait (2 15 /f X : 5.
User’s Manual U12978E J3V0UD 186 CHAPTER 13 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by inadvertent program loop time detected by watchdog tim e r External and internal reset have no functional differences.
CHAPTER 13 R ESET F UNCTI ON User ’ s Manual U12978EJ3V0UD 187 Figure 13-2. Reset Timing by RESET Input X1 RESET Internal reset signal Port pin During normal operation Delay Delay Hi-Z Reset period (oscillation stops) Normal operation (reset processing) Oscillation stabilization time wait Figure 13-3.
CHAPTER 13 R ESET F UNCTI ON User’s Manual U12978E J3V0UD 188 Table 13-1. Hardware Status After R eset (1/2) Hardware Status Aft er Reset Program count er (PC) Note 1 The contents of reset vect or tables (0000H and 0001H) are set.
CHAPTER 13 R ESET F UNCTI ON User’s Manual U12978E J3V0UD 189 Table 13-1. Hardware Status After R eset (2/2) Hardware Status Aft er Reset USB func tion Data pack et transm it byt e number counter 0 .
User’s Manual U12978E J3V0UD 190 CHAPTER 14 µ µ µ µ PD78F9801 The µ PD78F9801 is a product that substitutes flash mem ory for the internal ROM of the mask ROM version. The differences between the µ PD78F9801 and the mask RO M versions are shown in Table 14-1.
CHAPTER 14 µ µ µ µ PD78F9801 User’s Manual U12978E J3V0UD 191 14.1 Flash Memory Charact eristics Flash mem ory programm ing is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR 4, PG-FP4)) to the target system with the µ PD78F9801 mounted on the target system (on-board).
CHAPTER 14 µ µ µ µ PD78F9801 User ’ s Manual U12978EJ3V0UD 192 14.1.2 Communication mode Use the communication m ode shown in Table 14-2 to perform communication between the dedicated flash programmer and µ PD78F9801.
CHAPTER 14 µ µ µ µ PD78F9801 User ’ s Manual U12978EJ3V0UD 193 Figure 14-3. Example of Connection with Dedicated Flash Progr ammer (a) 3-wire serial I/O Dedicated flash programmer VPP1 VDD RESET.
CHAPTER 14 µ µ µ µ PD78F9801 User’s Manual U12978E J3V0UD 194 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash program mer, the following signals are generated for the µ PD78F9801. For details, refer to the manual of Flashpro III/Flashpro IV.
CHAPTER 14 µ µ µ µ PD78F9801 User’s Manual U12978E J3V0UD 195 14.1.3 On-board pin processing When performing programm ing on the target system, provide a connector on the target system to connect the dedicated flash programmer.
CHAPTER 14 µ µ µ µ PD78F9801 User ’ s Manual U12978EJ3V0UD 196 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs.
CHAPTER 14 µ µ µ µ PD78F9801 User’s Manual U12978E J3V0UD 197 <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection w ith the reset signal generator.
CHAPTER 14 µ µ µ µ PD78F9801 User ’ s Manual U12978EJ3V0UD 198 14.1.4 Connection of adapter for flash writing The following figure shows an example of recom mended connection when the adapter for flash writing is used.
CHAPTER 14 µ µ µ µ PD78F9801 User ’ s Manual U12978EJ3V0UD 199 Figure 14-9. Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 PD78F9801 GND VDD SI SO SCK CLK OUT RESET VPP RESER VE/HS VDD (4.
User’s Manual U12978E J3V0UD 200 CHAPTER 15 INSTRUCTION SET This chapter lists the instruction set of the µ PD789800 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instruction User’s Manual (U 11047E) .
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 201 15.1.2 Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E:.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 202 15.2 Operation List Mnemonic Operands Bytes Cloc ks Operat ion Flag ZA C C Y MOV r,#byte 3 6 r ← byte saddr,#by te 3 6 (saddr) ← byt.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 203 Mnemonic Operands Bytes Cloc ks Operat ion Flag ZA C C Y MOVW rp,#word 3 6 rp ← word AX,s addrp 2 6 AX ← (saddrp) saddrp,AX 2 8 (sad.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 204 Mnemonic Operands Bytes Cloc ks Operat ion Flag ZA C C Y SUBC A,#b y te 2 4 A,CY ← A − byt e − CY ××× saddr,#by te 3 6 (saddr),.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 205 Mnemonic Operands Bytes Cloc ks Operat ion Flag ZA C C Y CMP A,#by te 2 4 A − by te ××× saddr,#by te 3 6 (saddr) − byt e ××× A.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 206 Mnemonic Operands Bytes Cloc ks Operat ion Flag ZA C C Y CALL !addr16 3 6 (SP − 1) ← (P C+3) H , (SP − 2) ← (PC+3) L , PC ← ad.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 207 15.3 Inst ructions List ed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, R.
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 208 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand #word AX rp Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp = BC, DE, or HL .
CHAPTER 15 I NSTRUCTI ON SET User’s Manual U12978E J3V0UD 209 (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand AX !addr16 [addr5] $addr16 Bas.
User’s Manual U12978E J3V0UD 210 CHAPTER 16 ELECTRICAL SP ECIFICATIONS Absolute Maximum Ratings (T A = 25 ° ° ° ° C) Parameter Symbol Condit ions Rat ing Unit V DD − 0.3 to + 6.5 V Supply v oltage V PP µ PD78F9801 only Note 1 − 0.3 to +10.5 V Input vol tage V I − 0.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User ’ s Manual U12978EJ3V0UD 211 System Clock Oscillation Circuit Characteristics (T A = − − − − 40 to +85 ° ° ° ° C, V DD = 4.0 to 5.5 V) Resonator Rec ommended Circui t P arameter Conditions MI N.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User ’ s Manual U12978EJ3V0UD 212 DC Characteristics (T A = − − − − 40 to +85 ° ° ° ° C, V DD = 4.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User’s Manual U12978E J3V0UD 213 DC Characteristics (T A = − − − − 40 to +85 ° ° ° ° C, V DD = 4.0 to 5.5 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit I DD1 6.0 MHz cry stal osc illation (operating mode) Note 2 1.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User’s Manual U12978E J3V0UD 214 AC Characteristics (1) Basic operations (T A = − − − − 40 to +85 ° ° ° ° C, V DD = 4.0 to 5.5 V) Parameter Symbol Conditions MIN. TY P. MAX. Unit When PCC = 00H (f X = 6.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User’s Manual U12978E J3V0UD 215 (b) 3-wire serial I/O mode (T A = − − − − 40 to +85 ° ° ° ° C, V DD = 4.0 to 5.5 V) (i) SCK10 ...Internal clock output (when f X = 6.0 MHz) Parameter Symbol Conditions MIN.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User ’ s Manual U12978EJ3V0UD 216 AC Timing Measurement Points (Except X1 Input and USB Function) 0.8V DD 0.2V DD 0.8V DD 0.2V DD Measurement points Clock timing 1/f X t XL t XH X1 input V IH3 (MIN.) V IL3 (MAX.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User’s Manual U12978E J3V0UD 217 Serial Transfer Timing USB function: USBDM and USBDP rise/fall time USBDM, USBDP t R 0.
CHAPTER 16 E LECTRI CAL SPECIFICATIO NS User ’ s Manual U12978EJ3V0UD 218 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = − − − − 40 to +85 ° ° ° ° C) Item Sy mbol Conditions MIN. TY P. MAX. Unit Data hold suppl y volt age V DDDR 4.
User’s Manual U12978E J3V0UD 219 CHAPTER 17 PACKAGE DRAW INGS 33 34 22 44 1 12 11 23 44 PIN PLASTIC LQFP (10x10) ITEM MILLIMETERS N Q0 . 1 ± 0.05 0.10 S44GB-80-8ES-2 J I H N A 12.0 ± 0.2 B 10.0 ± 0.2 C 10.0 ± 0.2 D 12.0 ± 0.2 F G H 1.0 0.37 1.0 I J K 0.
User’s Manual U12978E J3V0UD 220 CHAPTER 18 RECOMMENDE D SOLDERING CONDITIONS The µ PD789800 Subseries should be soldered and mounted under the following recom mended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E) .
User’s Manual U12978E J3V0UD 221 APPENDIX A DEVEL OPMENT TO OLS The following development tools are available for developm ent of systems using the µ PD789800 Subseries.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978E J3V0UD 222 Figure A-1. Development Tools Language processing software · Assembler package · C compiler package · Device file · C library source.
APPENDIX A DEVELOPMENT TOOLS User ’ s Manual U12978EJ3V0UD 223 A.1 Softw are Package Software t ools for dev elopment of the 78K/0S Series are c ombined in t his pack age.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U12978E J3V0UD 224 Remark ×××× in the part number differs depending on the host machine and operating system to be used. µ S ×××× RA78K0S µ S ×××× CC78K0S ×××× Host Mac hine OS Supply Medi um AB13 J apanese Windows 3.
APPENDIX A DEVELOPMENT TOOLS User ’ s Manual U12978EJ3V0UD 225 A.5 Debugging Tools (Hardwa re) IE-78K0S -NS In-circ uit emul ator In-circ uit emul ator for debugging hardware and s oftware of an appl ication system usi ng the 78K/0S S eries. S upports a int egrated debugger (ID78K 0S-NS).
APPENDIX A DEVELOPMENT TOOLS User ’ s Manual U12978EJ3V0UD 226 A.6 Debugging Tools (Softwar e) This debugger support s the in-c ircuit emulators IE-78K0S -NS and IE-78K 0S-NS-A f or the 78K/0S S eries.
APPENDIX A DEVELOPMENT TOOLS User ’ s Manual U12978EJ3V0UD 227 A.7 Notes on Targ et System Design Figures A-2 and A-3 show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.
APPENDIX A DEVELOPMENT TOOLS User ’ s Manual U12978EJ3V0UD 228 Figure A-3. Connection Condition of Target System (NP-H44GB-TQ) Emulation board IE-789801-NS-EM1 Emulation probe NP-H44GB-TQ Conversion adapter TGB-044SAP 11 mm 34 mm 40 mm 10 mm 23 mm Target system Remarks 1 .
User’s Manual U12978E J3V0UD 229 APPENDIX B REGIS TER INDEX B.1 Register Index (Alphabetic Order of Register Name) 8-bit compare register 00 (CR00) ............................................................................................... .....
APPENDI X B REGI STER I NDEX User’s Manual U12978E J3V0UD 230 Port mode register 2 (PM2) .................................................................................................................................... 69 Port mode register 4 (PM4) .
APPENDI X B REGI STER I NDEX User’s Manual U12978E J3V0UD 231 B.2 Register Index (Alphabetic Order of Register Symbol) [A] ADRCMP: Token addres s compare register ......................................................................................
APPENDI X B REGI STER I NDEX User’s Manual U12978E J3V0UD 232 PU0: Pull-up resistor option register 0 ........................................................................................ 70 [R] REMWUP: Remote wake-up control register ...........
User’s Manual U12978E J3V0UD 233 APPENDIX C REV ISION HISTORY The revision history is described below. The “Applied to” column indicates the chapters in each edition.
APPEND IX C REVISION HISTORY User’s Manual U12978E J3V0UD 234 (2/2) Edition Maj or Revisi ons from P revious E dition Applied to: Correction of address v alues in Figure 3-1 Memory Map ( µ µ µ µ.
An important point after buying a device NEC switch (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought NEC switch yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data NEC switch - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, NEC switch you will learn all the available features of the product, as well as information on its operation. The information that you get NEC switch will certainly help you make a decision on the purchase.
If you already are a holder of NEC switch, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime NEC switch.
However, one of the most important roles played by the user manual is to help in solving problems with NEC switch. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device NEC switch along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
