Instruction/ maintenance manual of the product Core 2 Quad Q6700 Intel
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Document Number: 315592 -005 Intel ® Core™2 Extreme Quad-Core Processor QX6000 Δ Sequence and Intel ® Core™2 Quad Processor Q6000 Δ Sequence Datasheet —on 65 nm Process in the 775- land LGA .
2 Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL PRODUCTS . NO LICENSE, EXPRES S OR IMPLIED , BY EST OPPEL OR OTH ERW IS E , TO AN Y IN T EL LEC T UAL PR OP ERT Y R IG HT S I S G RAN T ED BY TH I S DOCUMENT .
Datasheet 3 Contents 1I n t r o d u c t i o n ......... ......... .......... ........... ........ ........... .......... ......... .......... ......... .......... .... 9 1.1 Terminology ........... .......... ......... .......... ........... .........
4 Datasheet 5.2.5 THERMTRIP # Signal ........... ........ ........... .......... ........... .......... ........... ........79 5.3 Platform Environme nt Control Interface (PECI) .... ............ ........... .......... ............. .... 80 5.3.1 Introdu ction .
Datasheet 5 Figures 1V CC Static and Transient T olerance ................ ........... .......... ........... .......... ........... ........ 20 2V CC Overshoot Examp le Waveform .............. ........... .......... ........... .......... ...........
6 Datasheet Tables 1 References ............... ......... .......... ........... ........ ........... .......... ......... .......... ........... ......11 2 Voltage Identification Definition .... ........... .......... ......... .......... ...........
Datasheet 7 Revision History § Revision Number Description Date -001 • Initial release November 2006 -002 • Added specificatio ns for the Intel ® Core™2 Quad Processor Q6600 • Updated T able 8, “Signal Char acteristics” . • Updated VTT_SEL description in T able 24.
8 Datasheet Intel ® Core™2 Extreme Quad-Core Processor QX6000 and Intel ® Core™2 Quad Processor Q6000 Sequence Features The Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence deliver Intel's adv anced, powerful processors for desktop PCs.
Datasheet 9 Introduction 1 Introduction The Intel ® Core™2 Extreme quad-core proce ssor QX6000 sequence and Intel ® Core™2 quad processor Q6000 sequence are the first desktop quad-core processor.
Introduction 10 Datasheet “Front Side Bus” refers to the interface betwee n the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory , and I/O.
Datasheet 11 Introduction • Enhanced Intel Technology SpeedStep ® Technology — Enhanced Intel T echnology SpeedStep ® T echnology allow s trade-offs to be made betw een performance and power consumptions, based on processor utilization. This may lower aver age power consumption (in conjunction with OS support).
Introduction 12 Datasheet.
Datasheet 13 Electrical Specifications 2 Electrical Specifications This chapter describes the electrical charac teristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VT T and VSS (ground) inputs for on-chip power distribution.
Electrical Specifications 14 Datasheet 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, so me of the high frequency capacitance required for the FSB is included on the processor package.
Datasheet 15 Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX 11110 1 0.8500 0 11110 1 . 2 3 7 5 11110 0 0.8625 0 11101 1 . 2 5 0 0 11101 1 0.8750 0 11100 1 .
Electrical Specifications 16 Datasheet 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must re main unconnected. Connection of these lands to V CC , V SS , V TT , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.
Datasheet 17 Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Ta b l e 3 specifies absolute maximum and mini mum r atings only and lie outside the functional limits of the processor . Within functional operation limits, functionality and long-term reliability can be expected.
Electrical Specifications 18 Datasheet 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1, 2 NOTES: 1. Unless other wise noted, all sp ecifications in this table are bas ed on estimates an d simulations or empirical data.
Datasheet 19 Electrical Specifications 8. I CC_MAX specification i s based on the V CC_MAX loadline. Refer to Figur e 1 for details. 9. These Processors have CPUID = 06FBh 10.
Electrical Specifications 20 Datasheet NOTES: 1. The loadline s pecificatio n includes both st atic and transient limits e xcept for overshoot allowed as shown in Sectio n 2.5.3 . 2. This loadline s pecificatio n shows the deviation from the VID set point.
Datasheet 21 Electrical Specifications 2.5.3 V CC Overshoot The processor can tolerate short tr ansient overshoot events where V CC exceeds the VID voltage when transitioning from a high to low current load condition. This ov ershoot cannot exceed VID + V OS_MAX (V OS_MAX is the maximum allowable overshoot v oltage).
Electrical Specifications 22 Datasheet 2.6 Signaling Specifications Most processor Front Side Bus signals use Gunning T r a nsceiver Logic (GTL+) signaling technology . This technology provides im proved noise margins and reduced ringing through low voltage swings and controlled edge r ates.
Datasheet 23 Electrical Specifications NOTES: 1. R efer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, the se signals are used to support a debug port in terposer . In systems with the debug port implemented on the system board, these signals are no connec ts.
Electrical Specifications 24 Datasheet 2.6.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IG NNE#, INIT#, SMI#, an d STPCLK# use CMOS input buffers. All of the CMOS and Open Dr ain signals are required to be asserted/ deasserted for at least four BCLKs for the processor to recognize the proper signal state.
Datasheet 25 Electrical Specifications NOTE: 1. V TT supplies the PECI interface. PECI behavior does not affect V TT min/max specificat ions. Refer to Ta b l e 4 for V TT specificat ions. 2. The leakage spec ification applie s to powered devices on the PECI bus.
Electrical Specifications 26 Datasheet 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integr ated into the processor silicon. See Ta b l e 8 for details on which GTL+ signals do not include on-die termination.
Datasheet 27 Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Ta b l e 1 6 defines the possible combinations of the signals and the frequency associated with each combination.
Electrical Specifications 28 Datasheet 2.7.4 BCLK[1:0] Specifications . Table 17. Front Si de Bus Diffe rential BCLK Specificat ions Symbol Parameter Min Typ Max Unit Figure Notes 1 NOTES: 1. Unless otherwise no ted, all specificat ions in this table apply to all processor frequencies.
Datasheet 29 Electrical Specifications Table 19. FSB Differ ential Cloc k Specifications (1333 MHz FSB) T# Parameter Min Nom Max Unit Figure Notes 1 NOTES: 1. Unless otherwis e noted, all specifi cations in this table apply to all processor cor e frequencies based on a 333 MHz BCLK[1:0].
Electrical Specifications 30 Datasheet § § Figure 4. Differential C lock Crosspoint Specification Figure 5. Differential Me asurements 660 670 680 690 700 710 720 730 740 750 760 7 70 780 790 800 810 820 830 840 850 200 250 300 350 400 450 500 550 600 650 VHavg (mV) Crossing Poin t (mV) 550 mV 300 mV 300 + 0.
Datasheet 31 Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-L GA6) package that interfaces with the motherboar d via an LG A775 sock et. The package consists of a processor core mounted on a substrate land-carrier .
Package Mechanical Specifications 32 Datasheet Figure 7. Processor Package Drawing Sh eet 1 of 3.
Datasheet 33 Package Mechanical Specifications Figure 8. Processor Package Drawing Sheet 2 of 3.
Package Mechanical Specifications 34 Datasheet Figure 9. Processor Package Drawing Sh eet 3 of 3.
Datasheet 35 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must n ot intrude into the required keep-out zones.
Package Mechanical Specifications 36 Datasheet 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide .
Datasheet 37 Package Mechanical Specifications Figure 11. Processor Top- Side Markings Example for 1333 MHz Processors ATPO S/ N INTEL ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.
Package Mechanical Specifications 38 Datasheet 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands.
Datasheet 39 Land Listi ng and Sign al Description s 4 Land Listing and Signal Descriptions This chapter provides the processor la nd assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for th e processor .
Land Listing and Signal Descriptions 40 Datasheet Figure 13. land-out Diagram ( Top View – Left Si de) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VS S VCC VCC VSS.
Datasheet 41 Land Listi ng and Sign al Description s Figure 14. land-out Diagram (Top View – Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VSS VCC VCC VID_SEL ECT VSS_MB_ REGULA TION .
Land Listing and Signal Descriptions 42 Datasheet Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/Outpu.
Land Listi ng and Sign al Description s Datasheet 43 D18# F9 Source Synch Input/Output D19# E9 Source Synch Input/Output D20# D7 Source Synch Input/Output D21# E10 S ource Synch Input/Output D22# D10 .
Land Listing and Signal Descriptions 44 Datasheet FC32 H15 Power/Other FC33 H16 Power/Other FC34 J17 Power/Other FC35 H4 Power/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC39 AA2 Power/Other FC4 .
Land Listi ng and Sign al Description s Datasheet 45 TRDY# E3 Common Clock Input TRST# AG1 T AP Input VCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/O.
Land Listing and Signal Descriptions 46 Datasheet VCC AJ18 Powe r/Other VCC AJ19 Powe r/Other VCC AJ21 Powe r/Other VCC AJ22 Powe r/Other VCC AJ25 Powe r/Other VCC AJ26 Powe r/Other VCC AJ8 Power/Othe.
Land Listi ng and Sign al Description s Datasheet 47 VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Oth er VCC J9 Power/Oth er VCC K23 Power/O ther VCC K24 Power/O ther VCC K.
Land Listing and Signal Descriptions 48 Datasheet VID_SELECT AN7 Power/Other Output VID0 AM2 Power/Other Output VID1 AL5 Power/Other Output VID2 AM3 Power/Other Output VID3 AL6 Power/Other Output VID4.
Land Listi ng and Sign al Description s Datasheet 49 VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/O ther VSS AH 10 Power/Other VSS AH 13 Power/Other.
Land Listing and Signal Descriptions 50 Datasheet VSS B20 Power/O ther VSS B24 Power/O ther VSS B5 Power/Othe r VSS B8 Power/Othe r VSS C10 Power/Other VSS C13 Power/Other VSS C16 Power/Other VSS C19 .
Land Listi ng and Sign al Description s Datasheet 51 VSS N3 Power/Oth er VSS N6 Power/Oth er VSS N7 Power/Oth er VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27.
Land Listing and Signal Descriptions 52 Datasheet Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 VSS Power/Other A3 RS2# Common Clock I nput A4 D02# Source Synch .
Land Listi ng and Sign al Description s Datasheet 53 C20 DBI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Other C23 VCCIOPLL Power/Other C24 VSS Power/Other C25 VTT Pow.
Land Listing and Signal Descriptions 54 Datasheet F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Inp.
Land Listi ng and Sign al Description s Datasheet 55 H30 BSEL1 Power/Other Output J1 VTT_OUT_LEFT Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1# Source Synch Inp.
Land Listing and Signal Descriptions 56 Datasheet M30 VCC Power/Other N1 PWRGOOD Power/Other Input N2 IGNNE# Asynch CMOS Input N3 VSS Power/Oth er N4 RESERVED N5 RESERVED N6 VSS Power/Oth er N7 VSS Po.
Land Listi ng and Sign al Description s Datasheet 57 U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 P ower/Other Output V2 RESERVED V3 VSS Power/Other V4 A15# Source Synch Input/.
Land Listing and Signal Descriptions 58 Datasheet AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other AC1 TMS T A P Inp ut AC2 DBR# Power/Other Out.
Land Listi ng and Sign al Description s Datasheet 59 AF12 VCC Power/Ot her AF13 VSS Power/Ot her AF14 VCC Power/Ot her AF15 VCC Power/Ot her AF16 VSS Power/Ot her AF17 VSS Power/Ot her AF18 VCC Power/.
Land Listing and Signal Descriptions 60 Datasheet AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CL K1 TAP Input AJ4 VSS Power/O ther AJ5 A 34# So.
Land Listi ng and Sign al Description s Datasheet 61 AL18 VCC Power/Ot her AL19 VCC Power/Ot her AL20 VSS Power/Ot her AL21 VCC Power/Ot her AL22 VCC Power/Ot her AL23 VSS Power/Ot her AL24 VSS Power/.
Land Listing and Signal Descriptions 62 Datasheet 4.2 Alphabetical Signals Reference Table 25. Signal Descript ion (Sheet 1 of 9) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, th ese signals transmit the address of a transaction.
Datasheet 63 Land Listi ng and Sign al Description s BPM[5:0]# BPMb[3:0]# Input/ Output BPM[5:0]# and BPMb[3:0] # (Break point Monitor) are break point and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for moni toring processor performance.
Land Listing and Signal Descriptions 64 Datasheet D[63:0]# Input/ Output D[63:0]# (Data) are the data sign als. These signals provide a 6 4- bit data path between the processor FSB agents , and must connect the appropriate pins/lands on all such agents.
Datasheet 65 Land Listi ng and Sign al Description s DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order co mple tion. Assertion of DEFER# is normally the responsibility of the addressed me mory or input/ output agent.
Land Listing and Signal Descriptions 66 Datasheet HIT# HITM# Input/ Output Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. An y FSB agent may assert both HIT# and HITM# together to indic ate that it requires a s noop stall, which can be continued by reassertin g HIT# and HITM# together .
Datasheet 67 Land Listi ng and Sign al Description s LOCK# Input/ Output LOCK# indicates to the syst em that a transaction must occur atomically . This signal must conn ect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions 68 Datasheet RS[2:0]# Input RS[2:0]# (R esponse Status) are driv en by the response agent (th e agent responsible for completion o f the current tr ansaction), and must connect th e appr opriate pins/lands of all processor FSB agents.
Datasheet 69 Land Listi ng and Sign al Description s THERMTRIP# Output In the even t of a catastrophic c ooling failure, the processo r will automatically sh ut down when the sili con has reached a temperature approximately 20 °C above the ma ximum T C .
Land Listing and Signal Descriptions 70 Datasheet § § VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V SS . VSS Input VSS are the ground pins for the pr ocessor and should be connected to the system ground plan e.
Datasheet 71 Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temper atures within the operating limits as set forth in Section 5.
Thermal Specifications and Design Considerations 72 Datasheet The case temperature is defined at the geometric top center of the processor . Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods.
Datasheet 73 Thermal Specifications and Design Considerations Table 27. Thermal Profile for 130 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 42.4 34 48.2 68 54.0 102 59.7 2 42.
Thermal Specifications and Design Considerations 74 Datasheet Table 28. Thermal Profil e for 105 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.3 28 48.3 56 53.4 84 58.4 2 43.
Datasheet 75 Thermal Specifications and Design Considerations Table 29. Thermal Profile 95 W Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.4 28 52.2 56 60.1 84 67.9 2 45.0 30 52.
Thermal Specifications and Design Considerations 76 Datasheet 5.1.2 Thermal Metrology The maximum and minimum case temper a tures (T C ) for the processor is specified in Ta b l e 2 6 . This temperature specification is meant to help ensure proper oper ation of the processor .
Datasheet 77 Thermal Specifications and Design Considerations under-designed ther mal solution that is not able to prev ent excessive activ ation of the TCC in the anticipated ambient environm ent may.
Thermal Specifications and Design Considerations 78 Datasheet The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 T CC cannot be activ ated via the on demand mode.
Datasheet 79 Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operat ing temperature.
Thermal Specifications and Design Considerations 80 Datasheet 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal mo nitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues.
Datasheet 81 Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1).
Thermal Specifications and Design Considerations 82 Datasheet.
Datasheet 83 Features 6 Features 6.1 Power-On Configuration Options Several configur ation options can be config ured by hardwa re. The processor samples the hardware configur ation at reset, on the active-to-inactive tr ansition of RESET#. For specifications on these options, refer to Ta b l e 3 1 .
Feature s 84 Datasheet 6.2.1 Normal State This is the normal operating state for the processor . 6.2.2 HALT and Extended HALT Powerdown States The processor supports the HAL T or Extended HAL T powerdown state. The Extended HAL T Powerdown must be enabled via the BIO S for the processor to remain within its specification.
Datasheet 85 Features The system can generate a STPCLK# while th e processor is in the HAL T Power Down state. When the system deasserts the ST PCLK# interrupt, the processor will return execution to the HAL T state. While in HAL T Power Down state, the processor will process bus snoops.
Feature s 86 Datasheet 6.2.4 Extended HALT Snoo p or HALT Snoop State, Stop Grant Snoop State The Extended HAL T Snoop State is used in conjunction with the new Extended HAL T state. If Extended HAL T state is not en abled in the BIOS, the default Snoop State entered will be the HA L T Snoop State.
Datasheet 87 Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor . Intel boxed processors are intended for system integr ators who build systems from baseboards and standard components.
Boxed Processor Specifications 88 Datasheet 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical spec ifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink.
Datasheet 89 Boxed Processor Specifications NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Boxed Processor Specifications 90 Datasheet 7.1.2 Boxed Processor Fan Heatsink Weight The boxed pro cessor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.
Datasheet 91 Boxed Processor Specifications Figure 26. Boxed Processo r Fan Heatsink Power Cable Connector Description Table 32. Fan Heatsink Powe r and Signal Specific ations Description Min Typ Max Unit Notes +12 V : 12 volt fan power supply 11.4 12 12.
Boxed Processor Specifications 92 Datasheet 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor . 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cool ed with a fan heatsink.
Datasheet 93 Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Ke epout Requirements (S ide 1 View) Figure 29. Boxed Processor Fan Heatsink Airspace Ke epout Requirements.
Boxed Processor Specifications 94 Datasheet 7.3.2 Fan Speed Control Operation (Intel ® Core™2 Extreme processors on ly) The box ed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control ov er fan speed.
Datasheet 95 Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designe d with a fan speed controller .
Boxed Processor Specifications 96 Datasheet If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard de signs.
Datasheet 97 Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (LAIs) for use in debugging systems. T ektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces.
Debug Tools Specifications 98 Datasheet.
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