Instruction/ maintenance manual of the product Intel Pentium Dual Core E2140 Fujitsu
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Document Number: 316981 -005 Intel ® Pentium ® Dual-Core Desktop Processor E2000 Δ Series Datasheet March 2008.
2 Datasheet INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL PRODUCTS . NO LICENSE, EXPRES S OR IMPLIED , BY EST OPPEL OR OTH ERW IS E , TO AN Y I NT EL LE CT UA L P RO PE RTY RI GH TS IS GR AN TE D B Y T H IS DOCUMENT .
Datasheet 3 Contents 1I n t r o d u c t i o n ......... ......... .......... ........... ........ ........... .......... ......... .......... ......... .......... .... 9 1.1 Terminology ........... .......... ......... .......... ........... .........
4 Datasheet 5.2.2 Thermal Monito r 2 ................. .......... ........... ........ ........... .......... ........... .... 78 5.2.3 On-Demand M ode ..... ......... .......... ........... .......... ......... .......... ........... ........79 5.2.4 PROCHOT# Sig nal .
Datasheet 5 Figures 1V CC Static and Transient Tolerance for Processors..... .... ........ ........... .......... ......... .......... 21 2V CC Overshoot Examp le Waveform .............. ........... .......... ........... .......... ........... ......
6 Datasheet Tables 1 References ............... ......... .......... ........... ........ ........... .......... ......... .......... ........... ......11 2 Voltage Identification Definition .... ........... .......... ......... .......... ...........
Datasheet 7 Intel ® Pentium ® Dual-Core Desktop Processor E2000 Δ Series The Intel Pentium ® Dual-Core desktop processor E2000 serie s deliver Intel's advanced, powerful processors for desktop PCs.
8 Datasheet Revision History § § Revision Number Description Date -001 • Initial release June 2007 -002 • Added specifications for Intel ® Pen tiu m ® Dual-Core Desktop processor E2180 August .
Datasheet 9 Introduction 1 Introduction The Intel ® Pen t i um ® Dual-Core Desktop processor E2000 series combines the performance of the current gener ation of de sktop products with the power efficiencies of a low-power microarchitecture to enable smaller , quieter systems.
Introduction 10 Datasheet 1.1.1 Processor Terminology Commonly used terms are expl ained here for clarification: • Intel ® Pentium ® Dual-Core Desktop pr ocessor E2000 series — Dual core processor in the FC -LGA6 package with a 1 MB L2 cache.
Datasheet 11 Introduction 1.2 References Material and concepts available in the fo llowing documents may be beneficial when reading this document. § § Table 1. References Document Location Intel ® Pentium ® Dual-Core Desktop Proce ssor E2000 Series Specification Update http://www.
Introduction 12 Datasheet.
Datasheet 13 Electrical Specifications 2 Electrical Specifications This chapter describes the electrical charac teristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VT T and VSS (ground) inputs for on-chip power distribution.
Electrical Specifications 14 Datasheet 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, so me of the high frequency capacitance required for the FSB is included on the processor package.
Datasheet 15 Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX VID6 VID5 VID4 VID3 VID2 VI D1 V CC_MAX 1 1 11 01 0 . 8 5 0 0 0 11110 1 . 2 3 7 5 1 1 11 00 0 . 8 6 2 5 0 11101 1 . 2 5 0 0 1 1 10 11 0 .
Electrical Specifications 16 Datasheet 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outp uts to determine the Market Segmen t of the processor . Ta b l e 3 provides details regarding the state of MSID[1:0]. A circuit can be used to preven t 130 W TDP processors from booting on boards optimized for 65 W TDP .
Datasheet 17 Electrical Specifications The TESTHI signals ma y use individual pull-u p resistors or be grouped together as detailed below. A matched resistor must be used for each group: • TESTHI[1:.
Electrical Specifications 18 Datasheet NOTES: 1. For functional oper ation, all processor electrical, signal qu ality , mechanical and thermal specificati ons must be sat isfied. 2. Excessive overshoot or un dersh oot on any signal wi ll likely result in permanent damage to the processor .
Datasheet 19 Electrical Specifications 2.6.2 DC Voltage and Cu rrent Sp ecification Table 5. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1, 2 NOTES: 1. Unless oth erwise note d, all specific ations in thi s table are based on estimates and si mulations or empirical data.
Electrical Specifications 20 Datasheet Table 6. V CC Static and Transient Tolerance for Pr ocessors I CC (A) Voltage Deviation from VID Setting (V) 1, 2, 3, 4 NOTES: 1. The loadline specification incl udes both static and tr ansient limits exc ept for overshoot allowe d as shown in Section 2.
Datasheet 21 Electrical Specifications NOTES: 1. The loadline specification includes bot h static and transient li mits except for overshoo t allowed as shown in Section 2.6 .3 . 2. This loadlin e specificati on shows the de viation from th e VID set point.
Electrical Specifications 22 Datasheet NOTES: 1. V OS is measured overshoot voltage. 2. T OS is measured time dur ation above VID. 2.6.4 Die Voltage Validation Overshoot events on processor mu st meet the specifications in Ta b l e 7 when measured across the VCC_SENSE and VSS_SENSE lands.
Datasheet 23 Electrical Specifications 2.7.1 FSB Signal Groups The front side bus sign als have be en combined into groups b y buffer type. GTL+ input signals have differential input buffers, whic h use GTLREF[1:0] as a reference level.
Electrical Specifications 24 Datasheet 3. The value of these signals during the acti ve-to- inactive e dge of RESET# defines the processor configuratio n options. See Section 6.1 for details. 4. PROCHOT# signal type is open dr ain output and CMOS input.
Datasheet 25 Electrical Specifications 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.
Electrical Specifications 26 Datasheet . 2.7.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integr ated into the processor silicon. See Ta b l e 9 for details on which GTL+ signals do not include on-die termination.
Datasheet 27 Electrical Specifications Table 14. G TL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes 1 NOTES: 1. Unless otherwise not ed, all specifications in this table apply to all proce ssor frequencies. GTLREF_PU GTLREF pull up resistor on Intel 975X and 96x Ex press Chipset family boards 124 * 0.
Electrical Specifications 28 Datasheet 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking BCLK[1:0] directly controls the FS B interface speed as well as the core frequency of the processor . As in previous generation processors, the processor’ s core frequency is a multiple of the BCLK[1:0] frequency .
Datasheet 29 Electrical Specifications 2.8.3 Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor . The VCCPLL input is used for the PLL. R efer to Ta b l e 5 for DC speci fications. 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) Table 16.
Electrical Specifications 30 Datasheet Figure 3. D ifferential Clock Waveform Figure 4. D ifferential Clock Crosspoint Specification High Time Period V CROSS CLK 1 CLK 0 Low Time V CROSS Min 300 mV V .
Datasheet 31 Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifica tions Symbol Parameter Min Typ Max Unit Figure Notes 1 NOTES: 1. Unless otherwise no ted, all specifi cations in this table apply to al l processor frequencies.
Electrical Specifications 32 Datasheet 2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication ch annel between Intel processors (may also include chipset components in the futu re) and external thermal monitoring devices.
Datasheet 33 Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-L GA6) package that interfaces with the motherboar d via an LG A775 sock et. The package consists of a processor core mounted on a substrate land-carrier .
Package Mechanical Specifications 34 Datasheet Figure 8. Processor Package Drawing Sheet 1 of 3.
Datasheet 35 Package Mechanical Specifications Figure 9. Processor Package Drawing Sheet 2 of 3.
Package Mechanical Specifications 36 Datasheet Figure 10. Processor Package Drawing Sheet 3 of 3.
Datasheet 37 Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must n ot intrude into the required keep-out zones.
Package Mechanical Specifications 38 Datasheet 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide .
Datasheet 39 Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the docume nt to identify processor lands.
Package Mechanical Specifications 40 Datasheet.
Datasheet 41 Land Listi ng and Sign al Description s 4 Land Listing and Signal Descriptions This chapter provides the processor la nd assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for th e processor .
Land Listing and Signal Descriptions 42 Datasheet Figure 13. land-out Diagram (Top View – Lef t Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VC C VSS VSS VCC VCC VSS .
Datasheet 43 Land Listi ng and Sign al Description s Figure 14. land-out Diagram (Top View – Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VS S VCC VCC VID_SELE CT VSS_MB_ REGULA TION.
Land Listing and Signal Descriptions 44 Datasheet Table 23. Alphabetical Land Assignments Land Name Land # Signal Buffer Type Direction A3# L5 S ource Synch Input/Output A4# P6 Source Synch Input/Outp.
Land Listi ng and Sign al Description s Datasheet 45 D22# D10 Source Synch Input/Output D23# F11 Source Sync h Input/Output D24# F12 Source Sync h Input/Output D25# D13 Source Synch Input/Output D26# .
Land Listing and Signal Descriptions 46 Datasheet FC33 H16 Power/Other FC34 J17 P ower/Other FC35 H4 P ower/Other FC36 AD3 Power/Other FC37 AB3 Power/Other FC38 G10 Power/Other FC38 C9 Power/Ot her FC.
Land Listi ng and Sign al Description s Datasheet 47 TRDY# E3 Com mon Cloc k Inp ut TRST# AG1 T AP Input VCC AA8 Power/Oth er VCC AB8 Power/O ther VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Po.
Land Listing and Signal Descriptions 48 Datasheet VCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power/Other VCC AJ26 Power/Other VCC AJ8 Power/Other VCC .
Land Listi ng and Sign al Description s Datasheet 49 VCC J28 Power/Othe r VCC J29 Power/Othe r VCC J30 Power/Othe r VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Othe r VCC K24 Power/Othe r VCC .
Land Listing and Signal Descriptions 50 Datasheet VID0 AM2 Power/Other Output VID1 AL5 Power/O ther Output VID2 AM3 Power/Other Output VID3 AL6 Power/O ther Output VID4 AK4 Power/O ther Output VID5 AL.
Land Listi ng and Sign al Description s Datasheet 51 VSS AG2 3 Power/Other VSS AG2 4 Power/Other VSS AG7 Powe r/Other VSS AH1 Power/Other VSS AH10 Power/Other VSS AH13 Power/Other VSS AH16 Power/Other.
Land Listing and Signal Descriptions 52 Datasheet VSS B24 Power/Other VSS B5 Powe r/Other VSS B8 Powe r/Other VSS C10 Power/Ot her VSS C13 Power/Ot her VSS C16 Power/Ot her VSS C19 Power/Ot her VSS C2.
Land Listi ng and Sign al Description s Datasheet 53 VSS N6 Power/Oth er VSS N7 Power/Oth er VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28.
Land Listing and Signal Descriptions 54 Datasheet Table 24. Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 V SS Power/Other A3 RS2# Common Clo ck Input A4 D02# Source Synch.
Land Listi ng and Sign al Description s Datasheet 55 C20 D BI3# Source Synch Input/Output C21 D58# Source Synch Input/Output C22 VSS Power/Ot her C23 VCCIOPLL Power/Other C24 VSS Power/Ot her C25 VTT .
Land Listing and Signal Descriptions 56 Datasheet F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output F15 D30# Source Synch Inp.
Land Listi ng and Sign al Description s Datasheet 57 H30 BSEL1 Power/Other Output J1 VT T_OUT_LEF T Power/Other Output J2 FC3 Power/Other J3 FC22 Power/Other J4 VSS Power/Other J5 REQ1# Source Synch I.
Land Listing and Signal Descriptions 58 Datasheet M30 VCC Power/O ther N1 PWRGO OD Power/Other Input N2 IGNNE# Asynch CMOS Input N3 VSS Power/Other N4 RESERVED N5 RESERVED N6 VSS Power/Other N7 VSS Po.
Land Listi ng and Sign al Description s Datasheet 59 U28 VCC P ower/Other U29 VCC P ower/Other U30 VCC P ower/Other V1 MSID1 Power/Other Output V2 RESERVED V3 VSS Power/ Other V4 A15# Source Synch Inp.
Land Listing and Signal Descriptions 60 Datasheet AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other AC1 TMS T AP Input AC2 DBR# Power/Other Outpu.
Land Listi ng and Sign al Description s Datasheet 61 AF12 VC C Power/Other AF13 VSS Power/Ot her AF14 VC C Power/Other AF15 VC C Power/Other AF16 VSS Power/Ot her AF17 VSS Power/Ot her AF18 VC C Power.
Land Listing and Signal Descriptions 62 Datasheet AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CLK1 T AP Input AJ4 VSS Power/Ot her AJ5 A34# Sou.
Land Listi ng and Sign al Description s Datasheet 63 AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power/Other AL23 VSS Power/Other AL24 VSS Power/Other .
Land Listing and Signal Descriptions 64 Datasheet 4.2 Alphabetical Signals Reference Table 25. Signal Descript ion (Sheet 1 of 9) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the addr ess phas e, these si gnals tran smit the address of a transaction.
Land Listi ng and Sign al Description s Datasheet 65 BPM[5:0]# Input/ Output BPM[5:0]# (Breakpoint Moni tor) are breakpoint and performance monitor signal s. They are outpu ts from the processor whi ch indicate the status of breakpoints and progr ammable counters used for monitoring processor performance .
Land Listing and Signal Descriptions 66 Datasheet D[63:0]# Input/ Output D[63:0]# (Data) are the data signal s. These signal s provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents.
Land Listi ng and Sign al Description s Datasheet 67 DEFER# Input DEFER# is asserted by an agent to indicate that a tr ansact ion cannot be ensured in-order completion. As sertion of DEFER# is normall y the responsibil ity of the addresse d me mory or input/output ag ent.
Land Listing and Signal Descriptions 68 Datasheet HIT# HITM# Input/ Output Input/ Output HIT# (Snoop Hit) and HITM# (Hit Modif ied) conve y transact ion snoop operation results. Any FSB agen t may assert both HIT# and HITM# together to indicat e that it requires a snoop stall, which can be continued by reassertin g HIT# and HITM# together .
Land Listi ng and Sign al Description s Datasheet 69 LOC K# Input/ Output LOCK# indicates to the sy stem that a transaction mu st occur atomically . This signal must connect th e appropri ate pins/lands of all processor FSB agents .
Land Listing and Signal Descriptions 70 Datasheet RS[2:0]# Input RS[2:0]# (Response Status ) are driven by the response agen t (the agent responsible for comple tion of the current transaction), and must connect the appropriate pins/l ands of all proc essor FSB agents.
Datasheet 71 Land Listi ng and Sign al Description s THERMTRIP# Output In the event of a catastrophic c ooling failure, the processor will automatically s hut down when the sili con has reached a tempe rature approximately 20 °C above the m aximum T C .
Land Listing and Signal Descriptions 72 Datasheet § § VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will no t boot on legacy platforms where this land is connec ted to V SS . VSS Inp ut VSS are the ground pins for the pr ocessor and should be connected to the system ground plane.
Datasheet 73 Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temper atures within the operating limits as described in Section 5 .
Thermal Specifications and Design Considerations 74 Datasheet The case temperature is defined at the geometric top center of the processor . Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods.
Datasheet 75 Thermal Specifications and Design Considerations Table 27. Thermal Profile (Intel ® Pentium ® Dual-Core Processors with CPUID = 06F2h) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 24 49.9 48 56.
Thermal Specifications and Design Considerations 76 Datasheet Table 28. Thermal Profi le (Intel ® Pentium ® Dual-Core Processors with CPUID = 06FDh ) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 45.3 2 4 55.6 48 65.
Datasheet 77 Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temper atures (T C ) for the processor is specified in Ta b l e 2 6 . This temperature specification is meant to help ensure proper operation of the processor .
Thermal Specifications and Design Considerations 78 Datasheet under-designed thermal solution that is not ab le to prev ent excessive activ ation of the TCC in the anticipated ambient environment may .
Datasheet 79 Thermal Specifications and Design Considerations The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Therma l Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 T CC cannot be activated via the on demand mode.
Thermal Specifications and Design Considerations 80 Datasheet 5.2.4 PROCHOT# Signal An external signal, PROCHO T# (processor hot), is asserted when the processor core temperature has reached its maximum oper ating temperature.
Datasheet 81 Thermal Specifications and Design Considerations 5.3 Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its colle ctor shorted to grou nd.
Thermal Specifications and Design Considerations 82 Datasheet NOTES: 1. Intel does not support or re commend operation of the thermal diode under revers e bias. 2. Same as I FW in Ta b l e 2 9 . 3. Preliminar y data. Will be char acterized ac ross a temper ature ra nge of 50–80 °C.
Datasheet 83 Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction PECI offers an interface for thermal m o nitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues.
Thermal Specifications and Design Considerations 84 Datasheet . . Figure 20. C onceptual Fan Cont rol on PECI-Based Platforms Mi n Max Fan Sp eed (R PM ) T CONTROL Set t i ng TCC Ac t i v at i on Tem perat ur e PECI = 0 PECI = -10 PECI = -20 Tem perat ur e N ot e: N ot inte nd e d to de pic t a ctu al im p lem en tat ion Figure 21.
Datasheet 85 Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification .
Thermal Specifications and Design Considerations 86 Datasheet.
Datasheet 87 Features 6 Features 6.1 Power-On Configuration Options Several configur ation options can be config ured by hardw are. The processor samples the hardware configur ation at reset, on the active-to-inactiv e transition of RESET#. For specifications on these options, refer to Ta b l e 3 3 .
Feature s 88 Datasheet 6.2 Clock Control and Low Power States The processor allows the use of AutoHAL T and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of th e processor , depending on each particular state.
Datasheet 89 Features 6.2.2.1 HALT Powerdown Stat e HAL T is a low power state entered when all the process or cores have executed the HAL T or MWAIT instructions. When one of the processor cores executes the HAL T instruction, that processor core is halted, however , the other processor continues normal operation.
Feature s 90 Datasheet 6.2.3.1 Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor -issued Stop Grant Acknowledge special bus cycle.
Datasheet 91 Features 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID oper ating point of the Extended HAL T state or Extended Stop Grant state.
Feature s 92 Datasheet.
Datasheet 93 Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor . Intel boxed processors are intended for system integr ators who build systems from baseboards and standard components.
Boxed Processor Specifications 94 Datasheet 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical spec ifications of the boxed processor . The boxed processor will be shipped with an unattached fan heatsink.
Datasheet 95 Boxed Processor Specifications NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Boxed Processor Specifications 96 Datasheet 7.1.2 Boxed Processor Fan Heatsink Weight The boxed pro cessor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate Thermal and Mech anical Design Guidelines (see Section 1.2 ) for details on the processor weight and heatsink requirements.
Datasheet 97 Boxed Processor Specifications Figure 27. Boxed Processo r Fan Heatsink Power Cable Conn ector Description Table 34. Fan Heatsink Powe r and Signal Specifications Description Min Typ Max Unit Notes +12 V : 12 v olt fan power supply 11.4 12 12.
Boxed Processor Specifications 98 Datasheet 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor . 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cool ed with a fan heatsink.
Datasheet 99 Boxed Processor Specifications Figure 29. Boxed Processor Fa n Heatsink Airspace Keepo ut Requirements (side 1 view) Figure 30. Boxed Processor Fan He atsink Airspace Keepout Requir ement.
Boxed Processor Specifications 100 Datasheet 7.3.2 Fan Speed Control Operation (Intel ® Pentium ® Dual-Core Desktop Processor E2000 Series) If the boxed processor f an heatsink 4-pin connector is co.
Datasheet 101 Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designe d with a fan speed controller.
Boxed Processor Specifications 102 Datasheet.
Datasheet 103 Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (LAIs) for use in debugging systems. T ektronix and Agilent should be contacte d to get specific information about their logic analyzer interfaces.
Debug Tools Specifications 104 Datasheet.
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