Instruction/ maintenance manual of the product KS57C2308 Samsung
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KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW OVERVIEW The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high perfo rmance using Samsung's newest 4- bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
PRODUCT OVERVIEW KS57C2308/P2308/C23 16/P2316 1- 2 FEATURES Memory – 512 × 4-bit RAM – 8 K × 8-bit ROM (KS57C2308/P2308) – 16 K × 8-bit ROM (KS57C2316/P2316) I/O Pins – Input only: 8 pins .
KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM Interrupt Control Block Instruction Register Program Counter Program Status Word Stack Pointer Arithmetic and Logic Unit Instruction Decoder Clock RESET X IN XT IN Internal Interrupts INT0, INT1,INT2 P3.
PRODUCT OVERVIEW KS57C2308/P2308/C23 16/P2316 1- 4 PIN ASSIGNMENTS SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P 7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.
KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW 1- 5 PIN DESCRIPTIONS Table 1 - 1. KS57C2308/C2316 Pin Descriptions Pin Name Pin Type Description Number Share Pin Reset Value Circuit Type P0.0 P0.1 P0.2 P0.3 I I/O I/O I 4-bit input port. 1-bit and 4-bit read and test are possible.
PRODUCT OVERVIEW KS57C2308/P2308/C23 16/P2316 1- 6 Table 1 - 1. KS57C2308/C2316 Pin Descriptio ns (Continued) Pin Name Pin Type Description Number Share Pin Reset Value Circuit Type LCDSY I/O LCD synchronization clock output for LCD display expan sion 33 P3.
KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW 1- 7 PIN CIRCUIT DIAGRAMS V DD P-CHANNEL IN N-CHNNEL Figure 1 -3 . Pin Circuit Type A SCHMITT TRIGGER V DD IN P-CHANNEL PULL-UP RESISTOR RESISTOR ENABLE Figure 1 -4 . Pin Circuit Type A-1 (P1, P0.0, P0.3) V DD P-CHANNEL DATA OUTPUT DISABLE N-CHANNEL OUT Figure 1 -5 .
PRODUCT OVERVIEW KS57C2308/P2308/C23 16/P2316 1- 8 DATA OUTPUT ENABLE V DD P - CH RESISTOR ENABLE N-CH PULL-UP RESISTOR I/O CIRCUIT TYPE A V DD PNE Figure 1 -7 .
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 1 2 ADDRESS SPACES PROGRAM MEMORY (ROM) OVERVIEW ROM maps for KS57C2 308/C2316 devices are mask programmable at the factory.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 2 GENERAL-PURPOSE MEMORY AREAS The 20-byte area at ROM locations 000C H–001FH and the 8,064 -byte (16,256 -byte ) area at ROM locations 0080H– 1 FFFH ( 0080H– 3 FFFH ) are used as general-purpose program memory.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 3 + + P ROGRAMMING TIP — Defining Vectored Interrupts The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 4 INSTRUCTION REFERENCE AREA Using 1-byte REF instructions, you can easily reference instructions with larger b yte sizes that are stored in ad dresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up table.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 5 DATA MEMORY (RAM) OVERVIEW In its standard configuration, the 512 x 4 -b it data memory has four areas: — 32 × 4-bit working register area in bank 0.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 6 Memory Banks 0, 1, and 15 Bank 0 (000H–0FFH) The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers; the next 224 nibbles (020H–0FFH) can be used both as stack area and as general-purpose data memory.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 7 Table 2- 2. Data Memory Organization and Addressing Addresses Register Areas Bank EMB Value SMB Value 000H–01FH Working registers 0 0, 1 0 020H–0FF.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 8 WORKING REGISTERS Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 9 Working Register Banks For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2, and bank 3.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 10 Special-Purpose Working Registers Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also be used as a 1-bit accumulator. 8-bit double registers WX, WL and HL are used as data pointers for indirect addressing.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 11 + + PROGRAMMING TIP — Selecting the Working Register Area The following examples show the correct programming method for selecting working register area: 1.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 12 STACK OPERATIONS STACK POINTER (SP) The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 13 PUSH OPERATIONS Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack: PUSH instructions, CALL instructions, and interrupts.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 14 POP OPERATIONS For each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for interrupts, the instruction IRET.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 15 BIT SEQUENTIAL CARRIER (BSC) The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to logic zero.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 16 PROGRAM COUNTER (PC) A 13 -bit program counter (PC) stores addresses for instruction f etches during program execution (KS57C2316 microcontroller has 14-bit program counter, PC0–PC13).
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 17 INTERRUPT STATUS FLAGS (IS0, IS1) PSW bits IS0 and IS1 contain the current interrupt execution status values.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 18 EMB FLAG (EMB) The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1 or 15.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 19 ERB FLAG (ERB) The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (SRB).
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 20 SKIP CONDITION FLAGS (SC2, SC1, SC0) The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions.
KS57C2308/P2308/C2316/P2316 ADDRESS SPACES 2 - 21 + + PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator 1. Set the carry flag to logic one: SCF ; C ← 1 LD EA,#0C3H ; EA ← #0C3H LD HL,#0AAH ; HL ← #0AAH ADC EA,HL ; EA ← #0C3H + #0AAH + #1H, C ← 1 2.
ADDRESS SPACES KS 57C2308/P2308/C2316/P2316 2 - 22 NOTES.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 1 3 ADDRESSING MODES OVERVIEW The enable memory bank flag, EMB, controls the two addressing modes for data memory.
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 2 DA DA.b @HL @H + DA.b @WX @WL mema.b memb.@L EMB = 0 EMB = 1 X X X 000H Working Registers BANK 0 (General Registers and Stack ) 01FH 020H 0FFH 100H 1DFH 1E0H BANK 1 (General Registers) RAM Areas Addressing Mode NOTES 1.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 3 EMB AND ERB INITIALIZATION VALUES The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, initializing it automatically.
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 4 ENABLE MEMORY BANK SETTINGS EMB = "1" When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by the select memory bank (SMB) value (0, 1 or 15) using 1-, 4-, or 8-bit instructions.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 5 SELECT BANK REGISTER (SB) The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register con sists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in Figure 3- 2.
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 6 DIRECT AND INDIRECT ADDRESSING 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. Indirect addressing specifies a memory location that contains the required direct address.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 7 + + PROGRAMMING TIP — 1-Bit Addressing Modes 1-Bit Direct Addressing 1. If EMB = "0": AFLAG EQU 34H.3 BFLAG EQU 85H.3 CFLAG EQU 0BAH.0 SMB 0 BITS AFLAG ; 34H.3 ← 1 BITS BFLAG ; F85H.3 ← 1 BTST CFLAG ; If FBAH.
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 8 4-BIT ADDRESSING Table 3- 3. 4-Bit Direct and Indirect RAM Addressing Operand Notation Addressing Mode Description EMB Flag Setting Addressable Area.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 9 + + PROGRAMMING TIP — 4-Bit Addressing Modes (Continued) 4-Bit Indirect Addressing (Example 1) 1. If EMB = "0", compare bank 0 locations .
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 10 4-Bit Indirect Addressing (Example 2) 1. If EMB = "0", exchange bank 0 locations 040H–046H with bank 0 locations 060H–066H: ADATA EQU.
KS57C2308/P2308/C2316/P2316 ADDRESSING MODES 3 - 11 8-BIT ADDRESSING Table 3- 4. 8-Bit Direct and Indirect RAM Addressing Instruction Notation Addressing Mode Description EMB Flag Setting Addressable .
ADDRESSING MODES KS5 7C2308/P2308/C2316/P2316 3 - 12 + + PROGRAMMING TIP — 8-Bit Addressing Modes (Continued) 8-Bit Indirect Addressing 1. If EMB = "0": ADATA EQU 46H SMB 1 ; Non-essential instruction, since EMB = "0" LD HL,#ADATA LD EA,@HL ; A ← (046H), E ← (047H) 2.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 1 4 MEMORY MAP OVERVIEW To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location.
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 2 Table 4- 1. I/O Map for Memory Bank 15 Memory Bank 15 Addressing Mode Address Register Bit 3 Bit 2 Bit 1 Bit 0 R/W 1-Bit 4-Bit 8-Bit F80H SP .3 .2 .1 "0" R/W No No Yes F81H .7 .6 .5 .4 F82H SB “0” “0” SRB1 SRB0 – No No No F83H SMB3 SMB2 SMB1 SMB0 Location, F84H, is not mapped.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 3 Table 4- 1. I/O Map for Memory Bank 15 (Continued) Memory Bank 15 Addressing Mode Address Register Bit 3 Bit 2 Bit 1 Bit 0 R/W 1-Bit 4-Bit 8-Bit FB7H SCMOD .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 4 Table 4- 1. I/O Map for Memory Bank 15 (Concluded) Memory Bank 15 Addressing Mode Address Register Bit 3 Bit 2 Bit 1 Bit 0 R/W 1-Bit 4-Bit 8-Bit FF0H Port 0 .3 .2 .1 .0 R Yes Yes No FF1H Port 1 .3 .2 .1 .0 R Yes Yes No FF2H Port 2 .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 5 CLMOD − − Clock Output Mode Control Register FD0H Bit Identifier RESET Value Read/Write Bit Addressing CLMOD.
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 6 BMOD — Basic Timer Mode Register F85H Bit 3210 Identifier .3 .2 .1 .0 RESET Value 0000 Read/Write WWWW Bit Addressing 1/4 444 .3 Basic Timer Restart Bit 1 Restart basic timer, then clear IRQB flag, BCNT and BMOD.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 7 CLMOD — Clock Output Mode Register FD0H Bit 3210 Identifier .3 "0" .1 .0 RESET Value 0000 Read/Write WWWW Bit Addressing 4444 .3 Enable/Disable Clock Output Control Bit 0 Disable clock output 1 Enable clock output .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 8 IE0, 1 , IRQ0, 1 — INT0, 1 Interrupt Enable/Request Flags FBEH Bit 3210 Identifier IE1 IRQ1 IE0 IRQ0 RESET Value 0000 Read/Write R/W R/W R/W R/W Bit Addr.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 9 IE2 , IRQ2 — INT2 Interrupt Enable/Request Flags FBFH Bit 3210 Identifier "0" "0" IE2 IRQ2 RESET Value 0000 Read/Write R/W R/W R/W R/W Bit Addressing 1/4 1/4 1/4 1/4 .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 10 IE4 , IRQ4 — INT4 Interrupt Enable/Request Flags FB8H IEB, IRQB — INTB Interrupt Enable/Request Flags FB8H Bit 3210 Identifier IE4 IRQ4 IEB IRQB RESET.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 11 IES , IRQS — INTS Interrupt Enable/Request Flags FBDH Bit 3210 Identifier "0" "0" IES IRQS RESET Value 0000 Read/Write R/W R/W R/W R/W Bit Addressing 1/4 1/4 1/4 1/4 .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 12 IET0 , IRQT0 — INTT0 Interrupt Enable/Request Flags FBCH Bit 3210 Identifier "0" "0" IET0 IRQT0 RESET Value 0000 Read/Write R/W R/W R/W R/W Bit Addressing 1/4 1/4 1/4 1/4 .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 13 IEW , IRQW — INTW Interrupt Enable/Request Flags FBAH Bit 3210 Identifier "0" "0" IEW IRQW RESET Value 0000 Read/Write R/W R/W R/W R/W Bit Addressing 1/4 1/4 1/4 1/4 .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 14 IMOD0 — External Interrupt 0 (INT0) Mode Register FB4H Bit 3210 Identifier .3 "0" .1 .0 RESET Value 0000 Read/Write WWWW Bit Addressing 4444 .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 15 IMOD1 — External Interrupt 1 (INT1) Mode Register FB5H Bit 3 2 1 0 Identifier "0" "0" "0" IMOD1.0 RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 4 4 4 4 .3–.1 Bits 3–1 0 Always logic zero .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 16 IMOD2 — External Inte rrupt 2 (INT2) Mode Register FB6 H Bit 3 2 1 0 Identifier "0" IMOD2.2 IMOD2.1 IMOD2.0 RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 4 4 4 4 .3 Bits 3 0 Always logic zero .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 17 IPR — Interrupt Priority Register FB2H Bit 3210 Identifier IME .2 .1 .0 RESET Value 0000 Read/Write WWWW Bit Addressing 1/4 444 IME Interrupt Master Enable Bit 0 Disable all interrupt processing 1 Enable processing for all interrupt service requests .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 18 LCON — LCD Output Control Register F8EH Bit 3210 Identifier "0" .2 " 0 " .0 RESET Value 0000 Read/Write WWWW Bit Addressing 4444 .3 LCD Bias Selection Bit 0 This bit is used for internal testing only; always logic zero.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 19 LMOD — LCD Mode Register F8DH, F8CH Bit 7 6 5 4 3 2 1 0 Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit Addressing 8 8 8 8 1/ 8 8 8 8 .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 20 PCON — Power Control Register FB3H Bit 3210 Identifier .3 .2 .1 .0 RESET Value 0000 Read/Write WWWW Bit Addressing 4444 .3–.2 CPU Operating Mode Control Bits 0 0 Enable normal CPU operating mode 0 1 Initiate idle power-down mode 1 0 Initiate stop power-down mode .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 21 PMG1 — Port I/O Mode Flags (Group 1: Port 3 and 6) FE9H, FE8 H Bit 76543210 Identifier PM6.3 PM 6 .2 PM 6 .1 PM6 .0 PM 3 .3 PM 3 .2 PM 3 .1 PM 3 .0 RESET Value 00000000 Read/Write WWWWWWWW Bit Addressing 88888888 PM6.
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 22 PMG2 — Port I/O Mode Flags (Group 2: Port 2, 4, 5, and 7) FEDH, FEC H Bit 76543210 Identifier PM7 “0” PM5 PM4 “0” PM2 “0” “0” RESET Value 00000000 Read/Write WWWWWWWW Bit Addressing 88888888 PM7 P7 I/O Mode Selection Flag 0 Set P7 to input mode 1 Set P7 to output mode .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 23 PNE — N-Ch annel Open-Drain Mode Register FD7H, FD6 H Bit 76543210 Identifier PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3 PNE4.2 PNE4.1 PNE4.0 RESET Value 00000000 Read/Write WWWWWWWW Bit Addressing 88888888 PNE5.
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 24 PSW — Program Status Word FB1H, FB0H Bit 76543210 Identifier C SC2 SC1 SC0 IS1 IS0 EMB ERB RESET Value (1) 0000000 Read/Write R/W RRR R/W R/W R/W R/W Bi.
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 25 PUMOD — Pull-Up Resistor Mode Register FDDH, FDCH Bit 76543210 Identifier PUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0 RESET Value 00000000 Read/Write WWWWWW.
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 26 SCMOD — System Clock Mode Control Register FB7H Bit 3 2 1 0 Identifier .3 .2 "0" .0 RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 1 1 1 1 .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 27 SMOD — Serial I/O Mode Register FE1H, FE0H Bit 76543210 Identifier .7 .6 .5 "0" .3 .2 .1 .0 RESET Value 00000000 Read/Write WWWW R/ W W W W Bit Addressing 8888 1/8 888 .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 28 TMOD0 — Timer/Counter 0 Mode Register F91H, F90H Bit 76543210 Identifier "0" .6 .5 .4 .3 .2 "0" "0" RESET Value 00000000 Read/Write WWWWWWWW Bit Addressing 8888 1/8 888 .7 Bit 7 0 Always logic zero .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 29 TOE — Timer Output Enable Flag Register F92H Bit 3210 Identifier “U” TOE0 “U” “U” RESET Value 0000 Read/Write – R/W – – Bit Addressing –1–– .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 30 WDFLAG — Watchdog Timer Counter Clear Flag Register F9AH Bit 3 2 1 0 Identifier WDTCF “0” “0” “0” RESET Value 0 0 0 0 Read/Write W W W W Bit Addressing 1/4 1/4 1/4 1/4 WDTCF Watchdog Timer Counter Clear Flag 1 Clears the watchdog timer counter .
KS57C2308/P2308/C2316/P2316 MEMORY MAP 4 - 31 WDMOD — Watchdog Timer Mode Register F99H, F98H Bit 7 6 5 4 3 2 1 0 Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 1 0 1 0 0 1 0 1 Read/Write W W W W W .
MEMORY MAP KS57C2308/P2308/C2316/P2316 4 - 32 WMOD — Watch Timer Mode Register F89H, F88H Bit 76543210 Identifier .7 "0" .5 .4 .3 .2 .1 .0 RESET Value 0000 ( note ) 000 Read/Write WWWW R WWW Bit Addressing 88881888 .7 Enable/Disable Buzzer Output Bit 0 Disable buzzer (BUZ) signal output 1 Enable buzzer (BUZ) signal output .
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 1 5 SAM47 INSTRUCTION SET OVERVIEW The SAM47 instruction set is specifically designed to support the large register files that are typical of most KS57-series microcontrollers.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 2 Instruction Reference Area Using the 1-byte REF (Reference) instruction, you can reference instructions stored in the addresses 0020H–007FH of program memory (the REF instruction look-up table).
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 3 Reducing Instruction Redundancy When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence, only the first instruction is executed, but the following redundant instructions are ignored, that is, they are handled like a NOP instruction.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 4 Flexible Bit Manipulation In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit addressing modes.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 5 ADC and SBC Instruction Skip Conditions The instructions “ADC A,@HL” and “SBC A,@HL” can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction “ADS A,#im”.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 6 SYMBOLS and CONVENTIONS Table 5-4. Data Type Symbols Symbol Data Type d Immediate data a Address data b Bit data r Register data f Flag data i Indirect addressing data t memc × 0.5 immediate data Table 5-5.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 7 OPCODE DEFINITIONS Table 5-7. Opcode Definitions (Direct) Register r2 r1 r0 A 000 E 001 L 0 1 0 H 011 X 100 W 101 Z 110 Y 111 EA 000 HL 010 WX 100 YZ 110 r = Immediate data for register Table 5-8.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 8 HIGH-LEVEL SUMMARY This section contains a high-level summary of the SAM47 instruction set in table format. The tables are designed to familiarize you with the range of instructions that are available in each instruction category.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 9 Table 5-9. CPU Control Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles SCF Set carry flag to logic one 1 1 R.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 10 Table 5-11. Data Transfer Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles XCH A,DA Exchange A and direct da.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 11 Table 5-12. Logic Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles AND A,#im Logical-AND A immediate data to.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 12 Table 5-14. Bit Manipulation Instructions — High-Level Summary Name Operand Operation Description Bytes Cycles BTST C Test specified bit and skip if carry flag is set 1 1 + S DA.b Test specified bit and skip if memory bit is set mema.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 13 BINARY CODE SUMMARY This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are experienced with the SAM47 instruction set.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 14 Table 5-15. CPU Control Instructions — Binary Code Summary Name Operand Binary Code Operation Notation SCF 11100111 C ← 1 RCF 11100110 C ← 0 CCF 11010110 C ← C EI 11111111 IME ← 1 10110010 DI 11111110 IME ← 0 10110010 IDLE 11111111 PCON.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 15 Table 5-16. Program Control Instructions — Binary Code Summary Name Operand Binary Code Operation Notation CPSE R,#im 11011001 Skip if R = im.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 16 Table 5-16. Program Control Instructions — Binary Code Summary (Continued) Name Operand Binary Code Operation Notation RET – 11000101 PC13.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 17 Table 5-17. Data Transfer Instructions — Binary Code Summary (Continued) Name Operand Binary Code Operation Notation LD Ra,#im 11011001 Ra .
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 18 Table 5-17. Data Transfer Instructions — Binary Code Summary (Concluded) Name Operand Binary Code Operation Notation POP RR 00101 r2 r1 0 RR L ← (SP), RR H ← (SP + 1) SP ← SP + 2 SB 11011101 (SRB) ← (SP), SMB ← (SP + 1), SP ← SP + 2 01100110 Table 5-18.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 19 Table 5-19. Arithmetic Instructions — Binary Code Summary Name Operand Binary Code Operation Notation ADC A,@HL 00111110 C, A ← A + (HL) + .
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 20 Table 5-20. Bit Manipulation Instructions — Binary Code Summary Name Operand Binary Code Operation Notation BTST C 11010111 Skip if C = 1 DA.b 1 1 b1 b0 0 0 1 1 Skip if DA.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 21 Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Continued) Name Operand Binary Code Operation Notation BITR DA.b 1 1 b1 b0 0 0 0 0 DA.b ← 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 11111110 mema.
SAM47 INSTRUCTION SET KS57C2308/P2308/C2 316/P2316 5- 22 Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Concluded) Name Operand Binary Code Operation Notation LDB mema.b,C * 11111100 mema.b ← C memb.@L,C 11111100 memb.7–2 + [L.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 23 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction of the SAM47 instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-reference re sour ce for application programmers.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 24 ADC — Add With Carry ADC dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Add indirect data memory to A with carry 1 1 EA,RR A.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 25 ADC — Add With Carry ADC (Continued) Examples: 3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction immediately after the ADS. An ADS instruction immediately after the ADC does not skip even if an overflow occurs .
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 26 ADS — Add And Skip On Overflow ADS dst,src Operation: Operand Operation Summary Bytes Cycles A, # im Add 4-bit immediate data to A and skip o.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 27 ADS — Add And Skip On Overflow ADS (Continued) Examples: 2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and the carry flag = "0": ADS EA,HL ; EA ← 0C3H + 12H = 0D5H JPS XXX ; Jump to XXX; no skip after ADS.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 28 AND — Logical And AND dst,src Operation: Operand Operation Summary Bytes Cycles A,#im Logical-AND A immediate data to A 2 2 A,@HL Logical-AND.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 29 BAND — Bit Logical And BAND C,src.b Operation: Operand Operation Summary Bytes Cycles C,mema.b Logical-AND carry flag with memory bit 2 2 C,memb.@L 2 2 C,@H+DA.b 2 2 Description: The specified bit of the source is logically ANDed with the carry flag bit value.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 30 BAND — Bit Logical And BAND (Continued) Examples: 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 31 BITR — Bit Reset BITR dst.b Operation: Operand Operation Summary Bytes Cycles DA.b Clear specified memory bit to logic zero 2 2 mema.b 2 2 memb.@L 2 2 @ H+DA.b 2 2 Description: A BITR instruction clears to logic zero (resets) the specified bit within the destination operand.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 32 BITR — Bit Reset BITR (Continued) Examples: 3. For clearing P2.2, P2.3, and P3.0–P3.3 to "0": LD L,#0AH BP2 BITR P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 INCS L JR BP2 4.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 33 BITS — Bit Set BITS dst.b Operation: Operand Operation Summary Bytes Cycles DA.b Set specified memory bit 2 2 mema.b 2 2 memb.@L 2 2 @ H+DA.b 2 2 Description: This instruction sets the specified bit within the destination without affecting any other bits in the destination.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 34 BITS — Bit Set BITS (Continued) Examples: 3. For setting P2.2, P2.3, and P3.0–P3.3 to "1": LD L,#0AH BP2 BITS P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F 2H.2 INCS L JR BP2 4.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 35 BOR — Bit Logical OR BOR C,src.b Operation: Operand Operation Summary Bytes Cycles C,mema.b Logical-OR carry with specified memory bit 2 2 C,memb.@L 2 2 C,@H+DA.b 2 2 Description: The specified bit of the source is logically ORed with the carry flag bit value.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 36 BOR — Bit Logical OR BOR (Continued) Examples: 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 37 BTSF — Bit Test and Skip on False BTSF dst.b Operation: Operand Operation Summary Bytes Cycles DA.b Test specified memory bit and skip if bit equals "0" 2 2 + S mema.b 2 2 + S memb.@L 2 2 + S @ H+DA.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 38 BTSF — Bit Test and Skip on False BTSF (Continued) Examples: 3. P2.2, P2.3 and P3.0–P3.3 are tested: LD L,#0AH BP2 BTSF P1.@L ; First, P1.@0AH = P2.2 ; (111100B) + 10B.10B = 0F2H.2 RET INCS L JR BP2 4.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 39 BTST — Bit Test and Skip on True BTST dst.b Operation: Operand Operation Summary Bytes Cycles C Test carry bit and skip if set (= "1") 1 1 + S DA.b Test specified bit and skip if memory bit is set 2 2 + S mema.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 40 BTST — Bit Test and Skip on True BTST (Continued) Examples: 2. You can use BTST in the same way to test a port pin address bit: BTST P2.0 ; If P2.0 = "1", then skip RET ; If P2.0 = "0", then return JP LABEL3 3.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 41 BTSTZ — Bit Test and Skip on True; Clear Bit BTSTZ dst.b Operation: Operand Operation Summary Bytes Cycles mema.b Test specified bit; skip and clear if memory bit is set 2 2 + S memb.@L 2 2 + S @ H+DA.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 42 BTSTZ — Bit Test and Skip on True; Clear Bit BTSTZ (Continued) Examples: 3. Bank 0, location 0A0H.0, is tested and EMB = "0": FLAG EQU 0A0H.0 • • • BITR EMB • • • LD H,#0AH BTSTZ @H+FLAG ; If bank 0 (AH + 0H).
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 43 BXOR — Bit Exclusive OR BXOR C,src.b Operation: Operand Operation Summary Bytes Cycles C,mema.b Exclusive-OR carry with memory bit 2 2 C,memb.@L 2 2 C,@H+DA.b 2 2 Description: The specified bit of the source is logically XORed with the carry bit value.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 44 BXOR — Bit Exclusive OR BXOR (Continued) Examples: 3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 45 CALL — Call Procedure CALL dst Operation: Operand Operation Summary Bytes Cycles ADR14 Call direct in page (14-bits) 3 4 Description: CALL calls a subroutine located at the destination address.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 46 CALLS — Call Procedure (Short) CALLS dst Operation: Operand Operation Summary Bytes Cycles ADR11 Call direct in page (11-bits) 2 3 Description: The CALLS instruction unconditionally calls a subroutine located at the indicated address.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 47 CCF — Complement Carry Flag CCF Operation: Operand Operation Summary Bytes Cycles – Complement carry flag 1 1 Description: The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 48 COM — Complement Accumulator COM A Operation: Operand Operation Summary Bytes Cycles A Complement accumulator (A) 2 2 Description: The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice versa.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 49 CPSE — Compare and Skip if Equal CPSE dst,src Operation: Operand Operation Summary Bytes Cycles R,#im Compare and skip if register equals # i.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 50 DECS — Decrement and Skip on Borrow DECS dst Operation: Operand Operation Summary Bytes Cycles R Decrement register (R); skip on borrow 1 1 + S RR Decrement register pair (RR); skip on borrow 2 2 + S Description: The destination is decremented by one.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 51 DI — Disable Interrupts DI Operation: Operand Operation Summary Bytes Cycles – Disable all interrupts 2 2 Description: Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 52 EI — Enable Interrupts EI Operation: Operand Operation Summary Bytes Cycles – Enable all interrupts 2 2 Description: Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be serviced when they occur, assuming they are enabled.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 53 IDLE — Idle Operation IDLE Operation: Operand Operation Summary Bytes Cycles – Engage CPU idle mode 2 2 Description: IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (PCON).
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 54 INCS — Increment and Skip on Carry INCS dst Operation: Operand Operation Summary Bytes Cycles R Increment register (R); skip on carry 1 1 + S.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 55 IRET — Return From Interrupt IRET Operation: Operand Operation Summary Bytes Cycles – Return from interrupt 1 3 Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 56 JP — Jump JP dst Operation: Operand Operation Summary Bytes Cycles ADR14 Jump to direct address (14 bits) 3 3 Description: JP causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 57 JPS — Jump (Short) JPS dst Operation: Operand Operation Summary Bytes Cycles ADR12 Jump direct in page (12 bits) 2 2 Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 58 JR — Jump Relative (Very Short) JR dst Operation: Operand Operation Summary Bytes Cycles # im Branch to relative immediate address 1 2 @WX Br.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 59 JR — Jump Relative (Very Short) JR (Continued) Examples: 1. A short form for a relative jump to label “KK” is the instruction JR KK where “KK” must be within the allowed range of current PC–15 to current PC+16.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 60 LD — Load LD dst,src Operation: Operand Operation Summary Bytes Cycles A,#im Load 4-bit immediate data to A 1 1 A,@Rra Load indirect data mem.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 61 LD — Load LD (Continued) Description: Operand Binary Code Operation Notation RR,#imm 10000 r2 r1 1 RR ← imm d7 d6 d5 d4 d3 d2 d1 d0 DA,A 10.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 62 LD — Load LD (Continued) Examples: 2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two times in succession, only the first LD is executed; the next instructions are treated as NOPs.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 63 LD — Load LD (Concluded) Examples: Instruction Operation Description and Guidelines LD EA,@HL Load data memory contents pointed to by 8-bit register HL to the A register, and the contents of HL+1 to the E register.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 64 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: Operand Operation Summary Bytes Cycles mema.b,C Load carry bit to a specified memory bit 2 2 memb.@L,C Load carry bit to a specified indirect memory bit 2 2 @ H+DA.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 65 LDB — Load Bit LDB (Continued) Examples: 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB C,P1.0 2.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 66 LDC — Load Code Byte LDC dst,src Operation: Operand Operation Summary Bytes Cycles EA,@WX Load code byte from WX to EA 1 3 EA,@EA Load code byte from EA to EA 1 3 Description: This instruction is used to load a byte from program memory into an extended accumulator.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 67 LDC — Load Code Byte LDC (Continued) Examples: 2. The following instructions will load one of four values defined by the define byte ( DB) di.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 68 LDD — Load Data Memory and Decrement LDD dst Operation: Operand Operation Summary Bytes Cycles A,@HL Load indirect data memory contents to A;.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 69 LDI — Load Data Memory and Increment LDI dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Load indirect data memory to A; incr.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 70 NOP — No Operation NOP Operation: Operand Operation Summary Bytes Cycles – No operation 1 1 Description: No operation is performed by a NOP instruction. It is typically used for timing delays.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 71 OR — Logical OR OR dst,src Operation: Operand Operation Summary Bytes Cycles A, # im Logical-OR immediate data to A 2 2 A, @HL Logical-OR ind.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 72 POP — Pop From Stack POP dst Operation: Operand Operation Summary Bytes Cycles RR Pop to register pair from stack 1 1 SB Pop SMB and SRB values from stack 2 2 Description: The contents of the RAM location addressed by the stack pointer is read, and the SP is incremented by two.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 73 PUSH — Push Onto Stack PUSH src Operation: Operand Operation Summary Bytes Cycles RR Push register pair onto stack 1 1 SB Push SMB and SRB va.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 74 RCF — Reset Carry Flag RCF Operation: Operand Operation Summary Bytes Cycles – Reset carry flag to logic zero 1 1 Description: The carry flag is cleared to logic zero, regardless of its previous value.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 75 REF — Reference Instruction REF dst Operation: Operand Operation Summary Bytes Cycles memc Reference code 1 1 (note) NOTE : The instruction referenced by REF determines the instruction cycles.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 76 REF — Reference Instruction REF (Continued) Examples: 1. Instructions can be executed efficiently using REF, as shown in the following exampl.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 77 REF — Reference Instruction REF (Concluded) Examples: 3. In this example the binary code of “REF A1” at locations 20H–21H is 20H, for .
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 78 RET — Return From Subroutine RET Operation: Operand Operation Summary Bytes Cycles – Return from subroutine 1 3 Description: RET pops the PC values successively from the stack, incrementing the stack pointer by six.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 79 RRC — Rotate Accumulator Right Through Carry RRC A Operation: Operand Operation Summary Bytes Cycles A Rotate right through carry bit 1 1 Description: The four bits in the accumulator and the carry flag are together rotated one bit to the right.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 80 SBC — Subtract With Carry SBC dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Subtract indirect data memory from A with carry.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 81 SBC — Subtract With Carry SBC (Continued) Examples: 3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on “no borrow” to the instruction immediately after the ADS.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 82 SBS — Subtract SBS dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Subtract indirect data memory from A; skip on borrow 1 1 +.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 83 SCF — Set Carry Flag SCF Operation: Operand Operation Summary Bytes Cycles – Set carry flag to logic one 1 1 Description: The SCF instruction sets the carry flag to logic one, regardless of its previous value.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 84 SMB — Select Memory Bank SMB n Operation: Operand Operation Summary Bytes Cycles n Select memory bank 2 2 Description: The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 85 SRB — Select Register Bank SRB n Operation: Operand Operation Summary Bytes Cycles n Select register bank 2 2 Description: The SRB instruction selects one of four register banks in the working register memory area.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 86 SRET — Return From Subroutine and Skip SRET Operation: Operand Operation Summary Bytes Cycles – Return from subroutine and skip 1 3 + S Des.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 87 STOP — Stop Operation STOP Operation: Operand Operation Summary Bytes Cycles – Engage CPU stop mode 2 2 Description: The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON) to logic one.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 88 VENT — Load EMB, ERB, and Vector Address VENTn dst Operation: Operand Operation Summary Bytes Cycles EMB (0,1) ERB (0,1) ADR Load enable memory bank flag (EMB) and the enable register bank flag (ERB) and program counter to vector address, then branch to the corresponding location.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 89 VENT — Load EMB, ERB, and Vector Address VENTn (Continued) Example: The instruction sequence ORG 0000H VENT0 1,0,RESET VENT1 0,1,INTA VENT2 0.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 90 XCH — Exchange A or EA with Nibble or Byte XCH dst,src Operation: Operand Operation Summary Bytes Cycles A,DA Exchange A and data memory cont.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 91 XCHD — Exchange and Decrement XCHD dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Exchange A and data memory contents; decre.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 92 XCHI — Exchange and Increment XCHI dst,src Operation: Operand Operation Summary Bytes Cycles A,@HL Exchange A and data memory contents; incre.
KS57C2308/P2308/C2316/P2316 SAM47 INSTRU CTION SET 5- 93 XOR — Logical Exclusive OR XOR dst,src Operation: Operand Operation Summary Bytes Cycles A,#im Exclusive-OR immediate data to A 2 2 A,@HL Exc.
SAM47 INSTRUCTION SET KS57C2308/P2308 /C2316/P2316 5- 94 NOTES.
Oscillator Circuits Interrupts Power-Down RESET I/O Ports Timers and Timer/Counter s LCD Controller/Driver Electrical Data Mechanical Data KS57P2308/P2316 OTP.
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KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 1 6 OSCILLATOR CIRCUITS OVERVIEW The KS57C2308/C2316 microcontroller has two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 2 Clock Control Registers When the system clock mode control register, SCMOD , a nd the power control register, PCON , are both cleared to zero after RESET , the normal CPU operating mode is enabled, a main system clock of fx/64 is selected, and main system clock oscillation is initiated.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 3 XT IN XT OUT Oscillator Stop CPU clock Wait release signal Internal RESET signal Power down release PCON.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 4 MAIN SYSTEM OSCILLATOR CIRCUITS X IN X OUT Figure 6- 2. Crystal/Ceramic Oscillator X IN X OUT Figure 6- 3. External Oscillator X IN X OUT R Figure 6- 4. RC Oscillator SUBSYSTEM OSCILLATOR CIRCUITS XT IN XT OUT 32.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 5 POWER CONTROL REGISTER (PCON) The power control register ( PCON ) is a 4-bit register that is used to select the CPU clock frequency and to con trol CPU operating and power-down modes.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 6 + + PROGRAMMING TIP — Setting the CPU Clock To set the CPU clock to 0.95 µs at 4.19 MHz: BITS EMB SMB 15 LD A,#3H LD PCON,A INSTRUCTION CYC.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 7 SYSTEM CLOCK MODE REGISTER (SCMOD) The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control main and sub- system clock oscillation. SCMOD is mapped to the RAM address FB7H.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 8 Table 6-4 . Main/Sub Oscillation Stop Mode Mode Condition Method to issue Osc Stop Osc Stop Release Source (2) Main Oscillation STOP Mode Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 9 Table 6-5 . System Operating Mode Comparison Mode Condition STOP/IDLE Mode Start Method Current Consumption Main operating mode Main oscillator runs. Sub oscillator runs (stops). System clock is the main oscillation clock.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 10 SWITCHING THE CPU CLOCK Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD, de termine whether a main system or a subsystem clock is selected as the CPU clock, and also how this frequency is to be divided.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 11 Table 6-6 . Elapsed Machine Cycles During CPU Clock Switch AFTER SCMOD.0 = 0 SCMOD.0 = 1 BEFORE PCON.1 = 0 PCON.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1 PCON.1 = 0 N/A 1 MACHINE CYCLE 1 MACHINE CYCLE PCON.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 12 CLOCK OUTPUT MODE REGISTER (CLMOD) The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the CLO pin and to select the CPU clock source and frequency.
KS57C2308/P2308/C2316 / P 2316 OSCILLATOR CIRCUITS 6 - 13 CLOCK OUTPUT CIRCUIT The clock output circuit, used to output clock pulses to the CLO pin, has the following components: — 4-bit clock output mode register (CLMOD) — Clock selector — Port mode flag — CLO output pin (P2.
OSCILLATOR CIRCUITS KS57C2308/P2308/C23 16 / P 2316 6 - 14 + + PROGRAMMING TIP — CPU Clock Output to the CLO Pin To output the CPU clock to the CLO pin: BITS EMB SMB 15 LD EA,#0 4 H LD PMG 2 ,EA ; P 2 ← Output mode BITR P 2.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 1 7 INTERRUPTS OVERVIEW The KS57C2308/C2316 interrupt control circuit has five functional components: — Interrupt enable flags ( IEx) — Interrupt request.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 2 Vectored Interrupts Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 3 Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ instruction IEx = 1 ? Interrupt is generated.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 4 # @ @ IRQB IRQ4 IRQ0 IRQ1 IRQS IRQT0 IRQW IRQ2 IMOD1 IMOD0 INTB INT4 INT0 INT1 INTS INTT0 INTW Power-Down Mode Release Signal IME IPR IS1 IS0 Interrupt Co.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 5 MULTIPLE INTERRUPTS The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, w here either all inter rupt requests or.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 6 Multi-Level Interrupt Handling With multi-level interrupt handling, a lower-priority interrupt request can be executed by manipulating the interrupt status flags, IS0 and IS1 while a high-priority inter rupt is being serviced (see Table 7- 2).
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 7 INTERRUPT PRIORITY REGISTER (IPR) The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI instruction.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 8 + + PROGRAMMING TIP — Setting the INT Interrupt Priority The following instruction sequence sets the INT1 interrupt to high priority: BITS EMB SMB 15 DI ; IPR.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 9 EXTERNAL INTERRUPT 0 and INTERRUPT 1 MODE REGISTERS (C ontinued ) When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 ma chine cycles have elapsed.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 10 EXTERNAL INTERRUPT 2 MODE REGISTER (IMOD2 ) T he mode register for external interrupt 2 at the K S 0– KS7 pins, IMOD2 , is addressable only by 4-bit write instructions. RESET clears all IMOD2 bits to logic zero.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 11 INT2 KS7 KS6 KS5 KS4 KS3 KS2 KS1 KS0 IRQ2 FALLING EDGE DETECTION CIRCUIT CLOCK SELECTOR RISING EDGE DETECTION CIRCUIT IMOD2 Figure 7 -6 .
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 12 INTERRUPT FLAGS There are three types of interrupt flags: interrupt request and interrupt enable f lags that correspond to each in terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.
KS57C2308/P2308/C2316/P2316 INTERRUPTS 7 - 13 Interrupt Request Flags (IRQx) Interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.
INTERRUPTS KS57C2308/P2308/C23 16/P2316 7 - 14 + + PROGRAMMING TIP — Enabling the INTB and INT4 Interrupts To simultaneously enable INTB and INT4 interrupts: INTB DI BTSTZ IRQB ; IRQB = 1 ? JP I NT4.
KS57C2308/P2308/C2316/P2316 POWER-DOWN 8 - 1 8 POWER-DOWN OVERVIEW The KS57C2308/C2316 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP.
POWER-DOWN KS57C2308/P2308/C2316/P2316 8 - 2 Table 8- 1. Hardware Operation During Power-Down Modes Mode Main Stop Sub Stop Main/Sub Stop Idle System clock Main clock ( fx) Sub clock ( fxt) Main clock ( fx) (1) Main ( fx) or sub clock ( fxt) Instruction STOP Setting SCMOD.
KS57C2308/P2308/C2316/P2316 POWER-DOWN 8 - 3 IDLE MODE TIMING DIAGRAMS CLOCK SIGNAL IDLE INSTRUCTION OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz) NORMAL MODE IDLE MODE NORMAL MODE NORMAL OSCILLATION RESET Figure 8- 1.
POWER-DOWN KS57C2308/P2308/C2316/P2316 8 - 4 STOP MODE TIMING DIAGRAMS STOP INSTRUCTION OSCILLATION STABILIZATION (31.3 ms / 4.19 MHz) RESET CLOCK SIGNAL NORMAL MODE IDLE MODE NORMAL MODE OSCILLATION RESUMES STOP MODE OSCILLATION STOPS Figure 8- 3.
KS57C2308/P2308/C2316/P2316 POWER-DOWN 8 - 5 + + PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption.
POWER-DOWN KS57C2308/P2308/C2316/P2316 8 - 6 PORT PIN CONFIGURATION FOR POWER-DOWN The following method describes how to configure I/O port pins to reduce power consumption during power-down modes (stop, idle): Condition 1: If the microcontroller is not configured to an external device: 1.
KS57C2308/P2308/C2316/P2316 POWER-DOWN 8 - 7 RECOMMENDED CONNECTIONS FOR UNUSED PINS To reduce overall power consumption, please configure unused pins according to the guidelines described in Table 8-2 . Table 8-2 . Unused Pin Connections for Reduc ing Power Consumption Pin/Share Pin Names Recommended Connection P0.
POWER-DOWN KS57C2308/P2308/C2316/P2316 8 - 8 NOTES.
KS57C2308/P2308/C2316/P2316 RESET 9 - 1 9 RESET OVERVIEW When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.
RESET KS57C2308/P2308/C23 16/P2316 9 - 2 HARDWARE REGISTER VALUES AFTER RESET Table 9 - 1 gives you detailed information about hardware register values after a RESET occurs during power-down mode or during normal operation.
KS57C2308/P2308/C2316/P2316 RESET 9 - 3 Table 9 - 1. Hardware Register Values After RESET (Continued) Hardware Component or Subcomponent If RESET Occurs During Power-Down Mode If RESET Occurs During N.
RESET KS57C2308/P2308/C23 16/P2316 9 - 4 NOTES.
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 1 10 I/O PORTS OVERVIEW The KS57C2308/C2316 h as 9 ports. There are total of 8 input pins, 8 output pin and 24 configurable I/O pins, for a maximum number of 40 pins. Pin addresses for all ports are mapped to bank 15 of the RAM.
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 2 Table 10- 1. I/O Port Overview Port I/O Pins Pin Names Address Function Description 0 I 4 P0.0 – P0.3 FF0H 4-bit input port. 1-bit and 4-bit read and test are possible. P0.1 and P0.2 are software configurable as input or output for SCK and SO by SMOD register.
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 3 PORT MODE FLAGS (PM FLAGS) Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the corresponding I/O buffer. For convenient program reference, PM flags are organized into two groups — PMG1 and PMG2 as shown in Table 10- 3.
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 4 + + PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors P2 and P3 are enabled to be pull-up resistors.
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 5 Table 10-6. Port 8 Pin Addresses and LCD Segment Correspondence Port 8 Pin Number RAM Address LCD Segment P8.0 1F8H SEG24 P8.1 1F9H SEG25 P8.2 1FAH SEG26 P8.3 1FBH SEG27 P8.4 1FCH SEG28 P8.5 1FDH SEG29 P8.6 1FEH SEG30 P8.
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 6 PORT 0 CIRCUIT DIAGRAM SCK SCK SO SI SMOD V DD When and SO act as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 7 PORT 1 CIRCUIT DIAGRAM V DD PUMOD.1 INT0 P1.1 P1.2 P1.3 P1.0 N/R Circuit INT1 INT2 TCL0 INT0 CPU clock fxx/64 INT1 Edge Detection IRQ0 IMOD0 IMOD1 Clock Selector P1.1 P1.0 Edge Detection IRQ1 Noise Filter IMOD0 Figure 10- 2.
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 8 PORT 2 CIRCUIT DIAGRAM 8 1, 4 1, 4 M U X P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ PM2 Output Latch When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 9 PORT 3 AND 6 CIRCUIT DIAGRAM V DD 1, 4, 8 1, 4, 8 x = port number (3, 6) When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 10 PORT 4 AND 5 CIRCUIT DIAGRAM V DD 1, 4, 8 1, 4, 8 M U X Px.0 Px.1 Px.2 Px.3 Output Latch CMOS Push-Pull or N-Channel Open-Deain When a port pin acts as a.
KS57C2308/P2308/C2316/P2316 I/O PORTS 10 - 11 PORT 7 CIRCUIT DIAGRAM 8 1, 4 1, 4 P7.0 P7.1 P7.2 P7.3 When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).
I/O PORTS KS57C2308/P2308/C23 16/P2316 10 - 12 NOTES.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 1 11 TIMERS and TIMER/COUNTERS OVERVIEW The KS57C2308/C2316 microcontroller has three timer and timer/counter modules: — 8-bit basic timer (BT) — 8-bit timer/counter (TC0) — Watch timer (WT) The 8-bit basic timer (BT) is the microcontroller's main interval timer.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 2 BASIC TIMER (BT) OVERVIEW The 8-bit basic timer (BT) has five functional components: — Clock selector logic — 4-bit mode register (BMOD.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 3 Table 11- 1. Basic Timer Register Overview Register Name Type Description Size RAM Address Addressing Mode Reset Value BMOD Control Control.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 4 BASIC TIMER MODE REGISTER (BMOD) The basic timer mode register, BMOD, is a 4-bit write-only register.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 5 BASIC TIMER COUNTER (BCNT) BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. RESET leaves the BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register control bit (BMOD.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 6 + + PROGRAMMING TIP — Using the Basic Timer 1. To read the basic timer count register (BCNT): BITS EMB SMB 15 BCNTR LD EA,BCNT LD YZ,EA LD EA,BCNT CPSE EA,YZ JR BCNTR 2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 7 WATCHDOG TIMER MODE REGISTER (WDMOD) The watchdog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H–F99H. WDMOD register controls to enable or disable the watchdog function.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 8 + + PROGRAMMING TIP — Using the Watchdog Timer RESET DI BITS EMB SMB 15 LD EA,#00H LD SP,EA • • • LD A,#0DH ; WDCNT input clock is 7.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 9 8-BIT TIMER/COUNTER 0 (TC0) OVERVIEW Timer/counter 0 (TC0) is used to count system “ events ” by identifying the transition (high-to-low or low-to-high) of incoming square wave signals.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 10 TC0 COMPONENT SUMMARY Mode register (TMOD0) Activates the timer/counter and selects the internal clock frequency or the external clock source at the TCL0 pin. Reference register (TREF0) Stores the reference value for the desired nu mber of clock pulses between in terrupt requests.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 11 Table 11-4 . TC0 Register Overview Register Name Type Description Size RAM Address Addressing Mode Reset Value TMOD0 Control Controls TC0 .
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 12 TC0 ENABLE/DISABLE PROCEDURE Enable Timer/Counter 0 — Set TMOD0.2 to logic one — Set the TC0 interrupt enable flag IET0 to logic one — Set TMOD0.3 to logic one TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 13 TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select the clock frequency.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 14 TC0 EVENT COUNTER FUNCTION Timer/counter 0 can monitor or detect system “ events ” by using the external clock input at the TCL0 pin as the counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 15 TC0 CLOCK FREQUENCY OUTPUT Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select the clock frequency, load the appropriate values to the TC0 mode register, TMOD0.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 16 TC0 SERIAL I/O CLOCK GENERATION Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD).
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 17 TC0 MODE REGISTER (TMOD0) TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 18 Table 11-7 . TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings TMOD0.6 TMOD0.5 TMOD0.4 Resulting Counter Source and Clock Frequency 000 External clock input (TCL0) on rising edges 001 External clock input (TCL0) on falling edges 100 fxx/2 10 (4.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 19 TC0 COUNTER REGISTER (TCNT0) The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero (00H).
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 20 TC0 REFERENCE REGISTER (TREF0) The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to “ FFH ” .
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 21 + + PROGRAMMING TIP — Setting a TC0 Timer Interval To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps. 1. Select the timer/counter 0 mode register with a maximum setup time of 62.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 22 WATCH TIMER OVERVIEW The watch timer is a multi-purpose timer which consists of three basic components: — 8-bit watch timer mode registe.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 23 Buzzer Output Frequency Generator The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To s elect the desired BUZ frequency , load the appropriate value to the WMOD register.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 24 8 Selector Circuit IRQW fxt fxx/128 fw (32.768 kHz) MUX fw/2 (256 Hz) 7 fw/2 (2Hz) 14 Enable/ Disable Clock Selector fx = Main System Clock (4.19 MHz) fxt = Subsystem Clock (32.768 kHz) fw = Watch Timer Frequency fxx = System Clock BUZ WMOD.
KS57C2308/P2308/C2316/P2316 TIMERS and TIMER/COUNTERS 11 - 25 WATCH TIMER MODE REGISTER (WMOD) The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only addressable. An exception is WMOD bit 3 (the XT IN input level control bit) which is 1-bit read-only addressable.
TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11 - 26 + + PROGRAMMING TIP — Using the Watch Timer 1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable: BITS EMB SMB 15 LD EA,#04 H LD PMG 2 ,EA ; P 2 .
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 1 12 LCD CONTROLLER/DRIVER OVERVIEW The KS57C2308/C2316 microcontroller can directly drive an up-to- 128- dot ( 32 segments x 4 commons) LCD panel.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 2 LCD CIRCUIT DIAGRAM SEG31/P8.7 4 4 TIMING CONTROLLER 1E0H.0 1E0H.1 1E0H.2 1E0H.3 1F4H.0 1F4H.1 1F4H.2 1F4H.3 1FFH.0 1FFH.1 1FFH.2 1FFH.3 4 4 LMOD 8 COM3 COM2 COM1 COM0 COM CONTROL VLC0 VLC1 VLC2 LCDSY LCDCK SEG30/P8.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 3 LCD RAM ADDRESS AREA RAM addresses of bank 1 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 4 LCD CONTROL REGISTER (LCON) The LCD control register (LCON) is used to turn the LCD display on and off, to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD display expansion, and to control the flow of current to dividing resistors in the LCD circuit.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 5 LCD MODE REGISTER (LMOD) The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and display on/off. LMOD can be manipulated using 8-bit write inst ructions, bit 3 (LMOD.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 6 Table 12-5 . LCD Clock Signal (LCDCK) , Frame Frequency and LCD sync Signal (LCDSY) LCDCK f requency Static 1/2 Duty 1/3 Duty 1/4 Duty fw/2 9 .
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 7 BIAS PIN LCON.0 V SS 2R R R R V LCD = 3 V Static and 1/3 Bias V LC0 V LC1 V LC2 V DD Voltage Dividing Resistor Adjustment LCON.0 V SS 2R R R R 2R’ R’ R’ R’ BIAS PIN V LC0 V LC1 V LC2 V DD LCON.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 8 COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 9 V LCD T f = 2 x T COM0, 1 (1/2 DUTY) V LC0 V LC1, 2 V SS V LCD T f = 3 x T COM0, 1 (1/3 DUTY) V LC0 V LC1, 2 V SS T: LCDCK T f : Frame frequency Figure 12-6 .
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 10 T: LCDCK T f : Frame frequency V LCD T f = 4 x T COM0-3 (1/4 DUTY) V LC0 V LC1 V SS V LC2 V LCD T f = 3 x T COM0-2 (1/3 DUTY) V LC0 V LC1 V SS V LC2 Figure 12-7 .
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 11 SEGMENT (SEG) SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at 1E0H–1FFH . Bits 0–3 of the display RAM are synchronized with the common signal output pins COM0, COM1, COM2, and COM3 .
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 12 Table 12-8. Select/No-Select Signals for LCD 1/2 Bias Display Mode SEG Select Non-select COM V LC0 /V SS V SS /V LC0 Select V SS /V LC0 –V .
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 13 Table 12-9. Select/No-Select Signals for LCD 1/3 Bias Display Mode SEG Select Non-select COM V LC0 /V SS V SS /V LC0 Select V SS /V LC0 –V .
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 14 +V LCD – V LCD 0 V SEG12 V LC0 V SS SEG11 V LC0 V SS COM0 V LC0 V SS COM0– SEG11 COM0– SEG12 +V LCD – V LCD 0 V T f Figure 12-11 .
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 15 SEG16 COM3 COM2 COM1 COM0 Timing Strobe Bit 0 Open Possible SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG15 S.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 16 + V LCD – V LCD V LC0 V SS V LC1, 2 V LC0 V SS V LC1, 2 V LC0 V SS V LC1, 2 + 1/2 V LCD – 1/2 V LCD 0 – V LCD + 1/2 V LCD – 1/2 V LCD 0 + V LCD COM1 SEG9 COM0– SEG9 COM1– SEG9 COM0 T f Figure 12-13.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 17 SEG30 SEG31 COM3 COM2 COM1 COM0 Timing Strobe SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 18 V LC0 V SS V LC1, 2 COM0 T f V LC0 V SS V LC1, 2 COM1 V LC0 V SS V LC1, 2 COM2 V LC0 V SS V LC1, 2 SEG12 + V LCD – V LCD + 1/2 V LCD – 1/.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 19 SEG30 SEG31 COM3 COM2 COM1 COM0 Timing Strobe Open SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG1.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 20 T f + 1/3 V LCD + V LCD COM2– SEG12 – 1/3 V LCD 0 – V LCD + 1/3 V LCD + V LCD COM1– SEG12 – 1/3 V LCD 0 – V LCD LCD + 1/3 V LCD +.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 21 SEG30 SEG31 COM3 COM2 COM1 COM0 Timing Strobe Open SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG1.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 22 COM0 V V LC0 SS V LC2 V LC1 COM1 V V LC0 SS V LC2 V LC1 COM2 V V LC0 SS V LC2 V LC1 COM3 V V LC0 SS V LC2 V LC1 SEG13 V V LC0 SS V LC2 V LC1 COM0– SEG13 + 1/3 V LCD – V LCD + V LCD – 1/3 V LCD 0 COM1– SEG13 + 1/3 V LCD – V LCD + V LCD – 1/3 V LCD 0 T f Figure 12-19.
KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIV ER 12 - 23 COM3 COM2 COM1 COM0 Timing Strobe 1E8H 1E9H 1EAH 1EBH 1ECH 1EDH 1EEH 1EFH 1F0H 1F1H 1F2H 1F3H 1F4H 1F5H 1F6H 1F7H 1F8H 1F9H 1FAH 1FBH 1FCH 1F.
LCD CONTROLLER/DRIVER KS57C2308/P2308/C23 16/P2316 12 - 24 NOTES.
KS57C2308/P2308/C2316/P2316 SERIAL I/O INTERFACE 13- 1 13 SERIAL I/O INTERFACE OVERVIEW The serial I/O interface (SIO) has the following functional components: — 8-bit mode register (SMOD) — Clock.
SERIAL I/O INTERFACE KS57C2308/P2308/C23 16/P2316 1 3- 2 * Instruction Execution fxx: System Clock INTERNAL BUS LSB or MSB first SBUF (8-BIT) SI CLOCK SELECTOR R Q D TOL0 CPU CLK fxx/2 fxx/2 R S Q SO SMOD.7 SMOD.6 SMOD.5 SMOD.3 SMOD.2 SMOD.1 SMOD.0 Q0 Q1 Q2 3-BIT COUNTER CLEAR OVERFLOW IRQS CK 8 INTERNAL BUS BITS * 8 - P0.
KS57C2308/P2308/C2316/P2316 SERIAL I/O INTERFACE 13- 3 SERIAL I/O MODE REGISTER (SMOD) The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface. Its reset value is logical zero. SMOD is organized in two 4-bit registers, as follows: FE0H SMOD.
SERIAL I/O INTERFACE KS57C2308/P2308/C23 16/P2316 1 3- 4 SERIAL I/O TIMING DIAGRAMS SCK SI SO IRQS DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 TRANSMIT COMPLETE SET SMOD.3 Figure 13- 2. SIO Timing in Transmit/Receive Mode SCK SI SO IRQS DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 TRANSMIT COMPLETE SET SMOD.
KS57C2308/P2308/C2316/P2316 SERIAL I/O INTERFACE 13- 5 SERIAL I/O BUFFER REGISTER (SBUF) The serial I/O buffer register , SBUF, can be read or written using 8-bit RAM control instructions. Following a RESET , the value of SBUF is undetermined. When the serial interface operates in transmit-and-receive mode (SMOD.
SERIAL I/O INTERFACE KS57C2308/P2308/C23 16/P2316 1 3- 6 + + PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued) 3. Transmit and recei ve Data through SIO interface using an internal clock frequency of 4.
KS57C2308/P2308/C2316/P2316 SERIAL I/O INTERFACE 13- 7 + + PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued) 4. Transmit and receive Data through SIO interface using an ext.
SERIAL I/O INTERFACE KS57C2308/P2308/C23 16/P2316 1 3- 8 NOTES.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 1 14 ELECTRICAL DATA OVERVIEW In this section, information on KS57C2308/C2316 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 2 Table 14- 1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Units Supply Voltage V DD – – 0.3 to + 6.5 V Input Voltage V I1 All I/O ports – 0.3 to V DD + 0.3 Output Voltage V O – – 0.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 3 Table 14- 2. D.C. Electrical Characteristics (Continued) (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units Output l ow v oltage V OL1 V DD = 4.5 V to 5.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 4 Table 14- 2. D.C. Electrical Characteristics (Concluded) (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5 . 5 V) Parameter Symbol Conditions Min Typ Max Units VLC0 Output voltage V LC0 T A = 25 ø C 0.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 5 Table 14- 3. Main System Clock Oscillator Characteristics (T A = – 40 ° C + 85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Ceramic Oscillator X IN X OUT C1 C2 Oscillation frequency (1) – 0.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 6 Table 14- 4. Subsystem Clock Oscillator Characteristics (T A = – 40 ° C + 85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal Oscillator XT IN XT OUT C1 C2 Oscillation frequency (1) – 32 32.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 7 Table 14-6 . A.C. Electrical Characteristics (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5 . 5 V) Parameter Symbol Conditions Min Typ Max Units Instruction c ycle t CY V DD = 2.7 V to 5.5 V 0.67 – 64 µs t ime (1 ) V DD = 1.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 8 CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) 1 Supply Voltage (V) 250 kHz 500 kHz 750 kHz 1.00 MHz 1.0475 MHz 15.6 kHz CPU Clock 1.5 MHz 3 4 5 6 7 1.8 Main OSC. Frequency 6 MHz 4.19 MHz 3 MHz Figure 14- 1.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 9 TIMING WAVEFORMS t WAIT V DD RESET EXECUTION OF STOP INSTRUCTION V DDDR DATA RETENTION MODE STOP MODE INTERNAL RESET IDLE MODE OPERATING MODE t SREL Figure 14- 2.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 10 0.8 V DD 0.2 V DD 0.8 V DD 0.2 V DD MEASUREMENT POINTS Figure 14- 4. A.C. Timing Measurement Points (Except for X IN and XT IN ) X in t XL t XH x V DD – 0.1 V 0.1 V 1/f Figure 14- 5. Clock Timing Measurement at X IN XT in t XTL t XTH 1/f V DD – 0.
KS57C2308/P2308/C2316/P2316 ELECTRICAL DATA 14- 11 TCL0 t TIL0 t TIH0 1/f 0.2 V DD TI0 0.8 V DD Figure 14- 7. TCL 0 Timing RESET t RSL 0.2 V DD Figure 14- 8. Input Timing for RESET Signal INT0, 1, 2, 4 KS0 to KS7 t INTL t INTH 0.8 V DD 0.2 V DD Figure 14- 9.
ELECTRICAL DATA KS57C2308/P2308/C23 16/P2316 14- 12 SCK t KL t KH t KCY 0.8 V DD INPUT DATA OUTPUT DATA 0.2 V DD 0.8 V DD 0.2 V DD SI SO t KSO t SIK t KSI Figure 14- 10.
KS57C2308/P2308/C2316/P2316 MECHANICAL DATA 15- 1 15 MECHANICAL DATA This section contains the following information about the device package: — Package dimensions in millimeters — Pad diagram — Pad/pin coordinate data table NOTE : Dimensions are in millimeters.
MECHANICAL DATA KS57C2308/P2308/C23 16/P2316 15- 2 NOTES.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 1 16 KS57P2308/P2316 OTP OVERVIEW The KS57P2308/P2316 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS57C2308/C2316 microcontroller. It has an on-chip EPROM instead of masked ROM.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 2 SEG19 SEG20 SEG21 SEG22 SEG23 P8.0/SEG24 P8.1/SEG25 P8.2/SEG26 P8.3/SEG27 P8.4/SEG28 P8.5/SEG29 P8.6/SEG30 P8.7/SEG31 P 7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 3 Table 16-1. Pin Descriptions Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function V LC1 SDAT 10 I/O Serial data pin. Output port when reading and input port when writing can be assigned as Input/push-pull output port respectively.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 4 Table 16-4 . Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Units Supply Voltage V DD – – 0.3 to + 6.5 V Input Voltage V I1 All I/O ports – 0.3 to V DD + 0.3 Output Voltage V O – – 0.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 5 Table 16-5 . D.C. Electrical Characteristics (Continued) (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units Output l ow v oltage V OL1 V DD = 4.5 V to 5.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 6 Table 16-5 . D.C. Electrical Characteristics (Concluded) (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5 . 5 V) Parameter Symbol Conditions Min Typ Max Units VLC0 Output voltage V LC0 T A = 25 ø C 0.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 7 Table 16-6 . Main System Clock Oscillator Characteristics (T A = – 40 ° C + 85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Ceramic Oscillator X IN X OUT C1 C2 Oscillation frequency (1) – 0.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 8 Table 16-7 . Subsystem Clock Oscillator Characteristics (T A = – 40 ° C + 85 ° C, V DD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal Oscillator XT IN XT OUT C1 C2 Oscillation frequency (1) – 32 32.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 9 Table 16-9 . A.C. Electrical Characteristics (T A = – 40 ° C to + 85 ° C, V DD = 1.8 V to 5 . 5 V) Parameter Symbol Conditions Min Typ Max Units Instruction c ycle t CY V DD = 2.7 V to 5.5 V 0.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 10 CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64) 1 Supply Voltage (V) 250 kHz 500 kHz 750 kHz 1.00 MHz 1.0475 MHz 15.6 kHz CPU Clock 1.5 MHz 3 4 5 6 7 1.8 Main OSC. Frequency 6 MHz 4.19 MHz 3 MHz Figure 16-2 .
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 11 TIMING WAVEFORMS t WAIT V DD RESET EXECUTION OF STOP INSTRUCTION V DDDR DATA RETENTION MODE STOP MODE INTERNAL RESET IDLE MODE OPERATING MODE t SREL Figure 16-3 .
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 12 0.8 V DD 0.2 V DD 0.8 V DD 0.2 V DD MEASUREMENT POINTS Figure 16-5 . A.C. Timing Measurement Points (Except for X IN and XT IN ) X in t XL t XH x V DD – 0.1 V 0.1 V 1/f Figure 16-6 . Clock Timing Measurement at X IN XT in t XTL t XTH 1/f V DD – 0.
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 13 TCL0 t TIL0 t TIH0 1/f 0.2 V DD TI0 0.8 V DD Figure 16-8 . TCL 0 Timing RESET t RSL 0.2 V DD Figure 16-9 . Input Timing for RESET Signal INT0, 1, 2, 4 KS0 to KS7 t INTL t INTH 0.8 V DD 0.2 V DD Figure 16-10 .
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 14 SCK t KL t KH t KCY 0.8 V DD INPUT DATA OUTPUT DATA 0.2 V DD 0.8 V DD 0.2 V DD SI SO t KSO t SIK t KSI Figure 16-11 .
KS57C2308/P2308/C2316/P2316 KS57P2308/P 2316 OTP 16- 15 START Address= First Location V DD =5V, V PP =12.5V x = 0 Program One 1ms Pulse Increment X x = 10 Verify 1 Byte Last Address V DD = V PP = 5 V Compare All Byte Device Passed Increment Address Verify Byte Device Failed PASS FAIL NO FAIL YES FAIL NO Figure 16-12.
KS57P2308/P2316 OTP KS57C2308/P2308/C23 16/P2316 16- 16 NOTES.
KS57C2308/P2308/C2316/P2316 DEVELOPMENT TOOLS 17- 1 17 Development Tools OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software.
DEVELOPMENT TOOLS KS57C2308/P2308/C2 316/P2316 17- 2 RAM BREAK/ DISPLAY UNIT TARGET APPLICATION SYSTEM PROBE ADAPTER TB572308A/16A TARGET BOARD PROM/MTP WRITER UNIT TRACE/TIMER UNIT SAM4 BASE UNIT POWER SUPPLY UNIT POD RS-232C IBM-PC AT or Compatible BUS SMDS2+ EVA CHIP Figure 17-1 .
KS57C2308/P2308/C2316/P2316 DEVELOPMENT TOOLS 17- 3 TB572308A/16A TARGET BOARD The TB572308A/16A target board is used for the KS57C2308/P2308/C2316/P2316 microcontroller.
DEVELOPMENT TOOLS KS57C2308/P2308/C2 316/P2316 17- 4 Table 17-1. Power Selection Settings for TB572308A/16A “ To User_Vcc ” Settings Operating Mode Comments To User_Vcc ON OFF SMDS2/SMDS2+ TB570502A /0504A TARGET SYSTEM V CC V SS V CC The SMDS2 /SMDS2+ supplies V CC to the target board (evaluation chip) and the target system.
KS57C2308/P2308/C2316/P2316 DEVELOPMENT TOOLS 17- 5 Table 17-3. Sub-clock Selection Settings for TB572308A/16A Sub Clock Setting Operating Mode Comments XTAL MDS XTI SMDS2/ SMDS2+ EVA CHIP KS57E2308 No connection 100 pin connector XT IN XT OUT Set the XTI switch to “MDS” when the target board is connected to the SMDS2/SMDS2+.
DEVELOPMENT TOOLS KS57C2308/P2308/C2 316/P2316 17- 6 J101 4 0-PIN DIP CONNECTOR SEG2 SEG0 COM1 COM3 V LC0 V LC2 V SS X IN XT IN RESET P0.1/ P0.3/SI P1.1/INT1 P1.3/TCL0 P2.1 P2.3/BUZ P3.1/LCDSY P3.3 P4.1 P4.3 SEG1 COM0 COM2 BIAS V LC1 V DD X OUT TEST XT OUT P0.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
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(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
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If you have not bought Samsung KS57C2308 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Samsung KS57C2308 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Samsung KS57C2308 you will learn all the available features of the product, as well as information on its operation. The information that you get Samsung KS57C2308 will certainly help you make a decision on the purchase.
If you already are a holder of Samsung KS57C2308, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Samsung KS57C2308.
However, one of the most important roles played by the user manual is to help in solving problems with Samsung KS57C2308. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Samsung KS57C2308 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
