Instruction/ maintenance manual of the product PD789488 NEC
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User’s Manual µ PD789488 µ PD789489 µ PD78F9488 µ PD78F9489 µ PD789489 Subseries 8-Bit Single-Chip Microcontrollers Printed in Japan Document No.
2 User’s Manual U15331EJ4V1UD [MEMO].
User’s Manual U15331EJ4V1UD 3 1 2 3 4 V OL T A GE APPLICA TION W A VEFORM A T INPUT PIN W av eform distor tion due to input noise or a reflected wa ve ma y cause malfunction. If the input of the CMOS de vice stays in the area between V IL (MAX) and V IH (MIN) due to noise , etc.
4 User’s Manual U15331EJ4V1UD EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Window s NT are either registered trademar ks or trademarks of Microsoft Corpora tion in the United States and/or other countrie s. PC/AT is a trademark of International Business Machines Corporation .
User’s Manual U15331EJ4V1UD 5 The information in this document is current as of July, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc.
6 User’s Manual U15331EJ4V1UD Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development envi.
User’s Manual U15331EJ4V1UD 7 Major Revisions in This Edition Page Description Throughout Change of descriptions of µ PD789489, 78F9489 • Change of status from under development to development completed • Change of the subseries name to “ µ PD789489 subseries” pp.
8 User’s Manual U15331EJ4V1UD INTRODUCTION Target Readers This manual is intended for user engineers who w ish to understand the functions of the µ PD789489 Subseries and design and develop application systems and programs for these devices.
User’s Manual U15331EJ4V1UD 9 Conve ntions Data significance: Higher digits on the left and lowe r digits on the right Active low representation: xxx (overscore over pin or signal name) Note : Footn.
10 User’s Manual U15331EJ4V1UD Documents Related to Flash Me mory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User’s Manual U13502E PG-FP4 Flash Memory Programmer User’s Manual U15260E Other Related Documents Document Name Document No.
User’s Manual U15331EJ4V1UD 11 CONTENTS CHAPTER 1 GENE RAL ........................................................................................................... ............... 26 1.1 F eatur es ................................................
12 User’s Manual U15331EJ4V1UD 3.1.4 Data me mory addr essing ................................................................................................. ............. 54 3.2 Processo r Regist ers ..............................................
User’s Manual U15331EJ4V1UD 13 5.4.5 When subsyste m clock is not us ed ....................................................................................... ...... 104 5.4.6 Subsystem clock × 4 multiplicati on circui t ..........................
14 User’s Manual U15331EJ4V1UD 9.4.1 Operation as watchdog timer ............................................................................................ .......... 171 9.4.2 Operation as interval timer ..........................................
User’s Manual U15331EJ4V1UD 15 14.1 Multip lier Func tion ..................................................................................................... .............. 267 14.2 Multiplier Configur ation .......................................
16 User’s Manual U15331EJ4V1UD CHAPTER 20 MA SK OPTIONS .................................................................................................... ....... 331 CHAPTER 21 IN STRUCTION SET ....................................................
User’s Manual U15331EJ4V1UD 17 LIST OF FIGURES (1/6) Figure No. Title Page 2-1 I/O Circu it Ty pes .......................................................................................................... ................................ 46 3-1 Memory Map ( µ PD789488) .
18 User’s Manual U15331EJ4V1UD LIST OF FIGURES (2/6) Figure No. Title Page 5-5 Format of Subc lock Control Register...................................................................................... ......................99 5-6 Subclock Select ion Register Format .
User’s Manual U15331EJ4V1UD 19 LIST OF FIGURES (3/6) Figure No. Title Page 7-21 Timing of Square-Wave Out put with 16-Bi t Resolu tion ....................................................................... .......149 7-22 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) .
20 User’s Manual U15331EJ4V1UD LIST OF FIGURES (4/6) Figure No. Title Page 11-4 Format of Asynchronous Seri al Interface M ode Regist er 20 ................................................................ ......191 11-5 Format of Asynchronous Serial Interface Status Regist er 20 .
User’s Manual U15331EJ4V1UD 21 LIST OF FIGURES (5/6) Figure No. Title Page 13-12 Four-Time-Slice LCD Displ ay Pattern and El ectrode C onnecti ons .......................................................... ..263 13-13 Example of Connecting Four-Time-Slic e LCD Panel .
22 User’s Manual U15331EJ4V1UD LIST OF FIGURES (6/6) Figure No. Title Page 17-3 Releasing HALT Mode by R ESET I nput...................................................................................... ...............311 17-4 Releasing STOP Mode by Interr upt.
User’s Manual U15331EJ4V1UD 23 LIST OF TABLES (1/3) Table No. Title Page 2-1 Types of Pin I/O Cir cuits ................................................................................................ .............................. 45 3-1 Internal ROM C apacity .
24 User’s Manual U15331EJ4V1UD LIST OF TABLES (2/3) Table No. Title Page 10-1 Configuration of 10-Bit A/D Conver ter ................................................................................... .....................173 11-1 Configuration of Serial In terfac e 20 .
User’s Manual U15331EJ4V1UD 25 LIST OF TABLES (3/3) Table No. Title Page 21-1 Operand Identifiers and Descripti on Met hods ............................................................................. ............... 332 25-1 Surface Mounting Ty pe Soldering Conditi ons .
26 User’s Manual U15331EJ4V1UD CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Data Memory Part Number Program Memory (ROM) Internal RAM LCD Display RAM µ PD789488 Mask ROM µ PD78F9.
CHAPTER 1 GENERA L User’s Manual U15331EJ4V1UD 27 1.3 Ordering Information Part Number Package Internal ROM µ PD789488GC- ××× -8BT 80-pin plastic QFP (14 × 14) Mask ROM µ PD789488GK- ××× -9.
CHAPTER 1 GENERA L 28 User’s Manual U15331EJ4V1UD 1.4 Pin Configuration (Top View ) (1) µ PD789488, 78F9488 80-pin plastic QFP (14 × 14) µ PD789488GC- ××× -8BT µ PD78F9488GC-8BT µ PD789488GC.
CHAPTER 1 GENERA L User’s Manual U15331EJ4V1UD 29 Cautions 1. Connect the IC (Internally Connected) pin directly to V SS . 2. Connect th e A V DD pin to V DD .
CHAPTER 1 GENERA L 30 User’s Manual U15331EJ4V1UD Notes 1. Whether to use these pins as i nput port pins (P70 to P73) or s egment outputs (S16 to S19) can be selected in 1-bit units by means of a ma sk option or port function register (refer to 4.3 (3) Port function registers and CHAPTER 20 MA SK OPTIONS ).
CHAPTER 1 GENERA L User’s Manual U15331EJ4V1UD 31 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
CHAPTER 1 GENERA L 32 User’s Manual U15331EJ4V1UD The major functional differences bet ween the subseries are listed below . Series for General-purpose applications and LCD drive Timer V DD Function Subseries Name ROM Capacity 8-Bit 16-Bit Watc h WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O MIN.
CHAPTER 1 GENERA L User’s Manual U15331EJ4V1UD 33 Series for ASSP Timer V DD Function Subseries Name ROM Capacity 8-Bit 16-Bit Watc h WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O MIN. Value Remarks USB µ PD789800 8 KB 2 ch − − 1 ch − − 2 ch (USB: 1 ch) 31 4.
CHAPTER 1 GENERA L 34 User’s Manual U15331EJ4V1UD 1.6 Block Diagram 78K/0S CPU core ROM (flash memory) RAM V DD V SS IC0 (V PP ) CPT20/TO20/P33 8-bit timer/ event counter 60 P00 to P07 Port 0 P10 to.
CHAPTER 1 GENERA L User’s Manual U15331EJ4V1UD 35 1.7 Overview of Functions (1/2) Item µ PD789488 µ PD78F9488 µ PD789489 µ PD78F9489 ROM 32 KB 32 KB (flash memory) 48 KB 48 KB (flash memory) Hig.
CHAPTER 1 GENERA L 36 User’s Manual U15331EJ4V1UD (2/2) Item µ PD789488 µ PD78F9488 µ PD789489 µ PD78F9489 Supply voltage V DD = 1.8 to 5.5 V Operating ambient temperature T A = − 40 to +85 ° C Package • 80-pin plastic QFP (14 × 14) • 80-pin plastic TQFP (fine pitch) (12 × 12) An outline of the timer is shown below .
User’s Manual U15331EJ4V1UD 37 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins (1/2) Pin Name I/O Function After Reset Alternate Function P00 to P07 I/O Port 0.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 38 (1) Port pins (2/2) Pin Name I/O Function After Reset Alternate Function P70 to P73 Note 1 Input Port 7. 4-bit input port. (Only when input port is selected by mask option or port function register) Input − P80 to P87 Note 2 I/O Port 8.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 39 (2) Non-port pins (2 /2) Pin Name I/O Function After Reset Alternate Function S0 to S15 LCD controller/driver segment signal outputs Low-level .
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 40 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port. In additi on, these pins enable key return signal detection. Port 0 can be specified in the follo wing operation modes in 1-bit units.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 41 2.2.4 P30 to P34 (Port 3) These pins constitute a 5-bit I/O port. In addition, they also function as timer I/O, external interrupt input, and remote control receive data input Note . Port 3 can be specified in the follo wing operation modes in 1-bit units.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 42 2.2.6 P60 to P67 (Port 6) This is an 8-bit input-only port. In addition to a general-pur pose input port function, it has A/D converter input and key return signal detection Note functions. (1) Port mode In this mode, P60 to P67 function as an 8-bit input-only port.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 43 2.2.13 RESET This pin inputs an active-low system reset signal. 2.2.14 X1, X2 These pins are used to connect a crystal res onator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 44 2.2.21 IC0 (mask ROM version only) The IC0 (Internally Connected) pin is used to set the µ PD789489 Subseries in the test mode before shipment. In the normal operation mode, direct ly connect this pin to the V SS pin w ith as short a wiring length as possible.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 45 2.3 Pin I/O Circuits and Recomme nded Connection of Unused Pins The I/O circuit type of each pin and recommended connecti on of unused pins are show n in T able 2-1. For the I/O circuit configuration of each type, see Figure 2-1.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 46 Table 2-1. Types of Pin I/O Circuits (2/2) Pin Name I/O Circuit Type I/O Re commended Connection of Unused Pins XT1 Input Connect to V SS . XT2 – – Leave open. RESET 2 Input – IC0 Connect directly to V SS .
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 47 Figure 2-1. I/O Circuit Types (2/2) Type 13-W Type 13-V Data Output disable Input enable IN/OUT N -ch V SS Mask option V DD Middle-voltage inpu.
48 User’s Manual U15331EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789489 Subseries can access 64 KB of memory space. Figures 3-1 to 3-4 show the memory maps.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 49 Figure 3-2. Memory Map ( µ PD78F9488) 8 0 0 0 H 7 F F F H Special function registers 256 × 8 bits Internal high-speed RAM 1024 × 8 bits .
CHAPTER 3 CPU A RCHITECTURE 50 User’s Manual U15331EJ4V1UD Figure 3-3. Memory Map ( µ PD789489) B F F F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 0 4 0 H 0 0 3 F H 0 0 3 0 H 0 0 2 F H Program area Program .
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 51 Figure 3-4. Memory Map ( µ PD78F9489) B F F F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 0 4 0 H 0 0 3 F H 0 0 3 0 H 0 0 2 F H F F F F H F F 0 0 H .
CHAPTER 3 CPU A RCHITECTURE 52 User’s Manual U15331EJ4V1UD 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789489 Subseries provide internal ROM (or flash me mory) w ith the following capacity for each product.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 53 3.1.2 Internal data memory space (1) Internal high-speed RAM and internal low-sp eed RA M The µ PD789489 Subseries products incorporate the internal high-speed RAM and internal low-speed RAM of the following capacity for each product.
CHAPTER 3 CPU A RCHITECTURE 54 User’s Manual U15331EJ4V1UD 3.1.4 Data memory addressing The µ PD789489 Subseries is provided with a variety of addr essing modes to make memory manipulation as efficient as possible.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 55 Figure 3-6. Data Memory Addressing ( µ PD78F9488) Special function registers 256 × 8 bits Internal high-speed RAM 1024 × 8 bits LCD disp.
CHAPTER 3 CPU A RCHITECTURE 56 User’s Manual U15331EJ4V1UD Figure 3-7. Data Memory Addressing ( µ PD789489) Direct addressing Register indirect addressing Based addressing SFR addressing Short dire.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 57 Figure 3-8. Data Memory Addressing ( µ PD78F9489) Direct addressing Register indirect addressing Based addressing SFR addressing Short dir.
CHAPTER 3 CPU A RCHITECTURE 58 User’s Manual U15331EJ4V1UD 3.2 Processor Registers The µ PD789489 Subseries is provided with the fo llow ing on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence status and stack memory.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 59 (a) Interrupt enable flag (IE) This flag controls interrupt request a cknowledgement operati ons of the CPU. When 0, IE is set to the interrupt disabled status (DI), and interrupt reques ts other than non-maskable interrupts are all disabled.
CHAPTER 3 CPU A RCHITECTURE 60 User’s Manual U15331EJ4V1UD (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the memory sta ck area.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 61 3.2.2 General-purpose registers The general-purpose registers consis t of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit r egister, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
CHAPTER 3 CPU A RCHITECTURE 62 User’s Manual U15331EJ4V1UD 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocat ed in the 256-byte area of FF00H to FFFFH.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 63 Table 3-4. Specia l Function Registers (1/3) Bit Unit for Manipulation Address Special Function Register (SFR) Name Symbol R/W 1 Bit 8 Bits.
CHAPTER 3 CPU A RCHITECTURE 64 User’s Manual U15331EJ4V1UD Table 3-4. Specia l Function Registers (2/3) Bit Unit for Manipulation Address Special Function Register (SFR) Name Symbol R/W 1 Bit 8 Bits.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 65 Table 3-4. Specia l Function Registers (3/3) Bit Unit for Manipulation Address Special Function Register (SFR) Name Symbol R/W 1 Bit 8 Bits.
CHAPTER 3 CPU A RCHITECTURE 66 User’s Manual U15331EJ4V1UD 3.3 Instruction Address Addressing An instruction address is determined by the program counter (P C) contents.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 67 3.3.2 Immediate addressing [Function] Immediate data in the in struction word is transferred to t he program counter (PC) and branched. This function is carried out when the CALL !addr 16 or BR ! addr16 instruction is executed.
CHAPTER 3 CPU A RCHITECTURE 68 User’s Manual U15331EJ4V1UD 3.3.3 Table indirect addressin g [Function] Table contents (branch destination addr ess) of the particular location to be addressed by the low er 5-bit immediate data of an instru ction code from bit 1 to bit 5 are trans ferred to the program counter (PC) and branched.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 69 3.4 Operand Address Addressing The following various methods are available to spec ify the register and memory (addressing) w hich undergo manipulation during inst ruction execution.
CHAPTER 3 CPU A RCHITECTURE 70 User’s Manual U15331EJ4V1UD 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is dire ctly addressed w ith 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 71 3.4.3 Special function register (SFR) add ressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH.
CHAPTER 3 CPU A RCHITECTURE 72 User’s Manual U15331EJ4V1UD 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are access ed as operands. The general-purpose register to be accessed is specified by a register specification code or f unctional name in the instruction code.
CHAPTER 3 CPU A RCHITECTURE User’s Manual U15331EJ4V1UD 73 3.4.5 Register indirect addressing [Function] In the register indirect addressing m ode, memory is manipulated according to the contents of a register pair specified as an operand.
CHAPTER 3 CPU A RCHITECTURE 74 User’s Manual U15331EJ4V1UD 3.4.6 Based addressing [Function] 8-bit immediate data is added to the cont ents of the base register, that is, t he HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
User’s Manual U15331EJ4V1UD 75 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789489 Subseries provides the ports shown in Figure 4-1, enabling vari ous methods of control. The functions of each port ar e shown in Table 4-1. Numerous other functions are provi ded that can be used in addition to the digital I/O port functions.
CHAPTER 4 PORT FUNCTIONS 76 User’s Manual U15331EJ4V1UD Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P07 I/O port. Input/out put can be specified in 1-bit units.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 77 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0).
CHAPTER 4 PORT FUNCTIONS 78 User’s Manual U15331EJ4V1UD 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1).
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 79 4.2.3 Port 2 This is a 6-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2).
CHAPTER 4 PORT FUNCTIONS 80 User’s Manual U15331EJ4V1UD Figure 4-5. Block Diagram of P21 Internal bus V DD P21/SO20/TxD20 WR PUB2 RD WR PORT WR PM PUB21 Alternate function Output latch (P21) PM21 Se.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 81 Figure 4-6. Block Diagram of P22 and P25 P22/SI20/ RxD20, P25/SI10 WR PUB2 RD WR PORT WR PM PUB22, PUB25 Alternate function Output latch (P22,.
CHAPTER 4 PORT FUNCTIONS 82 User’s Manual U15331EJ4V1UD Figure 4-7. Block Diagram of P23 Internal bus V DD P-ch P23/SCK10 WR PUB2 RD WR PORT WR PM PUB23 Alternate function Output latch (P23) PM23 Al.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 83 Figure 4-8. Block Diagram of P24 Internal bus V DD P24/SO10 WR PUB2 RD WR PORT WR PM PUB24 Alternate function Output latch (P24) PM24 Selector.
CHAPTER 4 PORT FUNCTIONS 84 User’s Manual U15331EJ4V1UD 4.2.4 Port 3 This is a 5-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3).
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 85 Figure 4-10. Block Diagram of P34 (a) When µ PD789488, 78F9488 is used P34 WR PUB3 RD WR PORT WR PM PUB34 PM34 V DD P-ch Internal bus Selecto.
CHAPTER 4 PORT FUNCTIONS 86 User’s Manual U15331EJ4V1UD 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on- chip pull-up resistor can be specified by a mask option.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 87 4.2.6 Port 6 This is an 8-bit input-only port. This port is also used for the analog input of an A/D converter and key return signal input Note . Figure 4-12 shows a block diagram of port 6. Note µ PD789489 and 78F9489 only.
CHAPTER 4 PORT FUNCTIONS 88 User’s Manual U15331EJ4V1UD Figure 4-12. Block Diagram of P60 to P67 (2/2) (b) When µ PD789489, 78F9489 is used V REF RD Alternate function P60/ANI0/KR10 to P67/ANI7/KR1.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 89 4.2.7 Port 7 This is a 4-bit input-only port. Only the bits for w hic h the port function is selected can be used, by using a mask option in the µ PD789488 and 789489 or port function r egister 7 (PF7) in the µ PD78F9488 and 78F9489.
CHAPTER 4 PORT FUNCTIONS 90 User’s Manual U15331EJ4V1UD 4.2.8 Port 8 This is an 8-bit I/O port with an output latch. Only the bi ts for which the port function is selected can be used, by using a mask option in the µ PD789488 and 789489 or port function r egister 8 (PF8) in the µ PD78F9488 and 78F9489.
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 91 4.3 Registers Controlling Port Function The ports are controlled by the fo llowing three ty pes of registers.
CHAPTER 4 PORT FUNCTIONS 92 User’s Manual U15331EJ4V1UD Table 4-3. Port Mode Regis ters and Output Latch Settings When Using A lternate Functions Alternate Function Pin Name Name I/O PM ×× P ×× .
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 93 (2) Pull-up res istor option registers (PUB0 to PUB3) These registers set whether to use on-chip pull-up resist ors for pins P00 to P07, P10, P11, P20 to P25, and P30 to P34.
CHAPTER 4 PORT FUNCTIONS 94 User’s Manual U15331EJ4V1UD 4.4 Port Function Operation The operation of a port differs depending on w hether the port is set in the input or output m ode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output la tch of a port by using a transfer inst ruction.
User’s Manual U15331EJ4V1UD 95 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following tw o types of system clock oscillators are used. • Main system clock oscillator This circuit oscillates at 1.
CHAPTER 5 CLOCK GENERA TOR 96 User’s Manual U15331EJ4V1UD Figure 5-1. Clock Generator Blo ck Diagram ( µ PD789488, 789489) f XT 8f XT f XTT X1 X2 XT1 XT2 f X f X 2 2 f XTT 2 1/2 Prescaler Standby c.
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 97 Figure 5-2. Clock Generator Blo ck Diagram ( µ PD78F9488, 78F9489) Subsystem clock oscillator f XT X1 X2 XT1 XT2 Main system clock oscillat.
CHAPTER 5 CLOCK GENERA TOR 98 User’s Manual U15331EJ4V1UD 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following four registers.
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 99 (2) Subclock oscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 5 CLOCK GENERA TOR 100 User’s Manual U15331EJ4V1UD (4) Subclock selection register (SSCK) ( µ PD78F9488, 78F9489 only) This register is used to control the oper ation of the × 4 subsystem clock multiplication circuit. SSCK is set via a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 101 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins.
CHAPTER 5 CLOCK GENERA TOR 102 User’s Manual U15331EJ4V1UD 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz T YP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit.
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 103 5.4.3 Example of incorrect resonato r connection Figure 5-9 shows examples of incorrect resonator connection.
CHAPTER 5 CLOCK GENERA TOR 104 User’s Manual U15331EJ4V1UD Figure 5-9. Examples of In correct Resonator Connection (2/2) (e) Signal is fetched V SS X1 X2 Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series.
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 105 5.5 Clock Generator Operation The clock generator generates the follo wing clocks and controls the operation modes of the CPU, such as the standby mode.
CHAPTER 5 CLOCK GENERA TOR 106 User’s Manual U15331EJ4V1UD 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for sw itching betw een system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
CHAPTER 5 CLOCK GENERA TOR User’s Manual U15331EJ4V1UD 107 5.6.2 Sw itching between sy stem clock and CPU clock The following figure illustrates how the CPU clock and system clock switch.
108 User’s Manual U15331EJ4V1UD CHAPTER 6 16-BIT TIMER 20 6.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value match.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 109 Figure 6-1. Block Diagram of 16-Bit T imer 20 CPT20/TO20 /INTP3/P33 Internal bus Internal bus 16-bit timer mode control register 20 (TMC20) .
CHAPTER 6 16-BIT TIMER 20 110 User’s Manual U15331EJ4V1UD (4) 16 -bit counter read buffer 20 This buffer is used to latch and hold the count value for TM20. 6.3 Registers Controlling 16-Bit Timer 20 16-bit timer 20 is controlled by the follow ing three registers.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 111 Figure 6-2. Format of 16-Bit Timer Mode Control Re gister 20 Symbol <7> <6> 5 4 3 2 1 <0> Address After reset R/W TMC20 TO.
CHAPTER 6 16-BIT TIMER 20 112 User’s Manual U15331EJ4V1UD (2) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P33/INTP3/CPT20/T O20 pin as a capture input (CPT20), set PM33 to 1. When using the above pin as a timer output (TO20), set the PM33 and P33 output latches to 0.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 113 6.4 16-Bit Timer 20 Operation 6.4.1 Operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running c ounter value reaches the value set to CR20.
CHAPTER 6 16-BIT TIMER 20 114 User’s Manual U15331EJ4V1UD Figure 6-5. Timing of Timer Interrupt Opera tion CR20 INTTM20 TO20 TOF20 NN N N N t 0000H N FFFFH N 0000H 0001H 0001H Count clock TM20 count.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 115 6.4.2 Operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter va lue reaches the value set to CR20.
CHAPTER 6 16-BIT TIMER 20 116 User’s Manual U15331EJ4V1UD 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 20 (TM20) into a capture register in synchronization w ith a capture tr igger, and retaining the count value.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 117 6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out using a 16-bit m anipulation instruction. TM20 readout is performed via t he counter read buffer.
CHAPTER 6 16-BIT TIMER 20 118 User’s Manual U15331EJ4V1UD 6.5 Cautions on Using 16-Bit Timer 2 0 6.5.1 Restrictions w hen rewr iting 16-b it compare register 20 (1) Disable interrupts (T MMK20 = 1) and inversion contro l of timer output (TOC20 = 0) before rew riting the compare register (CR20).
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 119 <Countermeasure B> When rew riting using 16-bit access <1> Disable interrupts (TMMK20 = 1) and invers ion control of timer output (TOC20 = 0). <2> Rew rite CR20 (16 bits). <3> Wait for one cycle or more of the count clock.
120 User’s Manual U15331EJ4V1UD CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.1 Functions of 8-Bit Timers 50, 60, and 61 One 8-bit timer channel (timer 50) and two 8-bit timer/ev ent counter channels (timer 60 and 61) are incorporated in the µ PD789489 Subseries.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 121 (5) PPG output mode (PPG: Programmable Pulse Generator) Pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse w idth are programmable).
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 122 7.2 Configuration of 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 in clude the follow ing hardware.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 123 Figure 7-2. Block Diagram of Timer 50 TEG50 TCL500 TCL501 8-bit timer mode control register 50 (TMC50) Decoder Selector Selecto.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 124 TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600 8-bit timer mode control register 60 (TMC60) Carrier generator output control r.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 125 TCE61 TCL612 TCL611 TCL610 TMD611 TMD610 TOE610 8-bit timer mode control register 61 (TMC61) Decoder 8-bit timer counter 61 (TM.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 126 Figure 7-5. Block Diagram of Outp ut Controller (Timer 60) F/F RMC60 NRZ60 TOE60 PM31 P31 output latch Selector TO60/INTP1/P31 .
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 127 (4) 8-bit H w idth comp are registers 60 and 61 (CRH60, CRH61) In carrier generator mode and PPG output mode, the high-leve l width of timer output is set by writing a value to CRH6n.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 128 7.3 Control Registers for 8-Bit Timers 50, 60, and 61 8-bit timers 50, 60, and 61 are contro lled by the follow ing six registers.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 129 Figure 7-6. Format of 8-Bit Timer Mode Control Regis ter 50 (2/2) Symbol <7> <6> 5 4 3 2 1 <0> Address After .
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 130 Figure 7-7. Format of 8-Bit Timer Mode Control Regis ter 60 Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W TMC6.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 131 (3) Carrier generator output control register 60 (TCA60) This register is used to set the time r output data in carri er generator mode. TCA60 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 132 (4) 8-bit timer mod e control register 61 (TMC61) 8-bit timer mode control register 61 (TMC61) is us ed to control the timer 61 count clock setting and the operation mode setting.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 133 (5) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P30/INTP0/TO 50/TMI60 pin as a timer out put (TO50), set PM30 and th e P30 output latch to 0.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 134 7.4 Operation of 8-Bit Timers 50, 60, and 61 7.4.1 Operation as 8-bit timer counter Timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 135 Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 Minimum Interval Time Maximum Interval Time Resolution 0 0 0 1/f X (0.2 µ s) 2 8 /f X (51.2 µ s) 1/f X (0.2 µ s) 0 0 1 2 3 /f X (1.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 136 Figure 7-11. Timing of Interv al Timer Operat ion with 8-Bit Resolution (Basic Operation) Count stop Count clock CRnm TCEnm INT.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 137 Figure 7-13. Timing of Interv al Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH) Count clock CRnm TCEnm INTTMnm TOnm FFH TMnm FFH 00H 01H 00H 01H 00H FFH 00H 01H FFH FFH 00H Clear Clear Clear Count start Remark nm = 50, 60, 61 Figure 7-14.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 138 Figure 7-15. Timing of Interv al Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N > M)) Count clock C.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 139 Figure 7-16. Timing of Interv al Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Cou.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 140 (2) Ope ration as external ev ent counter with 8-bit resolution (timer 60 and timer 61 only ) The external event counter counts the number of external clock pulses input to the TMI6m pin by using 8-bit timer counter 6m (TM6m).
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 141 (3) Operation as square-wave output w ith 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (CRnm).
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 142 Table 7-7. Square-Wav e Output Range of Timer 60 TCL602 TCL601 TCL600 Minimum Pulse Width Maximum Pulse Width Resolution 0 0 0 1/f X (0.2 µ s) 2 8 /f X (51.2 µ s) 1/f X (0.2 µ s) 0 0 1 2 2 /f X (0.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 143 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 144 Table 7-9. Interval Time with 16-Bit Reso lution TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time Resolution 0 0 0 1/f X (0.2 µ s) 2 16 /f X (13.1 ms) 1/f X (0.2 µ s) 0 0 1 2 2 /f X (0.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 145 Interval time Count clock TM60 count value CR60 TCE60 INTTM60 TO60 FFH 00H 7FH 00H N 00H NN N N 80H 7FH 80H FFH 00H N 00H N N N.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 146 (2) Ope ration as external e vent counter with 16-bit resolution The external event counter counts t he number of external clock pulses input to the T MI60 pin by TM50 and TM60.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 147 TMI60 pin input TM60 count value CR60 TCE60 INTTM60 FFH 00H 7FH 00H N 00H NN N N 80H 7FH 80H FFH 00H N 00H N N N TM50 count pul.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 148 (3) Operation as square-wave output w ith 16-bit resolution Square waves of any frequency can be out put at an interval specified by the count value preset in CR50 and CR60.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 149 Count clock TM60 count value CR60 TCE60 INTTM60 TO60 Note FFH 00H 7FH 00H N 00H NN N N 80H 7FH 80H FFH 00H N 00H N N N TM50 cou.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 150 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cy cle set in TM 50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 151 Figure 7-22. Timing of Carrier Ge nerator Operation (When CR60 = N, CRH60 = M (M > N)) TM60 count clock TM60 count value CR6.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 152 Figure 7-23. Timing of Carrier Ge nerator Operation (When CR60 = N, CRH60 = M (M < N)) TM60 count clock TM60 count value CR6.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 153 Figure 7-24. Timing of Carrier Ge nerator Operation (When CR60 = CRH60 = N) TM60 count clock TM60 count value CR60 TCE60 INTTM6.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 154 7.4.4 PWM output mode operation (timer 50 ) In the PWM output mode, TO50 becom es high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-running).
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 155 Figure 7-26. Opera tion Timing When Overwriting CR50 (When Rising Edge Is Se lected) (1) When setting CR50 > TM50 after ov e.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 156 Figure 7-27. Opera tion Timing in PWM Output Mode (When Both Edges A re Selected) (1) CR50 = Ev en number Count clock CR50 TCE5.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 157 Figure 7-28. Oper ation Timing in PWM Output Mode (When Both Edges Are Selected) (When CR50 Is Overwritten) Count clock CR50 TC.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 158 7.4.5 PPG output mode operation (timer 60 and timer 61) In the PPG output mode, a pulse of any duty ratio can be output by setting a low-level w idth using CR6m and a high-level width using CRH6m.
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 159 Figure 7-29. PPG Output Mode Timing (Bas ic Operation) Count clock TM6m count value CR6m TCE6m INTTM6m 00H N 00H 01H N CRH6m M .
CHAPTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 160 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61 (1) Error on starting timer An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being generated.
User’s Manual U15331EJ4V1UD 161 CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the follow ing functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 shows a block diagram of the w atch timer.
CHAPTER 8 WA TCH TIMER 162 User’s Manual U15331EJ4V1UD (1) Watch timer An interrupt request (INTWT) occurs at an interval of 0.5 second when using ei ther the 4.19 MHz main system clock or the 32.768 kHz subsystem clock. Also, an interrupt request (INTWT) occurs at an in terval of 1.
CHAPTER 8 WA TCH TIMER User’s Manual U15331EJ4V1UD 163 8.3 Control Registers for Watch Timer The watch timer is controlled by the follow ing registers.
CHAPTER 8 WA TCH TIMER 164 User’s Manual U15331EJ4V1UD (2) Watch timer interrupt ti me selection register (W TIM) This register is used to set the interrupt time by select ing either the source clock or the clock divided by 2 for the subsystem clock to be input to w atch timer.
CHAPTER 8 WA TCH TIMER User’s Manual U15331EJ4V1UD 165 8.4 Watch Timer Operation 8.4.1 Operation as w atch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the w atch timer to operate at 0.5-second intervals. Also, an interrupt request (INTWT) occurs at an interv al of 1.
CHAPTER 8 WA TCH TIMER 166 User’s Manual U15331EJ4V1UD Figure 8-4. Watch Timer/Interv al Timer Operation Timing 0H Start Overflow Overflow 5-bit counter Count clock f W /2 9 Watch timer interrupt INTWT Interval timer interrupt INTWTI Watch timer interrupt time (0.
User’s Manual U15331EJ4V1UD 167 CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the follow ing functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the w atchdog time r mode register (WDTM).
CHAPTER 9 WA TCHDOG TIMER 168 User’s Manual U15331EJ4V1UD 9.2 Watchdog Timer Configuration The watchdog timer includes the follow ing hardware. Table 9-3. Configuration of Watc hdog Timer Item Configuration Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register (WDTM) Figure 9-1.
CHAPTER 9 WA TCHDOG TIMER User’s Manual U15331EJ4V1UD 169 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the follow ing two registers.
CHAPTER 9 WA TCHDOG TIMER 170 User’s Manual U15331EJ4V1UD (2) Watc hdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables /disables counting of the wa tchdog timer. WDTM is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 9 WA TCHDOG TIMER User’s Manual U15331EJ4V1UD 171 9.4 Watchdog Timer Operation 9.4.1 Operation as w atchdog timer The watchdog timer detects a program loop w hen bit 4 (W DT M4) of the w atchdog timer mode register (WDTM) is set to 1.
CHAPTER 9 WA TCHDOG TIMER 172 User’s Manual U15331EJ4V1UD 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDT M3) of the w atchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
User’s Manual U15331EJ4V1UD 173 CHAPTER 10 10-BIT A/D CONVERTER 10.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control eight channels (ANI0 to ANI7) of analog inputs.
CHAPTER 10 10-BIT A /D CONVERTER 174 User’s Manual U15331EJ4V1UD Figure 10-1. Block Diagram of 10-Bit A/D Converter ANI3/P63 Sample & hold circuit Voltage comparator Successive approximation reg.
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 175 (3) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input ci rcuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
CHAPTER 10 10-BIT A /D CONVERTER 176 User’s Manual U15331EJ4V1UD 10.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controll ed by the followi ng two registers.
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 177 Cautions 1. Start conversion (A DCS0 = 1) after 14 µ s have elapsed following th e setting of A DCE0. If A DCE0 is not used, the con v ersion result immediately after the setting of b it 7 (A DCS0) is undefined.
CHAPTER 10 10-BIT A /D CONVERTER 178 User’s Manual U15331EJ4V1UD 10.4 10-Bit A/D Converter Operation 10.4.1 Basic operation of 10-bit A/D converter <1> Bit 0 of A/D converter mode regist er 0 (ADML0) is set (ADCE0 = 1). <2> Select a channel for A/D conversion, using analog input channel specificati on register 0 (ADS0).
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 179 Figure 10-4. Basic Operation of 10-Bit A /D Converter Conversion time Sampling time Sampling A/D conversion Undefined Conversion resu.
CHAPTER 10 10-BIT A /D CONVERTER 180 User’s Manual U15331EJ4V1UD Figure 10-5. Relations hip Betw een A nalog Input Voltage and A /D Conversion Re sult 1,023 1,022 1,021 3 2 1 0 A/D conversion result.
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 181 10.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification regi ster 0 (ADS0) is used to select an analog input channel from ANI0 to ANI7 for A/D conversion.
CHAPTER 10 10-BIT A /D CONVERTER 182 User’s Manual U15331EJ4V1UD 10.5 Cautions Related to 10-Bit A/D Converter (1) Curre nt consumption in standby mode In standby mode, the A/D converter stops operation. Clearing bit 7 (ADCS0) and bit 0 (ADCE0) of A/D converter mode register 0 (ADML0) to 0 can reduce the curr ent consumption.
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 183 (5) Timing of unde fined A/D conv ersion result The A/D conversion value may becom e undefined if the timing of the co mpletion of A/D conversion and the timing to stop the A/D conversion operat ion conflict.
CHAPTER 10 10-BIT A /D CONVERTER 184 User’s Manual U15331EJ4V1UD (6) Noise prevention To maintain a resolution of 10 bits, watch for noise at the AV DD and ANI0 to ANI7 pins. The higher the output impedance of the analog input s ource, the larger the effect by noise.
CHAPTER 10 10-BIT A /D CONVERTER User’s Manual U15331EJ4V1UD 185 (9) Interrupt request flag (A DIF0) Changing the contents of A/D converter mode register 0 (ADML0) does not clear the interrupt request flag (ADIF0).
186 User’s Manual U15331EJ4V1UD CHAPTER 11 SERIAL INTERFACE 20 11.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-w ire serial I/O mode (1) Ope ration stop mode This mode is used when serial transfer is not performed.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 187 Internal bus Receive buffer register 20 (RXB20) Switch of the first bit Asynchronous serial interface status register 20 (ASIS20) Ser.
CHAPTER 11 SERIA L INTERFA CE 20 188 User’s Manual U15331EJ4V1UD Clock for receive detection Transmit shift clock Receive shift clock Receive detection TXE20 RXE20 CSIE20 1/2 1/2 Transmit clock coun.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 189 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmi t data is prepared. The transmit data is output from TXS20 bit-serially . When the data length is seven bits, bits 0 to 6 of t he data in T XS20 w ill be transmi t data.
CHAPTER 11 SERIA L INTERFA CE 20 190 User’s Manual U15331EJ4V1UD 11.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the follow ing six registers.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 191 (2) A synchronous serial interface mode register 20 (A SIM20) ASIM20 is used to make the settings relat ed to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 11 SERIA L INTERFA CE 20 192 User’s Manual U15331EJ4V1UD Table 11-2. Serial Interface 20 Operation Mode Setting s (1) Ope ration stop mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 PM22 .
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 193 (3) A synchronous serial interface status register 20 (A SIS20) ASIS20 indicates the type of a recepti on error, if it occurs w hile asynch ronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 11 SERIA L INTERFA CE 20 194 User’s Manual U15331EJ4V1UD (4) Baud ra te generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 195 The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal obtained by dividing the clock input to the ASCK20 pin.
CHAPTER 11 SERIA L INTERFA CE 20 196 User’s Manual U15331EJ4V1UD (b) Generation of UART baud rate transmit/receiv e clock from ext ernal clock input to A SCK20 pin The transmit/receive clock is generated by dividing t he clock input from the ASCK20 pin.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 197 11.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-w ire serial I/O mode 11.
CHAPTER 11 SERIA L INTERFA CE 20 198 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (A SIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 199 11.4.2 A synchronous serial interface (UART) mode In this mode, the one-byte data follow ing the start bit is transmitted/received, enabli ng full-duplex communication.
CHAPTER 11 SERIA L INTERFA CE 20 200 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (A SIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 201 (c) Asy nchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 11 SERIA L INTERFA CE 20 202 User’s Manual U15331EJ4V1UD (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memo ry manipulation instruction. RESET input sets BRGC20 to 00H. TPS203 0 0 0 0 0 0 0 0 1 TPS202 0 0 0 0 1 1 1 1 0 f X /2 f X /2 2 f X /2 3 f X /2 4 f X /2 5 f X /2 6 f X /2 7 f X /2 8 (2.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 203 Table 11-5. Example of Relation ship Between System Clock and Baud Rate Error (%) Baud Rate (bps) n BRGC20 Set Value f X = 5.0 MHz f X = 4.9152 MHz 1,200 8 70H 2,400 7 60H 4,800 6 50H 9,600 5 40H 19,200 4 30H 38,400 3 20H 76,800 2 10H 1.
CHAPTER 11 SERIA L INTERFA CE 20 204 User’s Manual U15331EJ4V1UD (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figur e 11-7. One data frame c onsists of a start bit, character bits, parity bit, and stop bit(s).
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 205 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally , the same kind of parity bit is used on the transmitting side and the receiving side.
CHAPTER 11 SERIA L INTERFA CE 20 206 User’s Manual U15331EJ4V1UD (c) Transmission A transmit operation is started by w r iting transmit data to transmit shift register 20 (TXS20).
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 207 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of t he RxD20 pin input is performed.
CHAPTER 11 SERIA L INTERFA CE 20 208 User’s Manual U15331EJ4V1UD (e) Receive errors The following three errors may occur during a receiv e operation: a parity e rror, framing error, and overrun error. After data reception, an error flag is se t in asynchronous serial in terface status register 20 (ASIS20).
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 209 (f) Reading receive data When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the value of receive buffer register 20 (RXB20).
CHAPTER 11 SERIA L INTERFA CE 20 210 User’s Manual U15331EJ4V1UD (3) Cautions related to UART mode (a) When bit 7 (T XE20) of asynchronous serial inte rface mode register 20 ( ASIM20) is cleared during transmission, be sure to set transmit shift regist er 20 (TXS20) to FFH, then set T XE20 to 1 before executing the next transmission.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 211 11.4.3 3-w ire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., w hich incorporate a conventional clocked se rial interface, such as the 75XL Series, 78K Series, and 17K Series.
CHAPTER 11 SERIA L INTERFA CE 20 212 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (A SIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is sele cted, ASIM20 must be set to 00H.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 213 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memo ry manipulation instruction. RESET input sets BRGC20 to 00H. TPS203 0 0 0 0 0 0 0 0 TPS202 0 0 0 0 1 1 1 1 f X /2 f X /2 2 f X /2 3 f X /2 4 f X /2 5 f X /2 6 f X /2 7 f X /2 8 (2.
CHAPTER 11 SERIA L INTERFA CE 20 214 User’s Manual U15331EJ4V1UD (2) Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization w ith the serial clock.
CHAPTER 11 SERIA L INTERFA CE 20 User’s Manual U15331EJ4V1UD 215 Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing (CSCK20=1) 12 3 45 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last bit previously output is output.
216 User’s Manual U15331EJ4V1UD CHAPTER 12 SERIAL INTERFACE 1A0 12.1 Function of Serial Interface 1A0 Serial interface 1A0 has the following three modes.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 217 12.2 Configuration of Serial Interface 1A0 Serial interface 1A0 includes the following hardw are.
CHAPTER 12 SERIA L INTERFA CE 1A0 218 User’s Manual U15331EJ4V1UD (1) Serial I/O shift register 1A 0 (SIO1A 0) This is an 8-bit register used to carry out par allel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization w ith the serial clock.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 219 12.3 Control Registers for Serial Interface 1A0 Serial interface 1A0 is controlled by the follow ing five registers.
CHAPTER 12 SERIA L INTERFA CE 1A0 220 User’s Manual U15331EJ4V1UD Figure 12-2. Format of Serial Operatio n Mode Register 1A 0 Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W C.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 221 (2) A utomatic data transmit/receive control register 0 (ADTC0) This register sets automatic re ception enable/disable, the operation mode, and di splays the state of automatic transmit/receive control.
CHAPTER 12 SERIA L INTERFA CE 1A0 222 User’s Manual U15331EJ4V1UD (3) A utomatic data transmit/receive inte rv al specification register 0 (ADTI0) This register sets the autom atic data transmit/receive f unction data transfer interval. ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 223 Figure 12-4. Format of Automatic Data Transmit /Receiv e Interval Specification Register 0 (2/2) Symbol <7> 6 5 <4> <.
CHAPTER 12 SERIA L INTERFA CE 1A0 224 User’s Manual U15331EJ4V1UD 12.4 Serial Interface 1A0 Operation Serial interface 1A0 provides the following three modes. • Operation stop mode • 3-w ire serial I/O mode • 3-w ire serial I/O mode with automatic transmit/receive function 12.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 225 12.4.2 3-w ire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., w hich incorporate a conventional clocked se rial interface, such as the 75XL Series, 78K Series, and 17K Series.
CHAPTER 12 SERIA L INTERFA CE 1A0 226 User’s Manual U15331EJ4V1UD Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W C SI M 1A 0 CSIE10 DIR10 ATE0 LSCK10 0 0 SCL101 SCL100 FF78H .
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 227 (2) Communication operation In 3-wire serial I/O mode, data transmission/rec eption is performed in 8-bit units. Data is transmitted/received bit by bit in sync hronization with the serial clock.
CHAPTER 12 SERIA L INTERFA CE 1A0 228 User’s Manual U15331EJ4V1UD Figure 12-5. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slav e operation timing 12 3 45 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK10 SI10 Note SO10 SIO1A0 write INTCSI10 Note The value of the last bit previously output is output.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 229 (3) MSB/LSB switching as th e start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 12-6 shows the configuration of serial I/O shift register 1A0 (SIO1A0) and the internal bus.
CHAPTER 12 SERIA L INTERFA CE 1A0 230 User’s Manual U15331EJ4V1UD 12.4.3 3-w ire serial I/O mode with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/recept ion of a maximum of 16-byte data without the use of software.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 231 Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W C SI M 1A 0 CSIE10 DIR10 ATE0 LSCK10 0 0 SCL101 SCL100 FF78H .
CHAPTER 12 SERIA L INTERFA CE 1A0 232 User’s Manual U15331EJ4V1UD (b) Automatic data transmit/receive control register 0 (A DTC0) ADTC0 is set via a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 233 (c) Automatic data transmit/receiv e inte rval specification register 0 (ADTI0) ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.
CHAPTER 12 SERIA L INTERFA CE 1A0 234 User’s Manual U15331EJ4V1UD Symbol <7> 6 5 <4> <3> <2> <1> <0> Address After reset R/W A DT I 0 ADTI07 0 0 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 FF7BH 00H R/W ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification (f X = 5.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 235 (2) A utomatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the leas t significant address FFA0H of buffer RAM (up to FFAFH). T he transmit data should be in the order from higher address to lower address.
CHAPTER 12 SERIA L INTERFA CE 1A0 236 User’s Manual U15331EJ4V1UD (3) Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in w hich the specified number of data are transmitted/received in 8-bit units.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 237 Figure 12-8. Basic Transmit/Receive Mode Flow chart Remark ADTP0: Automatic data transmit/receive address pointer 0 ADTI0: Automatic.
CHAPTER 12 SERIA L INTERFA CE 1A0 238 User’s Manual U15331EJ4V1UD In 6-byte transmission/reception (bit 6 (ARLD0) and bi t 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) = 0, and 1, respectively) in basic transmit/receive mode, buffer RAM operates as follow s.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 239 Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/.
CHAPTER 12 SERIA L INTERFA CE 1A0 240 User’s Manual U15331EJ4V1UD (b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 241 Figure 12-11. Basic Transmit Mode Fl owchart Remark ADTP0: Automatic data transmit/receive address pointer 0 ADTI0: Automatic data t.
CHAPTER 12 SERIA L INTERFA CE 1A0 242 User’s Manual U15331EJ4V1UD In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/rec eive control register 0 (ADTC0) are 0) in basic transmit mode, buffer RAM operates as follows.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 243 Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte tra nsmission point Transmit d.
CHAPTER 12 SERIA L INTERFA CE 1A0 244 User’s Manual U15331EJ4V1UD (c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 245 Figure 12-14. Repeat Transmit Mod e Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtaine.
CHAPTER 12 SERIA L INTERFA CE 1A0 246 User’s Manual U15331EJ4V1UD In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/rec eive control register 0 (ADTC0) are 1 and 0, respectively) in repeat transmit mode, buffer RAM operates as follow s.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 247 Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (c) Upon completion of transmission of 6 b.
CHAPTER 12 SERIA L INTERFA CE 1A0 248 User’s Manual U15331EJ4V1UD (d) Automatic transmission/reception su spension and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) to 0.
CHAPTER 12 SERIA L INTERFA CE 1A0 User’s Manual U15331EJ4V1UD 249 (4) Timing of inte rrupt request signal generation The interrupt request signal is generated in synchroni zation w ith the timing shown in Table 12-2.
250 User’s Manual U15331EJ4V1UD CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the µ PD789489 Subseries are as follows.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 251 The correspondence with the LCD display RAM is show n in Figure 13-1 below. Figure 13-1.
CHAPTER 13 LCD CONTROLLER/DRIVER 252 User’s Manual U15331EJ4V1UD LCDC03 LCDC02 LCDC01 LCDC00 2 2 f LCD 2 6 f LCD 2 7 f LCD 2 8 f LCD 2 9 LCDON0 VAON0 V LC0 COM0 COM1 COM2 COM3 3210 3210 65 74 FA00H .
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 253 13.3 Registers Controlling LCD Controller/Driver The LCD controller/driver is controll ed by the following three registers.
CHAPTER 13 LCD CONTROLLER/DRIVER 254 User’s Manual U15331EJ4V1UD (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display . It also specifies whether to enable booster circuit operation, segment pin/common pin out put, and the display mode.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 255 (2) LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and number of time slices. LCDC0 is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 13 LCD CONTROLLER/DRIVER 256 User’s Manual U15331EJ4V1UD (3) LCD v oltage boost control register 0 (LCDVA 0) LCDVA0 controls the voltage boost le vel during the volt age boost operation. LCDVA0 is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 257 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the LCD clock using LCD clock control register 0 (LCDC0). <2> Set the voltage boost level using LCD vo ltage boost control register 0 (LCDVA0).
CHAPTER 13 LCD CONTROLLER/DRIVER 258 User’s Manual U15331EJ4V1UD 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the pot ential difference betw een the corresponding common and segment signals becomes higher than a s pecific voltage (LCD drive voltage, V LCD ).
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 259 Figure 13-7. Common Signal Wav eforms COMn (Three-time-slice mode) T F = 3 × T V LC0 V SS V LCD V LC1 V LC2 T F = 4 × T COMn (Four-time-slice mode) V LC0 V LCD V LC1 V LC2 V SS T: One LCD clock period T F : Frame frequency Figure 13-8.
CHAPTER 13 LCD CONTROLLER/DRIVER 260 User’s Manual U15331EJ4V1UD 13.7 Display Modes 13.7.1 Three-time-slice display example Figure 13-10 shows how a nine-digit LCD panel having the di splay pattern show n in Figure 13-9 is connected to the segment signals (S0 to S26) and the common signals (COM0 to COM2) of the µ PD789489 Subseries chip.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 261 Figure 13-10. Exam ple of Connecting Three-Time-Slice LCD Panel ××××××××××××××××××××××××××× x’ 00 x’ 1.
CHAPTER 13 LCD CONTROLLER/DRIVER 262 User’s Manual U15331EJ4V1UD Figure 13-11. Three-Time-Slic e LCD Drive Wav eform Examples (1/3 Bias Method) V LC0 V LC2 COM0 +V LCD 0 COM0-S9 -V LCD V LC1 +1/3V L.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 263 13.7.2 Four-time-slice display example Figure 13-13 shows how a 14-digit LCD panel having the disp lay pattern show n in Figure 13-12 is connected to the segment signals (S0 to S27) and the co mmon signals (COM0 to COM3) of the µ PD789489 Subseries chip.
CHAPTER 13 LCD CONTROLLER/DRIVER 264 User’s Manual U15331EJ4V1UD Figure 13-13. Exa mple of Connecting Four-Time-Slice LCD Panel 0010100010110010001000101000 0110010101110111011101100101 011111111010.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 265 Figure 13-14. Four-Time-Slice LCD Drive Wav eform Examples (1/3 Bias Me thod) T F V LC0 V LC2 COM0 +V LCD 0 COM0-S16 -V LCD V LC1 +1/.
CHAPTER 13 LCD CONTROLLER/DRIVER 266 User’s Manual U15331EJ4V1UD 13.8 Supplying LCD Driv e Voltages V LC0 , V LC1 , and V LC2 The µ PD789489 Subseries contains a booster circuit ( × 3 only) to generate a supply volt age to drive the LCD. T he internal LCD reference vo ltage is output from the V LC2 pin.
User’s Manual U15331EJ4V1UD 267 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function. • Calculation of 8 bits × 8 bits = 16 bits 14.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bi t result of multiplication.
CHAPTER 14 MULTIPLIER 268 User’s Manual U15331EJ4V1UD Figure 14-1. Block Diagram of Multiplier Internal bus Selector Counter value 3 CPU clock Start Clear Counter output 16-bit adder 16-bit multipli.
CHAPTER 14 MULTIPLIER User’s Manual U15331EJ4V1UD 269 14.3 Multiplier Control Register The multiplier is controlled by the following register. • Multiplier control register 0 (MULC0) (1) Multiplier control register 0 (MULC0) MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
CHAPTER 14 MULTIPLIER 270 User’s Manual U15331EJ4V1UD 14.4 Multiplier Operation The multiplier of the µ PD789489 Subseries can execute t he calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the mu ltiplier w here MRA0 is set to AAH and MRB0 is set to D3H.
User’s Manual U15331EJ4V1UD 271 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F 9489 ONLY) 15.1 Remote Controller Receiver Functions The remote controller receiver uses the following rem ote controller modes. • T ype A reception mode … Guide pulse (h alf clock) provided 15.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 272 Figure 15-1. Block Diagram of Remote Controller Receiver RIN/P34 Noise canceler f X /2 6 f X /2 7.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 273 (2) Remote contr oller receive data register (R MDR) This register holds the remote contro l ler reception data. When the remote controller receive shift register (RMSR) overflows, the data in RMSR is transferred to RM DR.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 274 (4) Remote cont roller receive GPHS compare register (RMGPHS) This register is used to detect the high level of a remote controller guid e pulse (short side).
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 275 (8) Remote cont roller receive DH0S compare register (RMDH0S) This register is used to detect the high level of remote controller data 0 (short side).
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 276 (12) Remote co ntroller receive end-w id th select register (RMER) This register determines the interval bet ween t he timing at which the INT REND signal is output.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 277 15.3 Registers to Control Remote Co ntroller Receiver The remote controller receiver is controlled b y the following register .
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 278 Figure 15-3. Format of Remo te Controller Receive Control Register (2/2) Symbol 7 6 5 4 3 2 1 0 A.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 279 15.4 Operation of Remote Controller Receiv er The following remote controller reception m ode is used for this remote controller receiver . • T ype A reception mode with guide pulse (half clock) 15.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 280 Figure 15-5. Operation Flow of Type A Reception Mode Note Read RM DR before data has been set to all the bits of RMSR.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 281 15.4.3 Timing Operation varies dependin g on the positi ons of the RIN input waveform below .
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 282 (3) Data high lev el width determination Relationship Between RMDH0S/RMDH0L/RMDH1S/RM DH1L/Counter Position of W aveform Corresponding Operation Counter < RMDH0S <1>: Short Error interrupt IN TRERR is generated.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 283 (4) End widt h determination RIN RMDLS RMDLL <1> <2> RIN RMER ∆ Relationship Between RMER/Counter Posi tion of Waveform Corresponding Operation Counter < RMER <1>: Short Error interrupt INTRERR is generated.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 284 Figure 15-6. Setting Ex ample (Where n1 = 1, n2 = 2) RIN RIN_2 T W RIN_1 Clock RMGPHS/RMDH0S/RMDH.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 285 15.4.5 Error interrupt generation timing After the guide pulse has been detected normally , the IN TRERR signal is generated und er any of the following conditions.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 286 Figure 15-7. Gene ration Timing of INTRERR Signal RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR INTREND RIN INTRERR RIN INTRERR Example 1 Counter < RMGPHS → INTRERR is not generated.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 287 15.4.6 Noise elimination This remote controller receiver provides a function that supplies the signa ls input from the outside to the RIN pin after eliminating noise.
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 288 Figure 15-8. Noise Elimination Operation Example (1/2) (a) 1-clock noise elimination (PRSEN = 0, .
CHAPTER 15 REMOTE CONTROL LER RECEIVER ( µ PD789489, 78F9489 ONL Y) User’s Manual U15331EJ4V1UD 289 Figure 15-8. Noise Elimination Operation Example (2/2) (c) 2-clock noise elimination (PRSEN = 1, .
290 User’s Manual U15331EJ4V1UD CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following tw o types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 291 Table 16-1. Interrupt Sources ( µ PD789488, 78F9488) Interrupt Source Interrupt Type Priority Note 1 Name Trigger Internal/ External V.
CHAPTER 16 INTERRUPT FUNCTIONS 292 User’s Manual U15331EJ4V1UD Table 16-2. Interrupt Sources ( µ PD789489, 78F9489) Interrupt Source Interrupt Type Priority Note 1 Name Trigger Internal/ External V.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 293 Figure 16-1. Basic Configur ation of Interrupt Function (A ) Internal non-maskable interrupt Internal bus Interrupt request Vector tabl.
CHAPTER 16 INTERRUPT FUNCTIONS 294 User’s Manual U15331EJ4V1UD 16.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 295 (1) Interrupt request flag registers (IF0 to IF2) An interrupt request flag is set (1) when the co rresponding interrupt request is generated, or w hen an instruction is executed.
CHAPTER 16 INTERRUPT FUNCTIONS 296 User’s Manual U15331EJ4V1UD (2) Interrupt mask flag registers (MK0 to MK2) Interrupt mask flags are used to enable and di sable the corresponding maskable interrupts. MK0 to MK2 are set with a 1-bit or 8- bit memory manipulation instruction.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 297 (3) External interrupt mode registers (INTM0, INT M1) These registers are used to specify the valid edge for INTP0 to INTP3. INTM0 and INTM1 are set with an 8-bit memory manipulation instruction.
CHAPTER 16 INTERRUPT FUNCTIONS 298 User’s Manual U15331EJ4V1UD (4) Program status word (PSW) The program status word is used to hold the instruction execution resu lts and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 299 (5) Key return mo de register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (rising edge of port 0). KRM00 is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 16 INTERRUPT FUNCTIONS 300 User’s Manual U15331EJ4V1UD (6) Key return mo de register 01 (KRM01) ( µ PD789489, 78F9489 only) This register is used to set the pin that is to detect the key return signal (falling edge of port 6). KRM01 is set with a 1-bit or 8-bi t memory manipulation instruction.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 301 16.4 Interrupt Servicing Operation 16.4.1 Non-maskable interrupt req uest acknowledg ment operation The non-maskable interrupt request is unconditionally ack nowledged even w hen interrupts are disabled.
CHAPTER 16 INTERRUPT FUNCTIONS 302 User’s Manual U15331EJ4V1UD Figure 16-10. Flow from Generation of Non-Maskable In terrupt Request to A cknow ledgment Start WDTM4 = 1 (watchdog timer mode is selec.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 303 16.4.2 Maskable interrupt request ackno wledgment op eration A maskable interrupt request can be acknowledged w hen the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0.
CHAPTER 16 INTERRUPT FUNCTIONS 304 User’s Manual U15331EJ4V1UD Figure 16-14. Interrupt Reque st Acknowledgment Timing (Example: MOV A , r) Clock CPU MOV A, r Saving PSW and PC, and jump to interrupt.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 305 Figure 16-16. Example of Mu ltiple Interrupt Servicing Example 1. A cknowledging multiple interrupts INTyy EI Main servicing EI INTyy s.
CHAPTER 16 INTERRUPT FUNCTIONS 306 User’s Manual U15331EJ4V1UD 16.4.4 Putting interrupt reque sts on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being execut ed, the interrupt request will not be acknow ledged until the instruct ion is completed.
User’s Manual U15331EJ4V1UD 307 CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the follow ing two modes. (1) HA LT mode This mode is set when the HALT inst ruction is executed.
CHAPTER 17 STA NDBY FUNCTION 308 User’s Manual U15331EJ4V1UD 17.1.2 Registe r controlling standby function The wait time after the STOP mode is released upon in terrupt request generation until oscillation stabilizes is controlled by the oscillation stabilizati on time selection register (OSTS).
CHAPTER 17 STA NDBY FUNCTION User’s Manual U15331EJ4V1UD 309 17.2 Standby Function Operation 17.2.1 HALT mode (1) HA LT mode The HALT mode is set by exec uting the HALT instruction. The operation statuses in the HALT m ode are shown in the following table.
CHAPTER 17 STA NDBY FUNCTION 310 User’s Manual U15331EJ4V1UD (2) Releasing HA LT mode The HALT mode can be released by the following three sources. (a) Release by unmasked interrupt request The HALT mode is released by an unmasked interrupt request.
CHAPTER 17 STA NDBY FUNCTION User’s Manual U15331EJ4V1UD 311 (c) Release by RESET input When the HALT mode is released by the RESET signal , execution branches to the reset vector address in the same manner as the ordinary reset oper ation, and program exec ution is started.
CHAPTER 17 STA NDBY FUNCTION 312 User’s Manual U15331EJ4V1UD 17.2.2 STOP mode (1) Se tting and operation status of STOP mode The STOP mode is set by exec uting the STOP instruction.
CHAPTER 17 STA NDBY FUNCTION User’s Manual U15331EJ4V1UD 313 (2) Releasing STOP mode The STOP mode can be released by the following tw o sources. (a) Release by unmasked interrupt request The STOP mode can be released by an unmasked interr upt request.
CHAPTER 17 STA NDBY FUNCTION 314 User’s Manual U15331EJ4V1UD (b) Release by RESET input When the STOP mode is released by the RESET si gnal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 17-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Wait (2 15 /f X : 6.
User’s Manual U15331EJ4V1UD 315 CHAPTER 18 RESET FUNCTION The following tw o operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by w atchdog timer program loop time detection External and internal reset have no functional differences.
CHAPTER 18 RESET FUNCTION 316 User’s Manual U15331EJ4V1UD Figure 18-2. Reset Timing by RESET Input X1 RESET Internal reset signal Port pin During normal operation Delay Delay Hi-Z Reset period (oscillation stops) Normal operation (reset processing) Oscillation stabilization time wait Figure 18-3.
CHAPTER 18 RESET FUNCTION User’s Manual U15331EJ4V1UD 317 Table 18-1. Status of Hardw are A fter Reset (1/2) Hardware Status After Reset Program counter (PC) Note 1 Contents of reset vector table (0.
CHAPTER 18 RESET FUNCTION 318 User’s Manual U15331EJ4V1UD Table 18-1. Status of Hardw are A fter Reset (2/2) Hardware Status After Reset Operation mode register (CSIM1A0) 00H Shift register (SIO1A0).
User’s Manual U15331EJ4V1UD 319 CHAPTER 19 FLASH MEMORY VERSION The µ PD78F9488 is available as the flash memory version of the µ PD789488 (mask ROM version). The µ PD78F9489 is available as the flash memory version of the µ PD789489 (mask ROM version).
CHAPTER 19 FLA SH MEMORY VERSION 320 User’s Manual U15331EJ4V1UD 19.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no.
CHAPTER 19 FLA SH MEMORY VERSION User’s Manual U15331EJ4V1UD 321 19.1.2 Communication mod e Use the communication mode shown in Table 19-2 to perform communication between the dedicated flash programmer and µ PD78F9488 or 78F9489.
CHAPTER 19 FLA SH MEMORY VERSION 322 User’s Manual U15331EJ4V1UD Figure 19-3. Example of Co nnection w ith Dedicated Flash Programmer (a) 3-w ire serial I/O Dedicated flash programmer VPP1 VDD RESET.
CHAPTER 19 FLA SH MEMORY VERSION User’s Manual U15331EJ4V1UD 323 If Flashpro III/Flashpro IV is used as a dedicated flas h programmer, the following signals are generated for the µ PD78F9488 and 78F9489. For details, refer to the manual of Flashpro III/Flashpro IV.
CHAPTER 19 FLA SH MEMORY VERSION 324 User’s Manual U15331EJ4V1UD 19.1.3 On-board pin processin g When performing programming on the target sy stem, provide a connector on t he target system to connect the dedicated flash programmer.
CHAPTER 19 FLA SH MEMORY VERSION User’s Manual U15331EJ4V1UD 325 (1) Signal conflict If the dedicated flash programmer (output ) is connected to a serial interfac e pin (input) that is connected to another device (output), a signal conflict occurs.
CHAPTER 19 FLA SH MEMORY VERSION 326 User’s Manual U15331EJ4V1UD <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occu rs. To prevent this, isolate the c onnection w ith the reset signal generator.
CHAPTER 19 FLA SH MEMORY VERSION User’s Manual U15331EJ4V1UD 327 19.1.4 Connection of adap ter for flash writing The following figure show s an example of recommended c onnection when the adapter for flash writing is used.
CHAPTER 19 FLA SH MEMORY VERSION 328 User’s Manual U15331EJ4V1UD Figure 19-9. Wiring Example for Flash Writing A dapter w ith 3-Wire Serial I/O w ith Handshake PD78F9488, PD78F9489 GND VDD VDD2 (L VDD) SI SO SCK CLKOUT RESET VPP RESERVE/HS WRITER INTERF ACE VDD (2.
CHAPTER 19 FLA SH MEMORY VERSION User’s Manual U15331EJ4V1UD 329 Figure 19-10. Wiring Example for Flash Writing Adapter with UA RT GND VDD SI SO SCK CLK OUT RESET VPP RESER VE/HS WRITER INTERF ACE VDD (2.
CHAPTER 19 FLA SH MEMORY VERSION 330 User’s Manual U15331EJ4V1UD 19.2 Cautions on µ PD78F9488 and 78F9489 (1) Whe n using HALT mode with subclock multiplied by four Observe the following constraints w hen using the flash version ( µ PD78F9488 and 78F9489) in the HALT mode with the subclock multiplied by 4 as the CPU clock.
User’s Manual U15331EJ4V1UD 331 CHAPTER 20 MASK OPTIONS The µ PD789488 and 789489 have the following mask options. • Pin function The segment pins of the LCD and port 7 (i nput port) can be selected in 1-bit units. <1> S (16 + n) <2> P7n (n = 0 to 3) The segment pins of the LCD and port 8 (I/O port) can be selected in 1-bit units.
332 User’s Manual U15331EJ4V1UD CHAPTER 21 INSTRUCTION SET This chapter lists the instruction set of the µ PD789489 Subseries. For details of the operation and machine language (instruction code) of eac h instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E) .
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 333 21.1.2 Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E .
CHAPTER 21 INSTRUCTION SET 334 User’s Manual U15331EJ4V1UD 21.2 Operation List Mnemonic Operands Bytes Clocks Operation Flag Z AC CY MOV r, #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte sfr.
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 335 Mnemonic Operands Bytes Clocks Operation Flag Z AC CY MOVW rp, #word 3 6 rp ← wor d AX, saddrp 2 6 AX ← (saddrp) saddrp, AX 2 8 (saddrp.
CHAPTER 21 INSTRUCTION SET 336 User’s Manual U15331EJ4V1UD Mnemonic Operands Bytes Clocks Operation Flag Z AC CY SUBC A, #byte 2 4 A, CY ← A − byte − CY x x x saddr, #byte 3 6 (saddr), CY ← .
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 337 Mnemonic Operands Bytes Clocks Operation Flag Z AC CY CMP A, #byte 2 4 A − byte x x x saddr, #byte 3 6 (saddr) − byte x x x A, r 2 4 A .
CHAPTER 21 INSTRUCTION SET 338 User’s Manual U15331EJ4V1UD Mnemonic Operands Bytes Clocks Operation Flag Z AC CY CALL !addr16 3 6 (SP − 1) ← (PC + 3) H , (SP − 2) ← (PC + 3) L , PC ← addr1.
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 339 21.3 Instructions Listed by Addressing Ty pe (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC , AND, OR, XOR, CMP, INC, DEC, ROR, ROL,.
CHAPTER 21 INSTRUCTION SET 340 User’s Manual U15331EJ4V1UD (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand #word AX rp Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note I N C W DECW PUSH POP saddrp MOVW s p M O V W Note Only w hen rp = BC, DE, or HL.
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 341 (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand AX !addr16 [addr5] $addr16 Basic .
342 User’s Manual U15331EJ4V1UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) A bsolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Ratings Unit V DD Power supply voltage AV DD V DD = AV DD − 0.3 to +6.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 343 Caution Product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 344 User’s Manual U15331EJ4V1UD Main System Clock Osc illator Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 345 Subsystem Clock Oscilla tor Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 346 User’s Manual U15331EJ4V1UD DC Characteristics (T A = –40 to +85 ° C, V DD = 1.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 347 DC Characteristics (T A = –40 to +85 ° C, V DD = 1.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 348 User’s Manual U15331EJ4V1UD DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (3/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 5.0 V ± 10% Note 2 2 3.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 349 DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (4/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 5.0 V ± 10% Note 2 5.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 350 User’s Manual U15331EJ4V1UD DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (5/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 5.0 V ± 10% Note 2 2.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 351 DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (6/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 5.0 V ± 10% Note 2 6.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 352 User’s Manual U15331EJ4V1UD AC Characteristics (1) Basic operation (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 2.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 353 (2) Serial interface 20 (SIO20) (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter Symbol Conditions MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 354 User’s Manual U15331EJ4V1UD (d) UART mode (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 2.7 to 5.5 V 800 ns ASCK20 cycle time t KCY3 V DD = 1.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 355 (3) Serial interface 1A0 (SIO1A 0) (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (a) 3-w ire serial I/O mode, 3-w i re serial I/O mode with automa tic transmit/receive function (internal clock output) Parameter Symbol Conditions MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 356 User’s Manual U15331EJ4V1UD A C Timing Measurement Points (Excluding X1 and XT1 Inputs) 0.8V DD 0.2V DD Point of measurement 0.8V DD 0.2V DD Clock Timing 1/f X t XL t XH X1 input V IH4 (MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 357 Key Return Input Timing t KRL KR0 to KR7 ( PD789488, 78F9488) , KR00 to KR07, KR10 to .
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 358 User’s Manual U15331EJ4V1UD 10-Bit A/D Conv erter Characteristics (T A = –40 to +85 ° C, 1.8 V ≤ AV DD = V DD ≤ 5.5 V, AV SS = V SS = 0 V) Parameter Symbol Conditions MIN.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 359 LCD Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit GAIN = 1 0.84 1.0 1.165 V LCD output voltage variation range V LCD2 C1 to C4 Note 1 = 0.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) 360 User’s Manual U15331EJ4V1UD Data Retention Timing (STO P Mode Release by RESET) V DD Data retention mode STOP mode.
CHAPTER 22 ELECTRICA L SPECIFICA TIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 361 Flash Memory Writing and Erasing Characteristics (T A = 10 to 40 ° C, V DD = 1.8 to 5.5 V) ( µ PD78F9488, 78F9489 only) Parameter Symbol Conditions MIN.
362 User’s Manual U15331EJ4V1UD CHAPTER 23 CHARACTERISTICS CUR VES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curv es of volta ge boosting stabilization time The following show .
CHAPTER 23 CHA RA CTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) User’s Manual U15331EJ4V1UD 363 (2) Temp erature characteristics of LCD output voltage T he follow ing shows the temperature charac teristics curves of LCD output voltage.
364 User’s Manual U15331EJ4V1UD CHAPTER 24 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.20 ± 0.20 14.00 ± 0.20 0.
CHAPTER 24 PA CKA GE DRAWINGS User’s Manual U15331EJ4V1UD 365 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) ITEM MILLIMETERS G H 0.22 ± 0.05 1.25 A 14.0 ± 0.2 C 12.0 ± 0.2 D F 1.25 14.0 ± 0.2 B 12.0 ± 0.2 M N 0.08 0.145 ± 0.05 P Q 0.1 ± 0.05 1.0 J 0.
366 User’s Manual U15331EJ4V1UD CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS The µ PD789489 subseries should be soldered and mount ed under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative.
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS User’s Manual U15331EJ4V1UD 367 Table 25-1. Surface Mounting Ty pe Soldering C onditions (2/3) (3) µ PD78F9489GC-8BT: 80-pin plastic QFP (14x14) Soldering Method Soldering Conditions Recommended Condition Symbol Interface reflow Package peak temperature: 235 ° C, Time:30 seconds max.
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS 368 User’s Manual U15331EJ4V1UD Table 25-1. Surface Mounting Type Soldering Conditions (3/3) (5) µ PD789488GC- ××× -8BT-A: 80-pin plastic QFP (14x14) .
369 User’s Manual U15331EJ4V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are availabl e for development of systems using the µ PD789489 Subseries.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 370 Figure A -1. Development Tools Language processing software · Assembler package · C compiler package · Device file · C library source.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 371 A.1 Softw are Package Software tools for development of the 78K/0 S Series are combined in this package.
APPENDIX A DEVELOPMENT TOOLS 372 User’s Manual U15331EJ4V1UD Remark ×××× in the part number differs depending on the host machine and operating system to be used. µ S ×××× RA78K0S µ S ×××× CC78K0S ×××× Host Machine OS Supply Medium AB13 Japanese Windows 3.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 373 A.5 Debugging Tools (Hardw are) IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and so ftware of an application system using the 78K/0S Series. Can be used with the integrated the debugger ID78K0S-NS.
APPENDIX A DEVELOPMENT TOOLS 374 User’s Manual U15331EJ4V1UD A.6 Debugging Tools (Softw are) This debugger supports the in-circuit emulat ors IE-78K0S-NS and IE-78K0S-NS-A for the 78K/0S Series.
User’s Manual U15331EJ4V1UD 375 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figures B-1 to B-6 show the conditions w hen connecti ng the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and c onsider the shape of parts to be mounted on the target system w hen designing a system.
APPENDIX B NO TES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 376 Figure B-2. Connection Conditions of Targe t System (When NP-80GC-TQ Is Use d) Emulation probe NP-80GC-TQ Emulation board IE-789488-NS-EM1 24.8 mm 25 mm 40 mm 34 mm T arget system 21 mm Pin 1 11 mm 21 mm Conv ersion adapter TGC-080SBP Figure B-3.
APPENDIX B NO TES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 377 (2) NP-80GK, NP-H80GK-TQ Figure B-4. Distance Betw een In-Circuit Emulator and Conv ersion Adapter (8 0GK) 170 mm Note In-ci.
APPENDIX B NO TES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 378 Figure B-5. Connection Conditions of Targe t System (When NP-80GK Is Use d) Emulation probe NP-80GK Emulation board IE-789488-NS-EM1 23 mm 40 mm 34 mm T arget system 16 mm Pin 1 11 mm 25 mm 16 mm Conv ersion adapter TGK-080SDP Figure B-6.
379 User’s Manual U15331EJ4V1UD APPENDIX C REGISTER INDEX C.1 Register Index (Register Names in Alphabetic Order) [A ] A/D conversion result register 0 (ADCR L0) ...................................................................................... .
APPENDIX C REG ISTER INDEX 380 User’s Manual U15331EJ4V1UD [L] LCD clock control r egister 0 (LCDC0 ) ........................................................................................... ....................... 256 LCD display mode r egister 0 (LCDM 0) .
APPENDIX C REG ISTER INDEX User’s Manual U15331EJ4V1UD 381 Remote controller receive end wi dth select regi ster (R MER) ..................................................................... .......... 276 Remote controller receiv e shift rece ive (R MSR).
APPENDIX C REG ISTER INDEX 382 User’s Manual U15331EJ4V1UD C.2 Register Index (Register Symbols Alphabetic Order) [A ] ADCRL0: A/D conversion result regi ster 0 ....................................................................................... .
APPENDIX C REG ISTER INDEX User’s Manual U15331EJ4V1UD 383 MUL0H: 16-bit multiplication re sult storage r egister H ......................................................................... ........... 267 MUL0L: 16-bit multiplication re sult storage r egister L.
APPENDIX C REG ISTER INDEX 384 User’s Manual U15331EJ4V1UD SIO1A0: Serial I/O sh ift regist er 1A0 .......................................................................................... ..................... 218 SSCK: Subclock sele ction r egist er .
User’s Manual U15331EJ4V1UD 385 APPENDIX D REVISION HISTORY The following table show s the revision history up to this editi on. The “Applied to:” column indicates the chapters of each edition in which the revision w as applied.
APPENDIX D REVISIO N HISTORY User’s Manual U15331EJ4V1UD 386 (2/4) Edition Major Revision from Previous Edition Applied to: Addition of descriptions of µ PD789489, 78F9489 (under development) • K.
APPENDIX D REVISIO N HISTORY User’s Manual U15331EJ4V1UD 387 (3/4) Edition Major Revision from Previous Edition Applied to: Change of descriptions of µ PD789489, 78F9489 • Change of status from under development to development completed • Change of the subseries name to “ µ PD789489 subseries” Throughout Update of 1.
APPENDIX D REVISIO N HISTORY User’s Manual U15331EJ4V1UD 388 (4/4) Edition Major Revision from Previous Edition Applied to: Modification of descriptions in Figure 12-4.
An important point after buying a device NEC PD789488 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought NEC PD789488 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data NEC PD789488 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, NEC PD789488 you will learn all the available features of the product, as well as information on its operation. The information that you get NEC PD789488 will certainly help you make a decision on the purchase.
If you already are a holder of NEC PD789488, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime NEC PD789488.
However, one of the most important roles played by the user manual is to help in solving problems with NEC PD789488. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device NEC PD789488 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
