Instruction/ maintenance manual of the product 1320Xf/1160Xf NEC
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NEC Enterprise Server NEC Express5800/1000 Series N E C E x p r e s s 5 8 0 0 / 1 0 0 0 T e c h n o l o g y G u i d e V o l .1 P o w e r e d b y t h e D u a l - C o r e I n t e l ® Itanium ® Process.
2 I n t o d a y ’ s f a s t - p a c e d b u s i n e s s e n v i r o n m e n t , a l l e n t e r p r i s e s , f r o m t h e w o r l d ’ s l a r g e s t c o m p a n i e s t o t h e s m a l l e s t d e p e n d o n I T.
3 Mainframe-class RAS features Reliability / Availability • Dual-Core Intel ® Itanium ® processor: Error handling of hardwar e and operating system through Machine Check Architecture (MCA) • Mem.
4 Features for performance improvement Dual-Core Intel ® Itanium ® processor and high-speed inter/intra Cell cache-to-cache data transfer At the heart of the Express5800/1000 series server is the 64-bit Dual-Core Intel ® Itanium ® processor , redesigned for even faster processing of larger data sets.
5 VLC Architectur e High-speed / low latency Intra-Cell cache-to-cache data transfer The Express5800/1000 series server implements the VLC architecture, which allows for low latency cache-to-cache data transfer between multiple CPUs within a cell.
6 RAS Design Philosophy Realization of a mainframe-class continuous operation through the pursuit of reliability and availability in a single server construct Mainframe-class RAS Features Clustering D.
7 Memory Mirroring Continuous operation even in the event of a non-correctable memory error The Express5800/1000 series server supports high-level memory RAS features to ensure that the server can rapidly detect memory errors, reduce multi-bit errors and continually operate even in the event of memory chip or memory controller failures.
8 Mainframe-class RAS Features Highly Available Center Plane System restoration after the replacement of a failed crossbar card no longer requires a planned system downtime The Express5800/1000 series server has separated and modularized the crossbar controller which or dinarily would reside on the system center plane.
9 Modularization, redundancy and domain segmentation of the system clock Minimizes downtime, and avoids multi-partition shutdown due to clock failure Diagnostics of the error detection circuits Substantial strengthening of data integrity Main data paths of the A 3 chipset on the Expr ess5800/1000 series servers have been protected by ECC.
10 Mainframe-class RAS Features Enhanced error detection of the high-speed interconnect Intricate error handling through multi-bit error detection and resending of error ed data Since higher speed int.
11 Flexibility and Operability Pursuit of flexibility and operability in a system — Flexible resource virtualization using floating I/O for improved operability Investment Protection Smooth migrat.
n NEC Express5800/1000 series Specifications Model 1080Rf 1160Xf 1320Xf CPU Processor Dual Core Intel ® Itanium ® processor Intel ® Processor Number 9120N 9140N 9150N 9120N 9140N 9150N 9120N 9140N 9150N Clock frequency 1.42GHz 1.60GHz 1.60GHz 1.42GHz 1.
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