Instruction/ maintenance manual of the product 88F6281 Marvel Group
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Marvell. Moving Forward Faster Doc. No. MV -S104859-U0, Rev . E December 2, 2008, Preliminary Document Classification: Proprietary Information Cover 88F6281 Integrated Controller Hardware Specificatio.
Document Conventions Note: Provides related infor mation or information of special impor tance. Caution: Indicates potential damage to hardwar e or software, or loss of data. Wa r n i n g : Indicates a risk of personal injury . Document St atus Doc S tatus: Preliminary T e chnical Publication: 0.
88F6281 Integrated Controller Hardware Specifications Copyright © 2008 Marvell Doc. No. MV -S104859-U0 Rev . E December 2, 2008, Preliminary Document Classification: Prop rietary Information Page 3 PRODUCT OVERVIEW The Marve ll ® 88F6281 is a high-performance, highly integrated controlle r .
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 4 Document Classification: Proprietary Information December 2, 2008, Preliminary FEATURES The 88F6281 includes: • High-performance CPU core, running at up to 1.
Features Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 5 • Priority queuing on receive based on Desti.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 6 Document Classification: Proprietary Information December 2, 2008, Preliminary I 2 S-specific features • Sample rates of 44.
Features Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 7 x16 x8 TDM Usage Mod el Exam p le: VoIP Gateway PCI Expre ss Mini Ca rd W i-Fi SD Card USB Host SATA Port Multip lier HDD Audio A/D – D/A GbE PHY FXS FXO NAND Flash SPI Flash (op.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 8 Document Classification: Proprietary Information December 2, 2008, Preliminary T able of Content s Product Overview .............. ............. ........
T able of Content s Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 9 8 Electrical Specifications (Pre liminary) ..... ................. ............. .....
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 10 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary List of T a bles 1 Pin and Signal Descriptions ........... ............
List of T ables Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 1 7 JTAG Interface .............. ............. ................ ............. ...........
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 12 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary 10 Package ............... ............. ................ .............
List of Figures Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 13 List of Figures 1 Pin and Signal Descriptions ........... ................ ............. .
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 14 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary Figure 28: Inter-IC Sound (I2S) T est Circuit ............ ............
Preface About this Document Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 15 Preface About this Document This datasheet provides th e hardware specificat ions for the 88F6281 integrated con troller .
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 16 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 – The ESP T riple DES T ransform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication).
Pin and Signal Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 17 1 Pin and Signal Descripti.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 18 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary 1.1 Pin Logic Figure 1: 88F6281 Pin Logic Diagram NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII T ransmit Clock.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 19 1.2 Pin Descriptions This section details all the pins for the different interfaces prov idin g a functional description of each pin and pi n at tributes.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 20 Document Classification: Proprietary Information December 2, 2008, Preliminary RTC RT C_ NAND Flash N.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 21 1.2.1 Power Supply Pins T able 3 p rovides the voltage levels for the various interface pin s.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 22 Document Classification: Proprietary Information December 2, 2008, Preliminary PEX_A V DD I Power PCI Express PHY quiet power su pply 1.8V NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Des ign Guide for power supply filteri ng recommendations.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 23 1.2.2 Miscellaneous Pin Assignment The Miscellaneou s signal list contains clock and reset, test, and relate d signals.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 24 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 25 M_ST A RTBURST O SSTL VDD_M St art Burst 88F6281 indication of st arting a burst read transacti on.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 26 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 27 1.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 28 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.6 Gigabit Ethernet Port Interface Pin Assignment s For additional information about the Gi gabit Ethernet port pin functions refer to Section 4.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 29 GE_RXD[3:0] I CMOS VDD_GE_A RGMII Receive Data Contains t he recei ve data nibble input s that are synchronous to GE_RXCLK input rising/falli ng edge.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 30 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP[27:24]/ GE1[7:4] I CMOS V DD_GE_B RGMII Receive Dat a Contains t he recei ve data nibble input s that are synchronous to GE_RXCLK input rising/falli ng edge.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 31 MPP[32]/GE1[12] I/O CMOS VDD_GE_B RGMII T ransmit Clock RGMII transmit refere nce output clock for GE_TXD[3:0] and GE_TXCTL Provides 125 MHz, 25 MHz or 2.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 32 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 33 1.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 34 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 35 1.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 36 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 37 1.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 38 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.13 T wo-Wire Serial Interface (TWSI) Interface Note All of the TWSI signals are mu ltiplexed on the MPP pi ns (see Section 4, Pin Mul tiplexing, on page 51 ).
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 39 1.2.14 UART Interface Note All of the UART signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexi ng, on page 51 ).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 40 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.15 Audio (S/PDIF / I 2 S) Interface Note All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 41 1.2.16 Serial Peripheral Interface (SPI) Interface Note All of the SPI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 42 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.17 Secure Digit al Input/Output (SDIO) Interface Note All of the SDIO signals are mult iplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 43 1.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 44 Document Classification: Proprietary Information December 2, 2008, Preliminary TDM_SPI_MOSI O CMOS VDDO / VDD_GE_B Serial SP I data from the host to the codec for re gister access.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 45 1.2.19 T ransport Stream (TS) Interface Note All of the TS signals are multiplexed on the MPP pin s (see Section 4, Pin Multiplexing, on page 51 ).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 46 Document Classification: Proprietary Information December 2, 2008, Preliminary TSMP[7] I/O CMOS VDDO/ VDD_GE_B • Parallel Mode: TS0_DA T A[2 ]: Port0 T S Data bit 2 • Serial Mode: TS1_SYNC: P ort1 Sync/Fram e S tart Indicator or Packet Clock.
Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 47 1.2.20 Precise Timing Protocol (PTP) Interface Note All of the PTP si gnals are multiplexed o n the MPP pin s (see Section 4, Pin Multiplex ing, on page 51 ).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 48 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.3 Internal Pull-up and Pull-down Pins Some pins of the device package are connected to internal pull-up and pul l-down resistor s.
Unused Interface S trapping Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 49 2 Unused Interface S trapping T able 2 4 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 50 Document Classification: Proprietary Information December 2, 2008, Preliminary 3 88F6281 Pin Map and Pin List The 88F6281 pin list is provided as an Excel file attachment.
Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 51 4 Pin Multiplexing 4.1 Multi-Purpose Pins Functional Summary The 88F6281 device contains 50 Multi-Purpose Pins (MPP).
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 52 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP pins can be assigned to different functionalit ies through the MPP Co ntrol register , as shown in T able 25 .
Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 53.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 54 Document Classification: Proprietary Information December 2, 2008, Preliminary T able 26: MPP Functio.
Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 55.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 56 Document Classification: Proprietary Information December 2, 2008, Preliminary Note For MPPs assi.
Pin Multiplexing Gigabit Ethern et (GbE) Pi ns Multiplexing on MPP Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 57 4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP The 88F6281 has 14 dedicated pins for its GbE port.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 58 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP_34 / GE1[14] NA MI.
Pin Multiplexing TSMP (TS Multiplexing Pins) on MPP Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 59 4.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 60 Document Classification: Proprietary Information December 2, 2008, Preliminary 5 Clocking T able 29 lists the clocks in the 88F6281.
Clocking Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 61 The following table lists the supported combinations of the CPU_C LK Frequ ency select, CPU_CLK to DDR CLK ra tio, and to CPU_CLK to CPU L2 clock ratio (see Section 6.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 62 Document Classification: Proprietary Information December 2, 2008, Preliminary 5.1 S pread Spectrum Clock Generator (SSCG) The SSCG (S pread S pectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input.
System Power Up/Down and Reset Setting s Power-Up/Down Seque nce Requirements Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Propriet.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 64 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 2: Power-Up Sequence Example 6.
System Power Up/Down and Reset Setting s Hardware Reset Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 65 6.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 66 Document Classification: Proprietary Information December 2, 2008, Preliminary 6.3 PCI Express Reset 6.3.1 PCI Express Root Complex Reset As a Root Complex, the d evice may generate a Hot Reset to the PCI Express port.
System Power Up/Down and Reset Setting s Pins Sample Configurat ion Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 67 In each row of Ta b l e 3 2 , the order of the pins is from MSb to LSb (e.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 68 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP[33], NF_ALE, NF_REn, NF_CLE CPU_CLK to DDR CLK Ratio 0x0–0x3 = Reserved 0x4 = 3:1 0x5 = Reserved 0x6 = 4:1 0x7 = 4.
System Power Up/Down and Reset Setting s Pins Sample Configurat ion Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Inform.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 70 Document Classification: Proprietary Information December 2, 2008, Preliminary 6.6 Serial ROM Initialization The device supports initialization of ALL of its inte rnal and configuration re g isters through the TWSI master interfac e.
System Power Up/Down and Reset Setting s Boot Sequence Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 71 The serial ROM initialization logic reads eight byte s at a time.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 72 Document Classification: Proprietary Information December 2, 2008, Preliminary Upon completing the ab.
JT AG Inte rfa ce T AP Controller Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 73 7 JT AG Interface T o enable board testing, the devi ce supports a te st mode operatio n through its JT AG boundary scan interface.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 74 Document Classification: Proprietary Information December 2, 2008, Preliminary 7.
Electrical Specifications (Preliminary) Absolute Maximum Ratings Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 75 8 Electrical S pecifications (Preliminary) 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 76 Document Classification: Proprietary Information December 2, 2008, Preliminary RTC_A VDD -0.
Electrical Specifications (Preliminary) Recommended Op erating Cond iti ons Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 77 8.2 Recommended Operating Conditions T able 36: Recommended Operating Conditions Parameter Min Ty p Max Units Comment s VDD 0.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 78 Document Classification: Proprietary Information December 2, 2008, Preliminary XT AL_A VDD 1.7 1.8 1.9 V Analog supply for: Internal clock i nverter for cryst al support and curre nt source for SA T A and USB PHYs RTC_A VDD 1.
Electrical Specifications (Preliminary) Thermal Power Dissipation Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 79 8.3 Thermal Power Dissip ation The purpose of the Thermal Power Dissipation table is to support system engineering in ther ma l design.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 80 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.4 Current Consumption The purpose of the Current Consum ption table is to support board power design and power module selection.
Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 81 8.5 DC Electrical S pecifications 8.5.1 General 3.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 82 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.5.2 RGMII, SMI and REF_CLK_XI N 1.8V (CMOS) DC Electrical S pecifications In the following t able, for the RGMII inte rface, VDDIO means the VDD_GE_A power rail.
Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 83 8.5.3 SDRAM DDR2 Interface DC Electrical Specifications In the following table, VREF is VDD_ M/2 and VDDIO means the VDD_M pow er rail.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 84 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.5.4 T wo-Wire Serial Interface (TWSI) 3.3V DC Electrical S pecifications In the following table, VDDIO means the VDDO power rail.
Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 85 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 86 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6 AC Electrical S pecifications See Section 8.7, Differential Interface Elec trical Ch aracteristics, o n page 1 18 for differential interface specifications.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 87 Notes: 1. Slew rate is d efined from 20% to 80% of the reference clock signal.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 88 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information P.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 90 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 91 8.6.2.3 SDRAM DDR2 In terface T est Circuit Figure 5: SDRAM DDR2 Interface T est Circuit 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 92 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 7: SDRAM DDR2 I.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 93 8.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 94 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 95 8.6.4 Gigabit Media Independen t Interface (GMII) AC T iming 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 96 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 97 8.6.5 Media Independent Interfac e/Marvell Media Independent Interface (MII/MMII) AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 98 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 16: MII/MMII MA.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 99 8.6.6 Serial Management In terface (SMI) AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 100 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 18: MDC Master Mode T est Circuit 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 101 8.6.7 JT AG Interface AC Timing 8.6.7.1 JT AG Interface AC Timing T able T able 54: JT AG Interface AC Timing T able 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 102 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 103 8.6.8 T wo-Wire Serial Interface (TWSI) AC T iming 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 104 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 105 8.6.9 Sony/Philip s Digit al Inter connect Format (S/PDIF) AC Ti m i n g 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 106 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 107 8.6.10 Inter-IC Sound Interface (I 2 S) AC T iming 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 108 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 109 8.6.1 1 Time Division Multiplexi ng (TDM) Interface AC T iming 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 10 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Cl assification: Proprietary Information Page 1 1 1 8.6.12 Serial Peripheral Interface (SPI) AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 12 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 13 8.6.13 Secure Digit al Input/Outp ut (SDIO) Interface AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 14 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 15 8.6.14 T ransport Stream (T S) Interface AC Timing 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 16 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.14.2 T ransport S tream Interface T est Circuit Figure 40: T ran sp ort Stream Interface T est Ci rcuit 8.
Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information P.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 18 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Prop.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 120 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 121 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 122 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 123 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 124 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.
Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 125 8.7.4 USB Electrical Characteristics 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 126 Document Classification: Proprietary Information December 2, 2008, Preliminary T able 70: USB Full Speed Driver and Receiver Characteristics Mi n Ma x Baud R ate BR M bps - Baud rate toleranc e Bppm - 2500.
Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 127 T able 71: USB High Speed Driver and Receiver Charac teristics 8.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 128 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 45: High Sp ee.
Thermal Dat a (Preliminary) Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 129 9 Thermal Dat a (Preliminary) T able 7 2 provides the p ackage thermal data for the de vice.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 130 Document Classification: Proprietary Information December 2, 2008, Preliminary 10 Package This section provides the 88F6281 package drawing an d dimensions.
Package Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 131 T able 73: HSBGA 288-pin Package Dimensions Symbol Common Dime nsion (in millimeters) Package HSBGA Body size X D 19.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 132 Document Classification: Proprietary Information December 2, 2008, Preliminary 11 Part Order Numbering/Package Marking 1 1 .1 Part Order Numbering Figure 48 shows the part order nu mbering scheme for the 88F6281.
Part Order Numberi ng/Package Markin g Package Marking Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 133 1 1 .2 Package Marking Figure 49 shows a samp le Commercial package marking a nd pin 1 location for the 88F6281.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 134 Document Classification: Proprietary Information December 2, 2008, Preliminary A Revision History T able 75: Revision Histor y Revision Date Comment s E Dec ember 2 , 2008 Revision 1.
Revision History Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 135 17.
88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 136 Document Classification: Proprietary Information December 2, 2008, Preliminary 17. In Section 4.1, Multi-Purpose Pins Functional Summary , on p age 51 : • Changed all references to MPP[0 ] and MPP[1 1] from GPI to GPIO.
Revision History Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 137 38.
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Marvell. Moving Forw ard Faster Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.
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