Instruction/ maintenance manual of the product BX80637G2010 Intel
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Document Number: 326764 -008 Desktop 3rd Generation Intel ® Core™ Processor Family, Desktop Intel ® Pentium ® Processor Family, and Desktop Intel ® Celeron ® Processor Family Datasheet – .
2 Datasheet, Volume 1 INFORMA TION IN THIS DOCUMENT IS PROV IDED IN CONNECTION WITH INTEL PRODUCTS . NO LICENSE, EXPRESS OR IMPLIED , BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
Datasheet, Volume 1 3 Contents 1I n t r o d u c t i o n ......... ......... .......... ........... ........ ........... .......... ......... .......... ......... .......... .... 9 1.1 Processor Feature De tails .......... .......... ............. .
4 Datasheet, Volume 1 2.4.1 3D and Vide o Engines for Graphics P rocessing ..................... ........... .......... .. 33 2.4.1.1 3D Engine Ex ecution Units ..... ........... ........... ........ ........... .......... .. 33 2.4.1.2 3D Pipeline ..
Datasheet, Volume 1 5 4.2.4 Core C-states ........ .. .. ........... ........ .. ... .. ........ .. .. .. ......... .. .. .. ......... .. .. .. ...... 52 4.2.4.1 Core C0 State...... .......... ........... .......... ........... ........ ..........
6 Datasheet, Volume 1 7.7 Signal Groups .... ........... .......... ........... .......... ........... ........... ........ ........... .......... .. 80 7.8 Test Access Port (TAP) Connection ............ .. .. .. ... .......... .. ........... ........
Datasheet, Volume 1 7 6-2 Memory Channe l A Signals ............. .......... ........... .......... ........... .......... ......... .......... .. 66 6-3 Memory Channe l B Signals ............. .......... ........... .......... ......... .........
8 Datasheet, Volume 1 Revision History § § Revision Number Description Revision Date 001 • Initial release April 2012 002 • Added Desktop 3rd Generation Intel ® Core™ i5 -3470T , i5-347 0, i5-3470S, i5-3475S, i5-3570, i5-3570S proc essors June 2012 003 • Updated Section 1.
Datasheet, Volume 1 9 Introduction 1 Introduction The Desktop 3rd Generation Intel ® Core™ processor family , Desktop Intel ® Pe nt i u m ® processor family , and Desktop Intel ® Celeron ® processor family are the next generation of 64-bit, multi-core processors built on 22-nanometer process technology .
Introduction 10 Datasheet, Volume 1 Figure 1-1. Desktop Processor Platform I n t e l ® F l e x i b l e D i s p l a y I n t e r f a c e DMI2 x4 Discrete Graphics (PEG) Analog CRT Giga bit Network Connec ti on USB 2.0 / USB 3.0 1 Intel ® HD Audio FWH Super I/O Seria l ATA DDR3 PCI Express* 3 .
Datasheet, Volume 1 11 Introduction 1.1 Processor Feature Details • Four or two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction / data second-level cache (L2) for each core • Up to 8-MB shared instruction / data thir d-level cache (L3), shared among all cores 1.
Introduction 12 Datasheet, Volume 1 • Support memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L DIMMs/DRAMs running at 1.5 V • The type of the DIMM modules supported by the processor i s .
Datasheet, Volume 1 13 Introduction to transmit data across this interface. This also does not account for packet overhead and link maintenance. • Maximum theoretical bandwidth on the interface of 8 GB/s in each direction simultaneously , for an aggregate of 16 GB/s when x16 Gen 2 • Gen 3 raw bit -rate on the data pins of 8.
Introduction 14 Datasheet, Volume 1 1.2.3 Direct Media Interface (DMI) • DMI 2.0 sup port • Four lanes in each direction • 5 GT/s point-to-point DMI interface to PCH is supported • Raw bit-r ate on the data pins of 5.
Datasheet, Volume 1 15 Introduction • DirectX* Video Acceleration (DXV A) support for accelerating video processing — Full AVC/VC1/MPEG2 HW Decod e • Advanced Scheduler 2.0, 1.0, XPDM supp ort • Windows* 7, Wi ndows* XP , OSX, Linu x OS Support • DirectX* 11, Dire ctX* 10.
Introduction 16 Datasheet, Volume 1 1.3.5 Direct Media Interface (DMI) • L0s and L1 ASPM power management capa bility 1.3.6 Processor Graphics Controller (GT) •I n t e l ® Rapid Memory Power Mana.
Datasheet, Volume 1 17 Introduction 1.5 Package The processor socket type is noted as LGA 1155. The p ackage is a 37.5 x 37.5 mm Flip Chip Land Grid Array (FCLGA 1155).
Introduction 18 Datasheet, Volume 1 1.6 Processor Compatibility The Desktop 3rd Generation Intel ® Core™ processor family , Desktop Intel ® Pent i u m ® processor family , Desktop Intel ® Celero.
Datasheet, Volume 1 19 Introduction 1.7 Terminology Table 1-2. Terminology (Sheet 1 of 3) Term Description ACPI Advanced C onfigurat ion and Power Interface ADB Automatic Display Brightness APD Ac.
Introduction 20 Datasheet, Volume 1 Intel ® VT -d Intel ® Virtualization T echnology (Intel ® VT) for D irecte d I/O. In tel VT -d is a ha rdwar e assist , unde r syste m softwa re (Vi rtual M ach ine Manager or operating sys t em) c ontro l, for enabling I/O device virtualization.
Datasheet, Volume 1 21 Introduction Storage Cond itions A non-oper ational state. The processor ma y be installed in a platform, in a tr ay , or loose.
Introduction 22 Datasheet, Volume 1 1.8 Related Documents Note: Contact your Intel representative for the latest revision of this item. § § Table 1-3.
Datasheet, Volume 1 23 Interfaces 2 Interfaces This chapter describes the interfac es supported by the processor . 2.1 System Memory Interface 2.1.1 System Memory Tec hnology Supported The Integrated Memory Controller (IMC) supports DDR3 / DDR3L protocols with two independent, 64-bit wid e channel s, each accessing one or two DIMMs.
Interfaces 24 Datasheet, Volume 1 Note: 1. DIMM module support is based on av ailability and is subject to change. Note: 1. System memory configurations are based on av ailability and are subject to change.
Datasheet, Volume 1 25 Interfaces Note: 1. System memory timing support is based on availability and is s ubject to change. 2.1.3 System Memory Orga nization Modes The IMC supports two memory organization modes, single-channel and dual-chann el.
Interfaces 26 Datasheet, Volume 1 2.1.3.2.1 Dual-Channel Sy mmetric Mode Dual-Chann el Symmetric mode, also kn own as interleaved mod e, provides maxi m um performance on real world applications. Addresses are ping-ponged between the channels after each cache line (6 4-byte boun dary).
Datasheet, Volume 1 27 Interfaces 2.1.5 Technology Enhancements of Intel ® Fast Mem ory Access (Intel ® FMA) The following sections describe the Just-i n - Time Scheduling, Command Ov erlap, and Out-of -Order Scheduling Intel FMA technology enhancements.
Interfaces 28 Datasheet, Volume 1 2.2 PCI Express* Interface This section describes the PCI Express interface capabilities of the processor . See the PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers is depen d ent on the platform.
Datasheet, Volume 1 29 Interfaces 2.2.1.1 Transaction Laye r The upper layer of the PCI Express* architecture is the T ransaction Layer . The T ransaction Layer's primary responsibilit y is the assembly and disassembly of T ransaction Layer P ackets (TLPs).
Interfaces 30 Datasheet, Volume 1 2.2.2 PCI Express* Co nfiguration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. PCI Express extends the configuration spac e to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification .
Datasheet, Volume 1 31 Interfaces 2.2.3 PCI Express* Port The PCI Express interface on the processor is a single, 16-lane (x16) port that can also be configured at narrower widths. The PCI Express port is being designed to be compliant with the PCI Express Base Specification, Revision 3.
Interfaces 32 Datasheet, Volume 1 2.3 Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI 2.0 is supported. Note: Only DMI x4 configuration is supported. 2.3.1 DMI Error Flow DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT , or GPE.
Datasheet, Volume 1 33 Interfaces 2.4 Processor Graphics Controller (GT) New Graphics Engine Architecture includes 3D compute elements, Multi-format hardware assisted decode/encode pipeline, and Mid-Level Cache (ML C) for superior high defini tion playback, video quality , and improve d 3D performance and M edia.
Interfaces 34 Datasheet, Volume 1 2.4.1.2 3D Pipeline 2.4.1.2.1 Vertex Fetch (VF) Stage The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*. 2.4.1.2.2 Vertex Shad er (VS) Stage The VS stage performs shading of vertices output by the VF f unction.
Datasheet, Volume 1 35 Interfaces 2.4.1.4 2D Engine The Display Engine fetches the raw data from the memory , puts the data into a stream, converts the data into r aw pixels, organizes pixels into images, blends diff erent planes into a single image, encodes the data, and sends the data out to the display device.
Interfaces 36 Datasheet, Volume 1 2.4.2 Processor Graphics Display The Processor Graphics controller display pipe can be broken down into three components: •D i s p l a y P l a n e s • Display P ipes • DisplayPort* and Intel ® FDI 2.
Datasheet, Volume 1 37 Interfaces 2.4.2.2 Display Pipes The display pipe blends and synchronizes pixe l data received from one or more display planes and adds the timing of the displa y output device upon which the image is displayed. The display pipes A, B, and C operate independently of each other at the rate of 1 pixel per clock.
Interfaces 38 Datasheet, Volume 1 2.5 Platform Environment Control Interface (PECI) The PECI is a one-wire interface that pr ovides a communication channel between a PECI client (processor) and a PECI master . The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master .
Datasheet, Volume 1 39 Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor .
Technologies 40 Datasheet, Volume 1 3.1.2 Intel ® Virtualization Technology (Intel ® VT) for IA-32, Intel ® 64 and Intel ® Architecture (Intel ® VT-x) Features The processor core supports.
Datasheet, Volume 1 41 Technologies 3.1.4 Intel ® Virtualization Technology (Intel ® VT) for Directed I/O (Intel ® VT-d) Features The processor supports the following Intel VT -d features: • Memory controller and processor graphics comply with Intel ® VT -d 1.
Technologies 42 Datasheet, Volume 1 3.2 Intel ® Trusted Execution Technology (Intel ® TXT) Intel T rusted Execution T echnology (Intel TXT) defines platform-level enhancements that provide the building blocks for creating trusted platforms.
Datasheet, Volume 1 43 Technologies 3.4 Intel ® Turbo Boost Technology Intel ® T urbo Boost T echnology is a feature that allows the processor core to opportunistically and automatically run faster than its r ated operating frequency/render clock if it is operating below power , temp erature, and current limits.
Technologies 44 Datasheet, Volume 1 3.5 Intel ® Advanced Vector Extensions (Intel ® AVX) Intel Advanced V ector Extensions (Intel AVX) is the latest expansion of the Intel instruction set. It extends the Intel Stream ing SIMD Extensions (Intel S SE) from 128- bit vectors to 256-bit vectors.
Datasheet, Volume 1 45 Technologies 3.6.3 RDRAND Instruction The processor introduces a software visible r andom number generation mechanism supported by a high quality entropy source. This capability will be made available to programmers through the new RDRAND inst ruction.
Technologies 46 Datasheet, Volume 1 • More efficient MSR interface to access APIC registers. — T o enhance inter-processor and self dire cted interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode.
Datasheet, Volume 1 47 Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Po wer Interface (ACPI) States.
Power Management 48 Datasheet, Volume 1 4.1 Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States 4.1.2 Processor Core / Package Id le States 4.
Datasheet, Volume 1 49 Power Management 4.1.4 PCI Express* Link States 4.1.5 Direct Media Interface (DMI) States 4.1.6 Processor Graphi cs Controller States 4.1.7 Interface State Co mbinations Table 4-4. PCI Express* Link States State Description L0 Full on – Activ e transfer s tate.
Power Management 50 Datasheet, Volume 1 4.2 Processor Core Power Management While executing code, Enhanced Intel SpeedS tep T echnology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operatin g point is defined by ACPI as a P-state.
Datasheet, Volume 1 51 Power Management Entry and exit of the C- States at the thread and core level are shown in Figure 4-3 . While individual threads can request low power C-states, power saving actions only take place once the core C -state is resolved.
Power Management 52 Datasheet, Volume 1 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requestin g low power idle states are through the MWAIT instruction with sub-state hints an d the HL T instruction (for C1 and C1E).
Datasheet, Volume 1 53 Power Management 4.2.4.2 Core C1 / C1E State C1/C1E is a low power state entered when all threads within a core execute a HL T or MW AIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Norm al state or the C1/C1E state.
Power Management 54 Datasheet, Volume 1 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, an d C6 power states. The following is a summary of the general rules for package C -state entry .
Datasheet, Volume 1 55 Power Management 4.2.5.1 Package C0 P ackage C0 is the normal operating state for the processor . The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted perm ission to the processor to go into a low power state.
Power Management 56 Datasheet, Volume 1 4.2.5.3 Pa ckage C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state • The other cores are in a C3 or lo.
Datasheet, Volume 1 57 Power Management 4.3.2 DRAM Power Manageme nt and Initialization The processor implements extensive support for power management on the SDRAM interface. The re are four SD RA M oper ations associated with the Clock Enable (CKE) signals that the SDRAM controller supports.
Power Management 58 Datasheet, Volume 1 It is important to understand that since the power down decision is per r ank, the MC can find a lot of opportunities to pow er down ran ks, even while running memory intensive applications; savings may be significant (up to a few W atts, depending on DDR configuration).
Datasheet, Volume 1 59 Power Management The target behavior is to enter self -refresh for the package C3 and C6 states as long as there are no memory requests to service. 4.3.2.3 Dynamic Power Down Operation Dynamic power do w n of memory is e m ployed during normal oper ation.
Power Management 60 Datasheet, Volume 1 4.4 PCI Express* Power Management • Active power management support using L0s and L1 states. • All inputs and outputs disabled in L2/L3 Ready state.
Datasheet, Volume 1 61 Power Management 4.6.4 Intel ® Smart 2D Display Technology (Intel ® S2DDT) Intel S2DD T reduces display refresh memo ry tr affic by reducing memory reads required for display refresh. P ower consumption is reduce d by less accesses to the IMC.
Power Management 62 Datasheet, Volume 1.
Datasheet, Volume 1 63 Thermal Management 5 Thermal Management For thermal specifications and design guidelines refer to the Desktop 3rd Generation Intel ® Core™ Processor Family, Desktop Intel ® Pentium ® Processor, Desktop Intel ® Celeron ® Processor, and LGA1155 Socket Thermal and Mechanical Specific ations and Design Guidelines.
Thermal Management 64 Datasheet, Volume 1.
Datasheet, Volume 1 65 Signal Description 6 Signal Description This chapter describes the processor signals. They are arr anged in functional groups according to their associated interface or ca tegory . The following notations are used to describe the signal type.
Signal Description 66 Datasheet, Volume 1 6.1 System Memory Interface Signals Table 6-2. Memory Channel A Signals Signal Name Description Direction/ Buffer Type SA_BS[2:0] Bank Select : The se signals define which ban ks are selected within each SDRAM rank.
Datasheet, Volume 1 67 Signal Description 6.2 Memory Reference and Compensation Signals Table 6-3. Memory Channel B Signals Signal Name Description Direction/ Buffer Type SB_BS[2:0] Bank Select: These signals define whic h banks are selected wi thin each SDRAM ra nk.
Signal Description 68 Datasheet, Volume 1 6.3 Reset and Miscellaneous Signals Note: 1. PCIe* bifurcation support v aries with the processor and PCH SKUs us ed.
Datasheet, Volume 1 69 Signal Description 6.4 PCI Express*-based Interface Signals Note: 1. PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] si gnals are only used for platforms that support 20 PCIe lanes .
Signal Description 70 Datasheet, Volume 1 6.6 Direct Media Interface (DMI) Signals 6.7 Phase Lock Loop (PLL) Signals 6.8 Test Access Points (TAP) Signals Table 6-8.
Datasheet, Volume 1 71 Signal Description 6.9 Error and Thermal Protection Signals Table 6-11. Error and Thermal Protection Signals Signal Name Description Direction/ Buffer Type CA TERR# Catastrophic Error: This signal indicates that the system has experienced a cat astrophic error and cannot continue to operate .
Signal Description 72 Datasheet, Volume 1 6.10 Power Sequencing Signals Table 6-12. Power Sequencing Signals Signal Name Description Direction/ Buffer Type SM_DRAMPWROK SM_DRAMPWROK Proces sor Input : Connects to PCH DRAMPWROK.
Datasheet, Volume 1 73 Signal Description 6.11 Processor Power Signals Note: 1. The VCCSA_VID can toggle at most o nce in 500 uS; The slew rate of VCCSA_VID is 1 V/nS. 6.12 Sense Signals Table 6-13. Processor Power Sig nals Signal Name Description Direction/ Buffer Type VCC Processor core power rail.
Signal Description 74 Datasheet, Volume 1 6.13 Ground and Non-Critical to Function (NCTF) Signals 6.14 Processor Internal Pull-Up / Pull-Down Resistors § § Table 6-15.
Datasheet, Volume 1 75 Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Lands The processor has VC C, VDDQ , VCCPLL, VCCS A, VCCAXG, VCCIO and VS S (ground) inputs for on-chip power distribution.
Electrical Specifications 76 Datasheet, Volume 1 7.3 Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a diffe ren tial clock to gener ate the processor co re ope r ating frequency , memory cont r oller freque ncy , syste m agent freq uencies, an d o t her interna l clocks.
Datasheet, Volume 1 77 Electrical Specifications Table 7-1. VR 12.0 Voltage Identifica tion Definition (S heet 1 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 HEX V CC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 HEX V CC_MAX 0 0 0 0 0 0 0 0 0 0 0.
Electrical Specifications 78 Datasheet, Volume 1 0 0101110 2 E 0 . 47500 1 0 1 0 1 1 1 0 A E 1.11500 0 0101111 2 F 0 . 48000 1 0 1 0 1 1 1 1 A F 1.12000 0 0110000 3 0 0 . 48500 1 0 1 1 0 0 0 0 B 0 1.1 2500 0 0110001 3 1 0 . 49000 1 0 1 1 0 0 0 1 B 1 1.
Datasheet, Volume 1 79 Electrical Specifications 0 1 0 1 1 1 0 1 5 D 0.71000 1 1 0 1 1 1 0 1 D D 1.35000 0 1 0 1 1 1 1 0 5 E 0.71500 1 1 0 1 1 1 1 0 D E 1.35500 0 1 0 1 1 1 1 1 5 F 0.72000 1 1 0 1 1 1 1 1 D F 1.36000 0 1 1 0 0 0 0 0 6 0 0.72500 1 1 1 0 0 0 0 0 E 0 1.
Electrical Specifications 80 Datasheet, Volume 1 7.5 System Agent (SA) V CC VID The V CCSA is configured by the processor outp ut land VCCSA_VID . VCCSA_VID output default logic state is low for 2nd generation and 3rd generation Desktop Core processors, and configures V CCSA to 0.
Datasheet, Volume 1 81 Electrical Specifications Table 7-2. Signal Groups (Sheet 1 of 2) 1 Signal Group Type Signals System Reference Clock Differential CMOS Input BCLK[0], BCLK#[0] DDR3 Reference.
Electrical Specifications 82 Datasheet, Volume 1 Notes: 1. R efer to Chapter 8 for signal description details. 2. SA and SB refer to DDR3 Channe l A and DDR3 C hannel B. 3. The maximum rise/fall time of UNCOREPWRGOOD is 20 ns. 4. PE_TX[3:0]/PE_TX#[3:0] and PE_RX[3:0]/PE_RX#[3:0] signals are only used fo r platforms that support 20 PCIe* lanes.
Datasheet, Volume 1 83 Electrical Specifications 7.9 Storage Conditions Specifications Environmental storage condition limits define the temper ature and relative humidit y to which the device is exposed to while being stored in a moisture barrier bag.
Electrical Specifications 84 Datasheet, Volume 1 7.10 DC Specifications The processor DC specifications in this section are define d at the processor pads, unless noted otherw ise. See Chapter 8 for the processor land listings and Chapter 6 for signal defin itions.
Datasheet, Volume 1 85 Electrical Specifications Notes: 1. Each processor is programmed with a maximum valid voltage identification valu e (VID), which is set at manufacturing and canno t be altered.
Electrical Specifications 86 Datasheet, Volume 1 Notes: 1. VCCSA must be provided using a separ ate voltage source and not be connec ted to V CC . This specification is measure d a t VCCSA_SENSE. 2. ±5% total. Minimum of ±2% DC and 3% AC at th e sense point.
Datasheet, Volume 1 87 Electrical Specifications Notes: 1. V AXG is VID based rail. 2. The V AXG_MIN and V AXG_M AX loadlines represent static and tr ansient limits. 3. The loadlines specify voltage limits at the die meas ured at the V AXG_SENSE and VSSAXG_SENSE lan ds.
Electrical Specifications 88 Datasheet, Volume 1 Notes: 1. Unless otherwise noted, all specifications in this table apply to a ll processor frequencies. 2. V IL is defined as the maximum voltage level at a receiv ing agent that will be interpreted as a logical low valu e.
Datasheet, Volume 1 89 Electrical Specifications Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The V CCIO referred to in these specificat ions refers to instantaneous V CCIO . 3. For V IN between “0” V a nd V CCIO .
Electrical Specifications 90 Datasheet, Volume 1 7.11 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices.
Datasheet, Volume 1 91 Electrical Specifications 7.11.2 DC Characteristics The PECI interface operates at a nominal voltage set by V CCIO . The DC electrical specifications shown in T able 7-10 are used with devices normally oper ating from a V CCIO interface supply .
Electrical Specifications 92 Datasheet, Volume 1.
Datasheet, Volume 1 93 Processor Land and Signal Information 8 Processor Land and Signal Information 8.1 Processor Land Assignments The processor land map is shown in Figure 8-1 . T able 8-1 provides a listing of all processor lands ordered alphabetically by land name.
Processor Land and Signal Information 94 Datasheet, Volume 1 Figure 8-1. LGA Socket Land Map 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4.
Datasheet, Volume 1 95 Processor Land and Signal Information Table 8-1. Processor Land List by Land Name Land Name Land # Buffer Type Dir. BCLK_ITP C40 Di ff Clk I BCLK_ITP# D40 Diff Clk I BCLK[0].
Processor Land and Signal Information 96 Datasheet, Volume 1 PECI J35 Async I/O PEG_COMPI B4 Analog I PEG_ICOMPO B5 Analog I PEG_RCOMPO C4 Analog I PEG_RX[0] B11 PCI Express I PEG_RX[1] D12 PCI Expres.
Datasheet, Volume 1 97 Processor Land and Signal Information RSVD D38 RSVD H7 RSVD H8 RSVD J33 RSVD J34 RSVD J9 RSVD K34 RSVD K9 RSVD L31 RSVD L33 RSVD L34 RSVD L9 RSVD M34 RSVD N33 RSVD N34 RSVD .
Processor Land and Signal Information 98 Datasheet, Volume 1 SA_DQ[44] AR39 DDR3 I/O SA_DQ[45] AR38 DDR3 I/O SA_DQ[46] AN39 DDR3 I/O SA_DQ[47] AN40 DDR3 I/O SA_DQ[48] AL40 DDR3 I/O SA_DQ[49] AL37 DDR3.
Datasheet, Volume 1 99 Processor Land and Signal Information SB_DQ[6] AJ6 DDR3 I/O SB_DQ[7] AJ7 DDR3 I/O SB_DQ[8] AL7 DDR3 I/O SB_DQ[9] AM7 DDR3 I /O SB_DQ[10] AM10 DDR3 I/O SB_DQ[11] AL10 DDR3 I/.
Processor Land and Signal Information 100 Datasheet, Volume 1 SB_MA[10] AN23 DDR3 O SB_MA[11] AU17 DDR3 O SB_MA[12] A T18 DDR3 O SB_MA[13] AR26 DDR3 O SB_MA[14] A Y16 DDR3 O SB_MA[15] AV16 DDR3 O SB_O.
Datasheet, Volume 1 101 Processor Land and Signal Information VCC F18 PWR VCC F19 PWR VCC F21 PWR VCC F22 PWR VCC F24 PWR VCC F25 PWR VCC F27 PWR VCC F28 PWR VCC F30 PWR VCC F31 PWR VCC F32 PWR VC.
Processor Land and Signal Information 102 Datasheet, Volume 1 VCCAXG AB36 PWR VCCAXG AB37 PWR VCCAXG AB38 PWR VCCAXG AB39 PWR VCCAXG AB40 PWR VCCAXG AC33 PWR VCCAXG AC34 PWR VCCAXG AC35 PWR VCCAXG AC3.
Datasheet, Volume 1 103 Processor Land and Signal Information VCCSA J10 PWR VCCSA K10 PWR VCCSA K11 PWR VCCSA L11 PWR VCCSA L12 PWR VCCSA M10 PWR VCCSA M11 PWR VCCSA M12 PWR VCCSA_SENSE T2 An alog.
Processor Land and Signal Information 104 Datasheet, Volume 1 VSS AK28 GND VSS AK31 GND VSS AK32 GND VSS AK33 GND VSS AK34 GND VSS AK35 GND VSS AK36 GND VSS AK37 GND VSS AK4 GND VSS AK40 GND VSS AK5 G.
Datasheet, Volume 1 105 Processor Land and Signal Information VSS AT 2 8 G N D VSS AT 2 9 G N D VSS AT 3 G N D VSS AT 3 0 G N D VSS AT 3 1 G N D VSS AT 3 2 G N D VSS AT 3 3 G N D VSS AT 3 4 G N D .
Processor Land and Signal Information 106 Datasheet, Volume 1 VSS F10 GND VSS F13 GND VSS F14 GND VSS F17 GND VSS F2 GND VSS F20 GND VSS F23 GND VSS F26 GND VSS F29 GND VSS F35 GND VSS F37 GND VSS F39.
Datasheet, Volume 1 107 Processor Land and Signal Information § § VSS R39 GND VSS R8 GND VSS T1 GND VSS T5 GND VSS T6 GND VSS U8 GND VSS V1 GND VSS V2 GND VSS V33 GND VSS V34 GND VSS V35 GND VSS.
Processor Land and Signal Information 108 Datasheet, Volume 1.
Datasheet, Volume 1 109 DDR Data Swizzling 9 DDR Data Swizzling T o achieve better memory performance and timing, Intel Design performed DDR Data pin swizzling that allows a better use of the product across different platform s. Swizzling has no effect on functional oper ation and is invisible to the operating system/software.
DDR Data Swizz ling 110 Datasheet, Volume 1 Table 9-1. DDR Data Swizzling Table – Channel A Land Name Land # MC Land Name SA_DQ[0] AJ3 DQ0 6 SA_DQ[1] AJ4 DQ0 5 SA_DQ[2] AL3 DQ01 SA_DQ[3] AL4 DQ00 SA.
DDR Data Swizzling Datasheet, Volume 1 111 § § Table 9-2. DDR D ata Swizzling table – Ch a nnel B Land Name Land # MC Land Name SB_DQ[0] AG7 DQ04 SB_DQ[1] AG8 DQ05 SB_DQ[2] AJ9 DQ02 SB_DQ[3] A.
DDR Data Swizzling 112 Datasheet, Volume 1.
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