Instruction/ maintenance manual of the product 41210 Intel
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Order N umber: 27 8890-00 3US Intel ® 41210 Serial to Parallel PCI Bridge Developer’s Manual May 2005.
2 Intel ® 41210 Serial to Parallel PCI Bridg e Develo per’s Manua l INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CO NNECTION WITH INT EL ® PRODUCTS.
Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 3 Contents Contents 1 Introduction ... ............. .................... ............. ................... ............. ................... ............. ................. 11 1.1 PCI Express * Interface Features .
4 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 5.3.1 PCI Expre ss* Configu ration Acces s ........... ................... ............. .................... ....... 42 5.3.2 Type 0 Con figuration A ccess from PCI -X Interface .
Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 5 Contents 12.2.6 Offset 0C h: CLS—Cac he-Line Si ze ... ............ ............. .................... ............. .......... 81 12.2.7 Offset 0D h: PMLT—Primary Master Laten cy Timer .
6 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 12.2.53 Offset 108h: ERRUNC_ MSK—PCI E xpress* Uncorrectab le Error Mask ........ ............. ................... ............. ................... ............ 106 12.
Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 7 Contents Tabl es 1 ODT Signal s ....... ............. ................... ............. ................... ............. ............. .......................... .... 14 2 PCI Expres s* Interface P ins .
8 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents 50 Offset 2C h: PMLU32— Prefetchabl e Memory Li mit Upper 32 Bi ts ..... .................... ............. ....... 87 51 Offset 30h: IOBLU1 6—I/ O Base and Lim it Upper 16 Bit s .
Intel ® 41210 Se rial to Parallel P CI Bridge De veloper’s M anual 9 Contents 100 Offset 178 h: PREF CTRL—Prefetch Control Regis ter .. ................... ............. .................... ........ 11 9 101 Offse t 300h: PW RBGT_HD R—Power B udgeting E nhanced Capabilit y Header .
10 Intel ® 41210 S erial to Par allel PCI Bridge De velope r’s Manual Contents Revision History Date Revision Description May 2005 003 Revised T able 1 and T able 9 October 2004 002 Updated PCI Express operation information in Section 1.1 and T able 2 in Section 2 .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 11 Introduction Introduction 1 The Intel ® 41210 S erial to Parallel P CI Brid ge (also cal led the 4 1210 Bridge or th e 41210) integrates two PCI Exp ress*-to-PCI/PCI-X bridg es.
12 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Introduction • Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transactions • T unab.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 13 Signal Description Signal Description 2 The “#” symbol at the en d of a signal name indicat es that the active (asserted) state occurs when the signal is at a low voltag e level.
14 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption T able 1. ODT Signals A_ACK64# B_AC K64# A_AD[63:32] B_AD[63:32] A_CBE#[7:4] B_CBE#[ 7:4] A_DEVSEL# B_DE VSE.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 15 Signal Description 2.2 PCI Express* Interface T able 2. PCI Exp ress* Int erface P ins Signal I/O Description REFCLKp/ REFCLKn.
16 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.3 PC I Bus Interface (T wo Inst ances) Each interface is marked by either the letter “A ” or “B” to signify the interf ace. For example, A_AD refers to th e AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 17 Signal Description A_PERR# B_PERR# I/O Parity Error: PERR# is driven by an external PCI device when it receives data that has a p arity error .
18 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.4 PC I Bus Interface 64-Bit Ext ension (T wo Interfaces) 2.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 19 Signal Description 2.6 Interrupt Interface (T wo Interfaces) This section lists the interrupt interface signals. There are two sets of interrupt signals for the standa rd INT A–IN TD PCI signals.
20 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.7 Reset Strap s The following sign als are used fo r static configura tion.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 21 Signal Description 2.8 SMBus Interface T able 8. SMBus Interface Pins Signal I/O Descriptio n SMBCLK I/OD SMBus Clock: This signal must be p ulled to 3.3 V through an 8.2 K Ω resistor .
22 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption 2.9 Mi scellane ous Pins T able 9 . Miscellaneous Pins Signal I/O Description CFG RST # O Configur a tion Res e t : This signal is asserted low when ever t he bridge goes through a fundemen tal reset (PERST# , RS TIN#, or P CI Express Res et).
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 23 Signal Description 2.10 V o lt age Pins § § T abl e 10. Miscellaneous Pins Signal Number Description RCOMP 1 Analog Compensati on Pin: RCOMP is the analog compensation pin for PCI.
24 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Signal Descri ption THIS P A GE INTEN TI ONALL Y LEFT B LANK.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 25 PCI-X In te rface PCI-X Int er face 3 This section deals with the specifics of the ope r at ion and transaction flow details of the PCI interfaces.
26 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface In summary: • A_RST# and B_RST# are output s from the 41210 . • PCI clocks are actively d riven out from the 41210. • The 41210 d rives X_AD[31 :0], X_BE[ 3:0], and X_P AR low du ring PCI bus reset.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 27 PCI-X In te rface 3.2.2 PCI- X Mode Ta b l e 1 4 lists the transactions that t he 41 210 supports when th e PCI interface is in the PCI-X mode. As a master , the 41210 supp orts the memory write block comma nd for writes that are multip les o f cache-line.
28 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.3 .2 D elayed All memory read transactions are delayed read transactions. When the 412 10 accepts a delayed read request, it samples the add ress, command, and address parity .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 29 PCI-X In te rface 3.2.5 LOCK Cycl es A lock is established when all the following conditions are true: • A PCI Express* device initiates a Memory Read Lock (MRdLk) request to read from a tar get PCI device.
30 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.6 Decodi ng In the PCI mode, the 4 1210 s uppo rt s only the linear i ncrement address mode for bu rst i ng memory transfers (indicated w hen the lowest two address bits are equa l to 0).
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 31 PCI-X In te rface of reordering allowed. Retry is not considered an error co ndition, so ther e is no error logging or report ing don e on a retry .
32 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.2.7.2 PCI-X Mode T ransaction T e rmination • Initiator Disconnect or Satisfactio n of Byte Count As a PCI-.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 33 PCI-X In te rface • T ar get T erminations Initiated by the 41210 The 41210 r esponds with a retry t o PCI-X when one of the followi ng condi tions i s met: — A memory r ead transaction occurs and th e 4121 0 delayed transaction queue is full.
34 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface 3.3 PC I-X Protocol Specifics 3.3.1 Attri bu tes Ta b l e 1 6 describ es h ow the 41210 fills in attribute fields where the PCI -to-PCI Bridg e Specification , Revision 1 .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 35 PCI-X In te rface 3.3.4 S plit T ran sactions • Completer attributes are given in Ta b l e 1 7 .
36 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual PCI-X Int erface For controlling the priority level , there is one bit for each of the PCI REQ# inputs and one bi t for the internal request input . Bit[7] in the control register is for the bridge, bit[5] is for REQ[5]#, bit[4] is for REQ[4]#, and so on.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 37 Power Man a gement Power Management 4 4.1 Hardware-Controlled Active St ate Power Management PCI Expr ess* defines a hardware- i nitiated power manag ement of the PC I Express* Link called active state power management.
38 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Power Man a gement 4.4 Intel ® 41210 Se rial to Parallel PCI Bridge Devic e Powe r Manage men t Each bridge segment supp orts PCI-PM 1.1 device power m anagement states D0, D 3hot, and D3cold.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 39 Power Man a gement T o support the PCI Express* p ower-managemen t event-signaling p rotocol, the 412 10 suppo rts the follow .
40 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Power Man a gement THIS P A GE INTEN TI ONALL Y LEFT B LANK.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 41 Addressing Addressing 5 5.1 Addressable Sp aces within the Int el ® 41210 Serial to Parallel PCI Bridge Befo re di s cus sing.
42 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing 5.2 Sec ondary PCI Devices Devices on the secondary PCI bus can b e co nfigu red as pr ivate d evices a nd h idden fr om BIOS and host software. Devices ar e hidden by inhi biting the assertion of the IDSEL input of the device during configurati on cycle s.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 43 Addressing The extended add ress bits used to acces s the config uration r egion above 25 6 B are all 0s when the access mechanism com p atible with the PCI-to-PCI Bridge Specification , Revisi on 1.
44 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing • T ype 1-to- T yp e 1 Forw a rdi ng : The 41210 pa sses a T ype 1 PCI Express * configuration cycl e as a T ype 1 .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 45 Addressing Instead of hav ing a s econ dary IDSEL# p in, the 4 1210 reserves a device number of 0 for itself.
46 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing The base register consists of an 8 -bit field at configur ati on address 1Ch, and a 1 6-bit field at address 30 h. The top four bits (bits[7:4 ] of address 1Ch) of the 8- bit field define b its[15:12 ] of the I/O base add ress.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 47 Addressing 5.5 Memory Sp ace Access Mechan ism The 41210 s upports 6 4 bits of memory ad dressing on both inter faces. T wo memory windows can be setup for forwarding memo ry transa ct ions from PCI Express*-t o- PCI.
48 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing 5.5.1 Memory-M apped I/O Window Softwa re us es the mem ory-m app e d I/O wind ow to map all non-p refet ch able (in other words, reads that have side ef fects, such as reads to FIFOs, or “read -to-clear” status registers) me mory space into PCI memor y space.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 49 Addressing 5.5.2 Pr efetc h able Memory Wi ndow The prefetchable memo ry base and address reg ist ers, alon g with th eir upper 3 2-bit coun terparts, define an additional ad dress rang e that the 41210 uses to forward accesses.
50 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Addressing When this bit is cleared, the 41210 forwards transactions ad dressing the VGA frame b uffer memory and VGA I/O registers from PCI Express* to PCI when the defined memory and I/O address ranges enable forwarding.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 51 Transac tion Ordering T ransaction Ordering 6 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e or 41210) follows t he producer -consumer model of a standard PCI Expres s*-to-PCI bri dge.
52 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Transaction Or d erin g 6.2 Downst ream T ransactio n Ordering Ta b l e 2 2 lists th e combined set of ordering rules in the downstream path of the 41210.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 53 Interrupt Suppor t Interrupt Support 7 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e.
54 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Interrupt Suppo rt 7.2 I nterru pt Rout ing for Devices behin d a Bridge Given t he legacy i nterrup t shari ng sch eme shown in.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 55 System Management Bus Interface System Management Bus Interface 8 The SMBus interface allows the Intel ® 41210 Serial to Para.
56 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.1 SMB us Commands The 41210 s upports six SMBus co mmands: Sequencing these commands in i tia tes accesses to the internal config uration and memory registers.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 57 System Management Bus Interface 8.2 Initialization Seq uence All configuration read and writes are accomp li shed through SMBus write(s ) followed by an SMBus read (for a r ead co mmand ).
58 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface Figure 6. DWor d Configuration Read Protocol (SMBus Block Write /Block Read, PEC Enabled) Figure 7.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 59 System Management Bus Interface Figure 8. DWord C onfiguration Read Protoc ol (SMBus Block Write/Block Read, PEC Disabled) Figure 9.
60 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.2.2 Configuration Writes Configuration writes are acc omplished throu gh a seri es of SMBus writes. As with reads, a write sequence is used first to initialize the bus number , device, function, and register number for the configuration access.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 61 System Management Bus Interface 8.3 Error Handling The SMBus slave interface handles two types of errors: internal an d PEC. Internal errors can occur when the target function is busy servicing a request from the PCI Express* interface.
62 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual System Management Bus Interface 8.4 SMB us Interface Reset The master has two ways to reset the slave in terface state machin e in the 41210: • The master holds SCL K low fo r 25 ms cum ulative.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 63 Local Initialization Local Initialization 9 The Intel ® 41210 S erial to Parallel PCI Brid ge (called her eafter the 41210 Bridg e or 412 10) includes device-specific regis ters that allow for co ntr ol of the b ridges’ s behavior , both int ernally and externally .
64 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Local Initialization THIS P A GE INTEN TI ONALL Y LEFT B LANK.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 65 Clock and Reset Clock and Reset 10 10.1 Clocking The Intel ® 41210 S erial to Parallel PCI Bridge ( cal led hereafter the 412 10 Bridge or the 41210) always uses the PCI Expr es s* REFCLK as its primary clock input and drives the PCI clock outputs .
66 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Clock and Reset 10.2.1 PERST# R eset Mechanism All the voltage sources in the sy stem are tracked by a s ystem co mponent that as serts the PERST# signal only after all the voltages have been st ab le for some predetermin ed time.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 67 Clock and Reset 10.2.4 Softw are PCI Reset (SBR—Sec ondary Bus Reset) Commonly referred to as the Secondary Bus Reset (SBR), the software PCI reset is initiated by a write to the bridge control register and resets only the particular PCI segment.
68 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Clock and Reset THIS P A GE INTEN TI ONALL Y LEFT B LANK.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 69 Error Hand ling Error Handling 11 For each interface, the I ntel ® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) implements the specifi ed error-l ogg ing and escalation actions a s per the interface rules.
70 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Error Hand ling 11 . 2 . 1 E r r o r Ty p e s PCI errors are class ified into two categories: fatal and non- fatal: • Fatal errors are those that have the potential to cause data corruption.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 71 Error Hand ling 1 1.2.2.2 Sp lit T ermination on PCI- X Interf ace A split-terminatio n error translation o ccurs when a compl.
72 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Error Hand ling 1 1.2.2 .3 Split T ermination on PCI Express* Interf ace Ta b l e 3 1 shows the split-comp letion errors rece i ved on the PCI Express* interf ace and how they translate to PCI-X.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 73 Register Descriptio n Register Description 12 This chapter describes the registers of the Intel ® 41210 Ser ial to Paral le l PCI Bri dge .
74 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2 Con figuration Reg isters The bridge conf i guration space fo llows the standard PCI E xpress*-to-PCI Bridge configur ation space format. Refer to t he PCI Expr ess*-to-PCI Bridge Specification , Rev ision 1.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 75 Register Descriptio n Figure 12. Intel ® 41210 Ser ial to Parallel PCI Bridge Capabilities 0xFFF E x t e n d e d C o n f i g u r a t i o n S p a c e Power B udgeting Capab i lity 0x300 B3174-02 PCI Express Advance d Error Reporting Capab i lity PCI-X Capability PCI-PM 1.
76 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption T able 33. Legacy Configur ation Sp ace Byte Offset Byte Offset DID VID 00h Reserved 80h PSTS PCICMD 04h.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 77 Register Descriptio n T abl e 34. PCI Express* Extended Conf igu ration Sp ace Register Byte Offset EXP AERR_C APID 100 ERRUNC.
78 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.1 Off s et 00h: ID —I de ntif ie r s Contains the vendor and device identifiers for software. 12.2.2 Offset 04h: PCICMD—Command Register This register controls ho w the device beha ves on the primary inter face (PCI Express* ).
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 79 Register Descriptio n 12.2.3 Offset 06h: PSTS—Primary Device St atus For the writable bits in this register, writing a 1 clears the bit. W riting a 0 to the bit has no effect.
80 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.4 Offset 08h: REVID—Revision ID This register is the Revi sion ID Regis ter . 11 R W C 0 b Signal ed T arget A bort (ST A): This bit is set when a completion packet with Completer Abort (CA) s tatus is gen erated on PCI Express*.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 81 Register Descriptio n 12.2.5 Offset 09h: CC—Class Code This register co ntains the class code, s ub-cl ass c ode, and programming inter face for the device. 12.2.6 Offset 0Ch: CLS—Cache-Line Size This register indicates the cache- l ine size of the system.
82 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.9 Offset 18h: BNUM—Bus Num bers This register contains the primary , secondary , and maximum subordinate bu s number regi sters.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 83 Register Descriptio n 12.2.1 1 Offset 1Ch: IOBL—I/O Base and Limit This register defines the base and limit, alig ned to a 4 KB boundary , o f the I/O area of the bridge.
84 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.12 Offset 1Eh: SS TS—Secondary S t atus For the writable bits in this register, w riting 1 to the bit clears the bit. W riting 0 to the bit has no effect .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 85 Register Descriptio n 12.2.13 Offset 20h: MBL—Memory Base and Limit Defines the base and limit, alig ned to a 1 MB bound ary , of the non- prefetchable memory area of the bridge.
86 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.14 Offset 24h: PMBL—Prefetchable Memory Base and Limit This regist er def ines the bas e and limit, aligned to a 1 MB bou ndary , of the prefetchab l e memory area of the bridg e.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 87 Register Descriptio n 12.2.16 Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bit s This regist er defines the upper 32 bits of the prefetchable ad dress base reg i ster .
88 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.20 Offset 3Eh: BCTRL—Bridge Control This regis ter provid es extensions t o the Com mand Reg i ster ( “Offset 04 h: PCICMD—Command Register” on page 78 ) that are specific to a bridge.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 89 Register Descriptio n 5R W 0 b Master A bort Mode ( MAM): This bit controls the bridge’s behavior when a ma ster-abort (or unsupported request) oc curs on either interface.
90 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.21 Offset 40h: BCNF—Bridge Configur ation Register The bridge co ntrol bits speci fic to the Intel ® 41210 Serial to Parallel PCI Bridge are listed in Ta b l e 5 5 .
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 91 Register Descriptio n 12.2.22 Offset 42h: MTT—Mult i-T ransaction T imer This register controls the amou nt of time that the 41210 arbiter allows for a PCI initiator to perform multiple back-to-back transactions on the PCI bus.
92 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.26 Offset 46h: EXP_CAP—PCI Express * Cap ability This register s tor es the v ersion n umb er o f th e capability item an d o t her bas e inf ormation co ntained in the capability structu re.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 93 Register Descriptio n 12.2.28 Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register This regist er stores co mmand bits that cont rol the 41210 behavio r on PCI Exp ress*.
94 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.29 Offset 4Eh: EXP_DSTS—PCI Express* Devi ce S t atus Register This register s t ores information on the PCI Expr es s* device status.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 95 Register Descriptio n 12.2.31 Offset 54h: EXP_LCTL—PCI Express* Link Control Register 14:12 RO 1 10b L0s Exit Laten cy: The .
96 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.32 Offset 56h: EXP_LSTS—PCI Express* Link St atus Register 12.2.33 Offset 5Ch: MSI_CAPID—PCI Express* MSI Cap ability Identifier Note: MSI genera tion is us ed for internal de bugging purposes and does not occur in n ormal oper ation.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 97 Register Descriptio n 12.2.35 Offset 5Eh: MSI_MC—PCI Expre ss* MSI Message Control 12.2.36 Offset 60h: MSI_MA—PCI Expres s* MSI Message Address 12.2.37 Offset 68h: MSI_MD—PCI Expres s* MSI Message Dat a 12.
98 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.39 Offset 6Dh: PM_NXTP—Power Management Next It em Pointer 12.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 99 Register Descriptio n 12.2.41 Offset 70h: PM_PMCSR—Power Management Control/St atus Register 12.2.42 Offset 72h: PM_BSE—Power Management Bri dge Support Extensions 12.2.43 Offset 73h: PM_DA T A—Power Management Dat a Field T able 75.
100 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.44 Offset D8h: PX_CAPID—PCI-X Cap abilities Identifi er This register identifies this item in the capabilities list as a PC I-X register set. 12.2.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 101 Register Descriptio n 12.2.46 Offset DAh: PX_SSTS— PCI-X Secondary St atus This is the PCI-X status register for t he bridge s econdary side.
102 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.47 Offset DCh: PX_BSTS—PCI-X Bridge St atus This register iden tifies PCI-X status register for the bridge primary side.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 103 Register Descriptio n 12.2.49 Offset E4h: PX_DSTC—PCI-X Downst ream S p lit T ransaction Control This register controls the behavior of the 41210 buf fers for forwarding split transactions from PCI Express* to the secondary bus.
104 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.50 Offset FCh: BINIT—Bridge Initialization Register T able 84.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 105 Register Descriptio n 12.2.51 Offset 100h: EXP AERR_CA PID—PCI Expres s* Advanced Error Cap ability Identifier This register stores the PCI Express* extended capability ID value.
106 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.53 Offset 108h: ERRUNC_MSK—PCI Ex p ress* Uncorrect able Error Mask This regi ster con trols the re porting of indiv i dual uncor r ectable errors by device to the host bridge via a PCI Express * error message.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 107 Register Descriptio n 12.2.54 Offset 10Ch: ERRUNC_SEV— PCI Express* Uncorrect able Error S everity This register co ntrols whether an individual uncorr ectable error is repo rted as a fatal erro r.
108 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.55 Offset 1 10h: ERRCOR_STS—PCI E xp ress* Corr ec table Error St atus This regis ter reports the er ror st atus of individual co rrectable error so urces on a PCI Exp ress* device.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 109 Register Descriptio n 12.2.56 Offset 1 14h: ERRCOR_MSK— PCI Express* Correct able Error Mask This register co ntrols the reporting o f indivi dual correctab le errors via ERR_CO R message.
110 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.58 Offset 1 1C–12Bh: HDR_LOG—PCI Express* T r ansaction Header Log This register is t he transaction header log for PCI Ex press* errors. T able 92.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 111 Register Descriptio n 12.2.59 Offset 12Ch: PCIXERRUNC_STS—Uncorrect able PCI-X S t atus Regist er T able 93.
112 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 2R W C S 0 b PCI-X Detected T arget Abort (optional in specificati on): The 41210 sets this bit when i t is the mast er of a reques t transaction on the PCI bus and it receives a target abor t.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 113 Register Descriptio n 12.2.60 Offset 130h: PCIXERRUNC_MSK—Uncorrect able PCI-X Error Mask Regist er This regist er mask s the repo rting of PCI-X un correctable erro rs. There is one mask bit per error .
114 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 2R W C S 0 b P CI -X Detected T arget Abort Mask: (optional in specifi c a t ion) 0 = Not masked 1 = Ma.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 115 Register Descriptio n 12.2.61 Offset 134h: PCIXERRUNC_SEV—Uncorrect able PCI-X Error Seve rity Register This regi ster con trols th e severity of the rep o rting of PC I-X unco rrectable errors.
116 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.62 Offset 13 8h: PCIXERRUNC_PTR—Un c orrectable PCI- X Erro r Pointe r This register points t o the first error t hat occurred.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 117 Register Descriptio n 12.2.63 Offset 13C–14Bh: PCIXHDR_LOG—Uncorrect able PCI-X Error T ransaction Header Log This register is the transaction h ead er log for PC I errors.
118 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.65 Offset 170h: SS R—Strap S tatus Register This register ind i cates the status of various reset strap s in the 41210.
Int el ® 41210 Se rial to Par allel PCI Br idge Developer’s M anual 119 Register Descriptio n 12.2.66 Offset 178h: PREFCTRL—Prefetch Control Register The followi ng regist er contains pref etch parameters for PCI operation.
120 Intel ® 41210 Se rial to Paralle l PCI Bridge Dev eloper’s Manual Reg ist er Descri ption 12.2.67 Offset 300h: PWRBG T_CAPID—Po wer Bud geting Enhanced Capability Header This register defines the capability identifier . 12.2.68 Offset 30 4h: PWRBG T_DSEL— P ower Budgeting Dat a Select Register 12.
An important point after buying a device Intel 41210 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Intel 41210 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Intel 41210 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Intel 41210 you will learn all the available features of the product, as well as information on its operation. The information that you get Intel 41210 will certainly help you make a decision on the purchase.
If you already are a holder of Intel 41210, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Intel 41210.
However, one of the most important roles played by the user manual is to help in solving problems with Intel 41210. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Intel 41210 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
