Instruction/ maintenance manual of the product Sharp ARM720T_LH79520 Altium
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Summary Core Reference CR0162 (v2.0) March 10, 2008 This document provides infor m ation o n Altium Designer's Wishbone wr.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Comput er, is a term that is conventionall y us ed to describe a t.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synony mous with a weaker f eature set – a traditional trade-off. Wi th FPGA-based sy stem designs you can have the best of both worlds.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and per ipherals, each of the 32-bi t proce ssors supported in Altium Designer has a W i shbone OpenBUS-based FPGA core that ' wraps' around the proces sor.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH795 20 in both schematic (left) and OpenBus System (right).
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Pin Description The following pin description is for the proce ssor when used on the schematic. In an OpenB us System, although the s ame signals are present, the abstract nature of the s ystem hides t he pin-level W ishbone interfaces.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Name Type Polarity/Bus size Description Peripheral I/O Interface Signals IO_STB_O O High Strobe signal. When asserted, indicates the start of a valid W ishbone data transfer cycle IO_CYC_O O High Cycle signal.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Name Type Polarity/Bus size Description PER_RESET I Low Reset signal from the LH79520. ARM7_SYS_RESE T O Low Reset signal to the LH79520 (internally co nnected from the RST_I line).
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Speed-critical (or latency-sens itive) parts of an application shou ld also be placed in this memory spac e.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Memory & I/O Management The ARM720T_LH79520 us es 32-bit address buses prov iding a 4GBy te linear addr ess space. All mem ory access is in 32-bit words, which creates a physic al ad dress bus of 30-bits.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_LH79 520's addressable External Static Memory. Figure 6. Peripheral devices mapped into bank 5 (cs5) of the ARM720T_LH79520's addressabl e External Static Memory.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor • cs0 (Bank 0) – 40 00_0000h to 43FF_ FFFFh • cs1 (Bank 1) – 44 00_0000h to 47FF_ FFFFh The bank select signals arrive at the processor's wrapper component in the FPGA on the PER_CS bus.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor The size of the RAM can vary bet ween 1KB and 16MB, dependent on the availabilit y of embed ded block RAM in the target FPGA device used.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave peripher al dev ice, the wait request to the ARM720T is dropped, the processor times out normal ly and the current data transfer cycle is forcibly terminated.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respectivel y with zeroes • for a byte load/store, the processor will sign-ext end from bit 8 • for a half-word load/store, the processor will sign-extend from bit 16.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Hardware Description For detailed information about the hardware and functionalit y of the ARM720T_LH7952 0 process or, inclu.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Wishbone Communications The following sections detail the standard ha ndsh aking that ta kes place when the processor communicat es to a slave p eripheral or memory device connected to the relevant Wishbone interface port.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or memor y controller (Wishbone Slave) in accordance with the standard Wishbone dat a transfer hands haking protocol.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79 52 0 is placed and wired within an FPGA design depends on the method us ed to build that design.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Design Featuring an OpenBus System Figure 11 illustrates identical use of the ARM720T _LH79520 within a design where the main processor system has been defined as an OpenBus System.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Figure 12. Wiring the OpenBus System-based ARM720T_ L H79520 to the physical pins of the FPGA device. For more information on the concepts and workin gs of the OpenBus System, refer to the article AR0144 Stre amlining Processor-based FPGA design w ith the OpenBus Syste m .
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor As the physical ARM720T processor do es no t reside within an FPGA, communications bet ween the host computer a nd t he ARM720T are carried out through the Hard Devices JT AG chain.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor • Download of the embedded c ode targ eted to the discrete ARM720T device. Click on the LH79520 devic e in the Har d Devices chain to access the process flo w re quired to do wnload the embedded soft ware to the processor, as illustrated below.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Figure 16. Starting an embedded code debug session. The debug environment offers the full suite of tools you would ex pect to see in order to effi cientl y debug the embedded code.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Figure 17. Workspace panels offering code- specific information and controls Figure 18.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Figure 19. Accessing debug features from the processor's instrument panel The Nexus Deb ugger button provides acces s to.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720T 32-b it RISC Processor Instruction Set The ARM7TDMI-S core processor – on which the ARM720T is bas ed – is an implementation of t he AR M architecture v4T.
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