Instruction/ maintenance manual of the product MB15F74UV Fujitsu
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DS04-21381-1E FUJITSU SEMICONDUCT OR DA T A S H E E T ASSP Dual S erial Input PLL Frequenc y Synthesiz er MB15F74UV ■ ■ ■ ■ DESCRIPTION The Fujitsu MB15F74UV is a serial input Phase Lock ed Loop (PLL) frequency synthesiz er with a 4000 MHz and a 2000 MHz prescalers.
MB15F74UV 2 (Continued) • Direct pow er saving function : P ower supply current in po wer sa ving mode T yp 0.1 µ A (V CC = 3.0 V, T a = + 25 ° C at 1 system) Max 10 µ A (V CC = 3.0 V at 1 system) • Software selectab le charge pump current : 1.
MB15F74UV 3 ■ ■ ■ ■ PIN DESCRIPTION Pin no. Pin name I/O Descriptions 1G N D Ground pin for OSC input buffer and the shift register circuit. 2f i n IF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling.
MB15F74UV 4 ■ ■ ■ ■ BLOCK DIA GRAM (10) Clock Data LE PS RF Xfin RF fin RF OSC IN fin IF PS IF V CCIF GND IF fp IF Do IF LD IF T1 T2 T1 T2 FC RF SW RF LDS Do RF OR LD / fout LD fr IF fr RF fp .
MB15F74UV 5 ■ ■ ■ ■ ABSOLUTE MAXIMUM RA TINGS W ARNING: Semiconductor de vices can be per manently damaged b y application of stress (voltage, current, temperature , etc.
MB15F74UV 6 * ■ ■ ■ ■ ELECTRICAL CHARA CTERISTICS (V CC = 2.7 V to 3.6 V, T a = − 40 ° C to + 85 ° C) (Continued) P arameter Symbol Condition Va l u e Unit Min T yp Max Power supply current I CCIF * 1 fin IF = 2000 MHz V CCIF = 3.0 V 2.1 2.
MB15F74UV 7 (Continued) (V CC = 2.7 V to 3.6 V, T a = − 40 ° C to + 85 ° C) *1 : Conditions ; f osc = 12.8 MHz, T a = + 25 ° C, SW = “0” in locking state. *2 : V CCIF = V CCRF = 3.0 V, f osc = 12.8 MHz, T a = + 25 ° C, in power sa ving mode.
MB15F74UV 8 ■ ■ ■ ■ FUNCTIONAL DESCRIPTION 1. Pulse swallo w function f VCO = [ (P × N) + A] × f OSC ÷ R f VCO : Output frequency of e xter nal voltage controlled oscillator (VCO) P : Prese.
MB15F74UV 9 (2) Data setting • Binar y 14 - bit Programmab le Ref erence Counter Data Setting Note : Divide ratio less than 3 is prohibited. • Binar y 11 - bit Programmab le Counter Data Setting N.
MB15F74UV 10 • Prescaler Data Setting • Charge Pump Current Setting • LD / f out output Selectable Bit Setting • Phase Comparator Phase Switching Data Setting Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set.
MB15F74UV 11 3. P ower Sa ving Mode (Intermittent Mode Control Cir cuit) The inter mittent mode control circuit reduces the PLL pow er consumption. By setting the PS pin low, the de vice enters into the pow er saving mode, reducing the current consumption.
MB15F74UV 12 4. Serial Data Data Input Timing Divide ratio is perf or med through a ser ial interf ace using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transf erred to a latch at the rise of the LE signal.
MB15F74UV 13 ■ ■ ■ ■ PHASE COMP ARA T OR OUTPUT W A VEFORM • LD Output Logic Notes : • Phase error detection range = − 2 π to + 2 π • Pulses on Do IF/RF signals during locking state are output to pre vent dead z one. • LD output becomes low when phase error is t WU or more .
MB15F74UV 14 ■ ■ ■ ■ TEST CIRCUIT (f or Measuring Input Sensitivity fin/OSC IN ) LD/ fout Do IF V CCIF 1000 pF 0.1 µ F 0.1 µ F PS IF GND IF fin IF Xfin IF GND OSC IN Do RF V CCRF PS RF GND RF Xfin RF fin RF LE Data Clock S.
MB15F74UV 15 ■ ■ ■ ■ TYPICAL CHARA CTERISTICS 1. fin input sensitivity 10 1500 2000 2500 3000 3500 4000 4500 5000 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC 0 − 10 − 20 − 30 − 40 − 50 Pfin RF [dBm] fin RF [MHz] Ta = +25 C Catalog guaranteed range 10 0 500 1000 1500 2000 2500 3000 V CC = 2.
MB15F74UV 16 2. OSC IN input sensitivity 10 0 20 40 80 100 140 160 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V SPEC 0 − 10 − 20 − 30 − 40 − 50 60 120 Catalog guaranteed range Input sensitivity vs.
MB15F74UV 17 3. RF/IF-PLL Do output current • 1.5 mA mode • 6.0 mA mode 2.50 0.50 − 2.50 1.0 3.0 0.0 2.0 0.5 2.5 1.5 2.00 − 1.00 1.50 − 1.50 1.
MB15F74UV 18 4. fin input impedance 494.28 Ω − 874.84 Ω 200 MHz 58.094 Ω − 216.47 Ω 1 GHz 39.773 Ω − 148 Ω 1.5 GHz 1 : 2 : 3 : START 100.000 000 MHz STOP 2 000.000 000 MHz − 102.92 Ω 2 000.000 000 MHz 4 : 30.266 Ω 1 2 3 4 773.21 fF 37.
MB15F74UV 19 5. OSC IN input impedance OSC IN input impedance 2.25 k Ω − 2.2373 k Ω 10 MHz 881.62 Ω − 1.8299 k Ω 20 MHz 448.75 Ω − 1.353 k Ω 30 MHz 1 : 2 : 3 : START 3.000 000 MHz STOP 40.000 000 MHz 4 : 278.69 Ω− 1.0537 k Ω 40.
MB15F74UV 20 ■ ■ ■ ■ REFERENCE INFORMA TION ( for Lock - up Time , Phase Noise and Reference Leakage ) (Continued) Test Circuit S.G. OSC IN fin Do LPF VCO Spectrum Analyzer 7.5 k Ω 1.6 k Ω 0.1 F 0.01 F 3300 pF V CC = 3.0 V Ta = + 25 ° C CP : 6 mA mode f VCO = 2113.
MB15F74UV 21 (Continued) 2.173604000 GHz 2.173600000 GHz 2.173596000 GHz 4.500 ms 2.000 ms A Mkr x: 439.99764 µ s y: 50.0009 MHz -500 µ s 500 µ s/div 2.113604000 GHz 2.113600000 GHz 2.113596000 GHz 2.000 ms A Mkr x: 400.00146 µ s y: − 50.0013 MHz 4.
MB15F74UV 22 ■ ■ ■ ■ APPLICA TION EXAMPLE LD/ fout Do IF V CCIF 1000 pF 0.1 µ F 0.1 µ F PS IF GND IF fin IF Xfin IF GND OSC IN Do RF V CCRF PS RF GND RF Xfin RF fin RF LE Data Clock 1000 pF .
MB15F74UV 23 ■ ■ ■ ■ USA GE PRECA UTIONS (1) V CCRF and V CCIF must be equal v oltage. Ev en if either RF-PLL or IF-PLL is not used, power must be supplied to V CCRF and V CCIF to k e ep them equal. It is recommended that the non-use PLL is controlled by po wer saving function.
MB15F74UV 24 ■ ■ ■ ■ P A CKA GE DIMENSION 18-pin plastic BCC (LCC-18P-M05) Dimensions in mm ( inches ) Note : The values in parentheses are reference values. C 2003 FUJITSU LIMITED C18058S-c-1-1 0.05(.002) 1 2.70 ± 0.10 2.40 ± 0.10 (.094 ± .
MB15F74UV FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.
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