Instruction/ maintenance manual of the product DSP56364 Freescale Semiconductor
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Document Number: DSP56364UM Rev. 2 08/2006 DSP56364 24-Bit Digital Signal Pr ocessor Users Manual.
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BookTitle, Rev . # Freescale Semiconductor iii Manual Conventions 1 Overview 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . .
BookTitle, Rev . # iv Freescale Semiconductor 3 Memory Configuration 3.1 Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Program Memory Space . . . . . .
BookTitle, Rev . # Freescale Semiconductor v 5 General Purpose Input/Output Port (GPIO) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 GPIO Programming Model .
BookTitle, Rev . # vi Freescale Semiconductor 6.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 . . . . . . . . . . . . . . . . . . . .
BookTitle, Rev . # Freescale Semiconductor vii 6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 . . . . . . . . . . . . . . . . .
BookTitle, Rev . # viii Freescale Semiconductor 6.6.2 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.6.3 Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . .
BookTitle, Rev . # Freescale Semiconductor ix 7.6.2 I 2 C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.7 SHI Programming Considerations . . . . . . . . . . . . . . . . .
BookTitle, Rev . # x Freescale Semiconductor.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor xi Figure 1-1 DSP56364 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 2-1 Signals Identified by Functional Group .
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xii Freescale Semiconductor Figure C-2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 Figure C-3 Interrupt Priority Register-C ore (IPR-C) .
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor xiii Table 2-1 DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Table 2-2 Power Inputs . . . . . . .
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xiv Freescale Semiconductor.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor xv Preface This manual contains the foll owing sections and appendices. SECTION 1—DSP56364 OVERVIEW • Provides a brief description of the DSP56364, incl uding a features list and block diagram.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xvi F reescale Semico nductor Manual Con ventions The following conventions are used in this manual: • Bits within registers are always listed from most significant bi t (MSB) to least significant bit (LSB).
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor xvii — the reset instructi on, written as “RESET ,” — the reset operating state, written as “Reset,” and — the reset function, written as “reset.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 xviii F reescale Semico nductor.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-1 1 Overview 1.1 Intr oduction The DSP56364 24-Bit Digital Signal Processor , a new audio digital signal proc.
Features DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-2 F reescale Semico nductor Figure 1-1 DSP56364 Block Diagram 1.2 Features • DSP56300 modular chassis — 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.
Audio Pr oces sor Architecture DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-3 — V ery low-power CMOS design, fully static design with operating frequencies down to DC. — STOP and W AIT low-power standby modes.
Core Description DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-4 F reescale Semico nductor 1.4 Core Description The DSP56364 uses the DSP56300 core, a high-performance, single cloc.
DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-5 1.5.1.1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode).
DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-6 F reescale Semico nductor 1.5.3 Pr ogram Control Unit (PCU) The PCU performs instruction pref etch, instruction decoding, hardware DO loop control, and exception processing.
DSP56300 Core Functional Blocks DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-7 • Y memory expansion bus (YM_EB) to Y memory • Global data bus (GDB) be.
Data and Program memory DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-8 F reescale Semico nductor 1.5.7 JT A G T AP and OnCE Module The DSP56300 core provides a dedicated user -accessible T AP fully compatible with the IEEE 1149.1 Standar d T est Access P ort and Boundary Scan Ar chitectur e .
Internal I/O Memor y Map DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 1-9 memory switch can be accomplishe d provided that the af fected addr ess ranges are not being accessed during the instruction cycle in which the switch operation takes place.
Status Register (SR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 1-10 F reescale Semico nductor 1.8 Status Register (SR) Refer to the DSP56300 24-Bit Digi tal Signal Processor Family Manual, Freescale publication DSP56300FM/AD for a description of the Status Register bits.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-1 2 Signal/Connection Descriptions 2.1 Signal Gr oupings The input and output signals of th e DSP56364 are organized into functi onal groups, which are listed in Ta b l e 2 - 1 and illustrated in Figure 2-1 .
Signal Groupings DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-2 F reescale Semico nductor Figure 2-1 Signals Identified b y Functional Group PORT A ADDRESS BUS A0-A17 VCCA (4) GND.
Pow e r DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-3 2.2 P ower 2.3 Gr ound T able 2-2 P ower Inputs P ower Name Description V CCP PLL P ower —V CCP is V CC dedicated for PLL use .
Cloc k and PLL DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-4 F reescale Semico nductor 2.4 Cloc k and PLL 2.5 External Memory Expansion P ort (P or t A) When the DSP56364 enters a low-power standby mode (st op or wait), it tri-stat es the relevant port A signals: D0–D7, AA0, AA1, RD , WR , CAS .
External Memory Expansion P ort (Port A) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-5 2.5.2 External Data Bus 2.
Interrupt and Mode Control DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-6 F reescale Semico nductor 2.6 Interrupt and Mode Contr ol The interrupt and mode control signals select the chip’ s operating m ode as it comes out of hardware reset.
Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-7 2.7 Serial Host Interface The SHI has five I/O signals that can be configured to allo.
Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-8 F reescale Semico nductor . T ab le 2-9 Serial Host Interf ace Signals Signal Name Signal Ty p e State during .
Serial Host Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-9 MOSI Input or output T ri-stated SPI Master-Out-Slave-In —When the SPI is configured as a master , MOSI is the master data output l ine.
Enhanced Serial A udio Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-10 F reescale Semico nductor 2.8 Enhanced Serial A udio Interface T ab le 2-10 Enhanced Serial Au dio.
Enhanced Serial Au d i o I n t e rf a c e DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-11 FST Input or output GPIO disconnected Frame Sync for T ransmitter —This is the transm itter frame sync input/output signal.
Enhanced Serial A udio Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-12 F reescale Semico nductor SDO5 Output GPIO disconnected Serial Data Output 5 —When programmed as a transmitter , SDO5 is used to transmit data from the TX5 serial transmit shift register.
JT A G/OnCE Interface DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 2-13 2.9 JT A G/OnCE Interface SDO1 Output GPIO disconnected Serial Data Output 1 —SDO1 is used to transmit data from the TX1 serial transmit shift regist er .
GPIO Signals DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 2-14 F reescale Semico nductor 2.10 GPIO Signals T able 2-12 GPIO Signals Signal Name Signal T ype State during Reset Signa.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-1 3 Memor y Configuration 3.1 Memory Spaces The DSP56364 provides the following three independent memory spac.
Memory Spaces DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-2 F reescale Semico nductor Customer code should not use this area. The conten ts of this program ROM segment is defined by the bootstrap ROM source code in Appendix A, "Bootstrap ROM" .
Memory Space Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-3 3.1.2.2 X Data RAM The on-chip X data RAM consists of 24-bit wide, high-speed, internal st atic RAM occupying 1K locations in the X memory space.
Internal Memory Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-4 F reescale Semico nductor Memory maps for the dif ferent configurations are shown in Figure 3-1 to Figure 3-4 . 3.3.1 RAM Locations The actual memory locations for pro gram RAM a nd Y data RAM in their own memory space are determined by the MS bit.
Internal Memory Configuration DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-5 3.3.3 Dynamic Memory Configuration Switching The internal memory configurati on is altered by remapping RAM modul es from Y data memory into program memory space and vice-ve rsa.
Memory Maps DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-6 F reescale Semico nductor 3.4 Memory Maps Figure 3-1 Memory Maps for MS=0, SC=0 Figure 3-2 Memory Maps for MS=1, SC=0 PROGRAM $FFFFFF $000000 $000200 0.
Memory Maps DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 3-7 Figure 3-3 Memory Maps for MS=0, SC=1 Figure 3-4 Memory Maps for MS=1, SC=1 PROGRAM $FFFF $0000 $0200 0.5K INTERNAL RAM X DATA $FFFF $0000 $0400 1K INTERNAL RAM INTERNAL I/O Y DATA $FF80 (128 words ) EXTERNAL EXTERNAL $FFFF $0000 $0600 1.
External Memory Suppor t DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 3-8 F reescale Semico nductor 3.5 External Memory Suppor t The DSP56364 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Di gital Signal Processor Family Manual, Freescale publication DSP56300FM/AD.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-1 4 Core Configuration 4.1 Intr oduction This chapter contains DSP56300 core configuration information deta ils specific to the DSP56364.
Operating Mode Regist er (OMR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-2 F reescale Semico nductor 4.2.1 Mode C (MC) - Bit 2 The Mode C (MC) bit is set during hardware reset and should be left set in the DSP56364.
Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-3 4.3 Operating Modes The operating modes are as shown in Ta b l e 4 - 1 The operating modes are latched from MODA, MODB and MODD pins during reset.
Bootstrap Program DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-4 F reescale Semico nductor address to start loading the program words and then a 24-bi t word for each program word to be loaded. The program words will be st ored in contiguous PRAM memory locations starting at the specified star ting address.
Interrupt Priori ty Register s DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-5 The interrupt vectors are shown in Ta b l e C - 2 and the interrupt priorities are shown in Ta b l e C - 3 in Appendix C, "Programmer ’ s Reference" .
Interrupt Priori ty Registers DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-6 F reescale Semico nductor Figure 4-2 Interrupt Priority Regi ster P Figure 4-3 Interrupt Prior ity Reg.
DMA Request Sources DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-7 4.6 DMA Request Sour ces The DMA Request Source bits (DRS0-DR S4 bits in the DMA Control/S tatus registers) encode the source of DMA requests used to trigger the DMA transfer s.
Device Identification (ID) Register DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-8 F reescale Semico nductor 4.7.2 Crystal Rang e Bit (XTLR) - Bit 15 The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance.
JT A G Boundary Sc an Register (BSR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 4-9 4.10 JT A G Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56364 JT AG implementation contains bits for all device signal and clock pins and asso ciated control signals.
JT A G Boundary Scan Register (BSR) DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 4-10 F reescale Semico nductor A12 Output3 Data SDO2/SDI3 - Control A[17:9] - Control SDO2/SDI3 Inpu.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 5-1 5 General Purpose Input/Output P or t (GPIO) 5.1 Intr oduction The General Purpose Input/Output (GPI O) pins are used for control a nd handshake functions between the DSP and external circuitry .
GPIO Pr ogramming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 5-2 F reescale Semico nductor 5.2.1 P or t B Contr ol Register (PCRB) The read/write Port B Control Regist er (PCRB) controls the functionality of the GPIO pins in conjunction with the Port B Direct ion Register (PRRB).
GPIO Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 5-3 Port B Direction Register (PRRB) The read/write Port B Direction Re gister controls the direction of data transfer for each GPIO pin. 5.
GPIO Pr ogramming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 5-4 F reescale Semico nductor NO TES.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-1 6 Enhanced Serial A UDIO Interface (ESAI) 6.1 Intr oduction The Enhanced Serial Audio Interfac e (ESAI) pro.
Introd uction DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-2 F reescale Semico nductor Figure 6-1 ESAI Block Diagram SDO1 [PC10] SDO0 [PC11] Shift Register RX0 TX5 SDO5/SDI0 [PC6].
ESAI Data and Contr ol Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-3 6.2 ESAI Data and Contro l Pins Three to twelve pins are require d for operation, depending on the opera ting mode selected and the number of transmitters and receivers enable d.
ESAI Data and Control Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-4 F reescale Semico nductor 6.2.4 Serial T ransmit 3/Receive 2 Data Pin (SDO3/SDI2) SDO3/SDI2 is used as th.
ESAI Data and Contr ol Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-5 When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register .
ESAI Data and Control Pins DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-6 F reescale Semico nductor SCKT may be programmed as a general-purpose I/O pi n (PC3) when the ESAI SC KT function is not being used.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-7 6.2.10 Frame Sync f or T ransmitter (FST) FST is a bidirectional pin providing the f.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-8 F reescale Semico nductor special-purpose time slot register . The following paragraphs give detail ed descriptions and operations of each bit in the ESAI registers.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-9 Figure 6-3 ESAI Cloc k Generator Functiona l Block Diagram 6.3.1.2 TCCR T ransmit Prescaler Rang e (TPSR) - Bit 8 The TPSR bit controls a fixed divide -by-eight prescaler in series with the variable prescaler .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-10 F reescale Semico nductor operational (see Figure 6-3 ). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-11 Figure 6-4 ESAI Frame Sync Gener ator Functional Bloc k Diagram 6.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-12 F reescale Semico nductor 6.3.1.5 TCCR T ransmit Clock P olarity (TCKP) - Bit 18 The T ransmitter Clock Polarity (TCK P) bit controls on which bit cloc k edge data and frame sync are clocked out and latched in.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-13 6.3.2 ESAI T r ansmit Control Register (TCR) The read/write T ransmit Control Re gister (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-14 F reescale Semico nductor In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after completing transmission of the c urrent data word until the beginning of the next frame.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-15 transmitter #4 is disabled after completing transmissi on of data currently in the ESAI transmit shift register . Data can be written to TX4 when TE4 is cleared but the data is not trans ferred to the transmit shift register #4.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-16 F reescale Semico nductor Since the data word is shorter than the slot length, th e data word is extended until achieving the slot length, according to the following rule: 1.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-17 Figure 6-6 Normal and Netw ork Operation Normal Mode SERIAL FRAME SYNC SERIAL DA T .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-18 F reescale Semico nductor 6.3.2.10 TCR Tx Slot and W ord Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-19 6.3.2.11 TCR T ransmit Frame Sy nc Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-20 F reescale Semico nductor Figure 6-7 Frame Length Selection DA T A DA T A SERIAL CLOC K RX, TX FRAME SYNC WORD LENG TH: TFSL=0, RF SL=0 RX, TX SERIAL DA T A NOTE: Frame sync occurs while data is valid.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-21 6.3.2.12 TCR T ransmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the tr ansmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0).
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-22 F reescale Semico nductor 6.3.2.17 TCR T ransmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data in terr upts.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-23 Hardware and software reset clear all the bits of the RCCR register .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-24 F reescale Semico nductor The ESAI frame sync generator functional diagram is shown in Figure 6-4 .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-25 6.3.3.8 RCCR Receiver Cloc k Sour ce Direction (RCKD) - Bit 21 The Receiver Clock S.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-26 F reescale Semico nductor 6.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receive.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-27 receivers can be enabled) if the input data pin is not used by a transmitter . Operating modes are also selected in this register . Hardware and software reset clear all the bits in the RCR register .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-28 F reescale Semico nductor 6.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 When RE3 is set and TE2 is cleared, the ESAI receiv er 3 is enabled and samples data at the SDO2/SDI3 pin.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-29 6.3.4.9 RCR Receiver Slot and W or d Select (RSWS4-RSWS0) - Bits 10-14 The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-30 F reescale Semico nductor 6.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the lengt h of the receive frame sync to be generated or recogn ized.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-31 6.3.4.12 RCR Receiver Section P ersonal Reset (RPR) - Bit 19 The RPR control bit is used to put the receiver section of the ESAI in the personal reset state.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-32 F reescale Semico nductor 6.3.5 ESAI Common Contr ol Register (SAICR) The read/write Common Control Regist er (SAICR) contains control bits for functions that af fect both the receive and transmit sect ions of the ESAI.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-33 6.3.5.5 SAICR Synchr onous Mode Selection (SYN) - Bit 6 The Synchronous Mode Select.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-34 F reescale Semico nductor Figure 6-11 SAICR SYN Bit Op eration 6.3.6 ESAI Status Register (SAISR) The S tatus Register (SAISR) is a read-only status regi ster used by the DSP to read the status and serial input flags of the ESAI.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-35 6.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 The IF0 bit is enabled only when th.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-36 F reescale Semico nductor 6.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 When set, RFS indicates that a r eceive frame sync occurred during recep tion of the words in the receiver data registers.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-37 6.3.6.10 SAISR T ransmit Frame Sync Flag (TFS) - Bit 13 When set, TFS indicates that a trans mit frame sync occurred in the curren t time slot.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-38 F reescale Semico nductor 6.3.6.14 SAISR T ransmit Odd-Data Register Empty (T ODE) - Bit 17 When set, TODE indicates that the enabled transmitte r data registers became empty at the beginning of an odd time slot.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-39 Figure 6-13 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=0) SDI 23 16 15 8 7 0 70 .
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-40 F reescale Semico nductor Figure 6-14 ESAI Data P ath Pr ogramming Model ([R/T]SHFD=1) SDI 23 16 15 8 7 0 70.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-41 6.3.7 ESAI Receive Shift Register s The receive shift registers (see Figure 6-13 and Figure 6-14 ) receive the incoming data from the serial receive data pins.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-42 F reescale Semico nductor transmitter empty condition (TDE=1), or to tri-stat e the transmitter data pi ns. TSMA and TSMB should each be considered as containing half a 32-bit register TSM.
ESAI Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-43 After hardware or software reset, the TSM register is preset to $FFFFFFFF , which means that all 32 possible slots are enable d for data transmission.
Operating Mod es DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-44 F reescale Semico nductor When bit number N in the RSM is set, the receive seque nce is as usual: data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set.
Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-45 NO TE If the ESAI receiver section is already operating with some of the receivers, enabling additional receivers on the fly (i.
Operating Mod es DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-46 F reescale Semico nductor the previous setting and the new frame is servic ed with the new setti ng without synchronization problems.
Operating Modes DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-47 or they may have their own separate clock and sync signals (a synchronous operating m ode). The SYN bit in the SAICR register selects s ynchronous or asynchronous operation.
GPIO - Pins and Regi sters DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-48 F reescale Semico nductor programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD bit in the TCR register for the transmitter section.
GPIO - Pins and Regi sters DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-49 6.5.2 P ort C Direction Register (PRRC) The read/write 24-bit Port C Direct ion Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionali ty of the ESAI GPIO pins.
ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-50 F reescale Semico nductor configured as GPIO. If a port pin [i] is configured as a GPIO i nput, then the corresponding PD[i] bit reflects the value present on this pin.
ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 6-51 6.6.2 Initializing J ust the ESAI T ransmitter Section • It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin.
ESAI Initialization Examples DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 6-52 F reescale Semico nductor NO TES.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-1 7 Serial Host Interface 7.1 Intr oduction The Serial Host Interface (SHI) is a serial I/O interface that provides a path for commu nication and program/coefficient data transfers between the DSP and an external host processor .
Serial Host Interface Internal Arch itecture DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-2 F reescale Semico nductor 7.2 Serial Host Interface Internal Ar chitecture The DSP views the SHI as a memory-mapped periphera l in the X data memory space.
SHI Cloc k Generator DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-3 7.3 SHI Cloc k Generator The SHI clock generator generates the serial clock to the SHI if the in terface operates in the Master mode.
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-4 F reescale Semico nductor Figure 7-4 SHI Programming Mod el—DSP Side HCKFR 8 15 14 13 12 1.
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-5 The interrupt vector table for the Serial Host Interface is shown in Ta b l e 7 - 1 and the exceptions generated by the SHI are prioritized as shown in Ta b l e 7 - 2 .
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-6 F reescale Semico nductor Figure 7-5 SHI I /O Shift Register ( IOSR) 7.4.2 SHI Host T ransmit Da ta Register (H TX)—DSP Side The Host T ransmit data register (HTX ) is used for DSP-to-Host data tran sfers.
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-7 7.4.4.1 HSAR Reserved Bits—Bits 17–0,19 These bits are reserved and unused. They read as 0s a nd should be written with 0s for future compatibility .
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-8 F reescale Semico nductor Figure 7-6 SPI Data-T o-Clock T iming Diagram The Clock Phase (CPHA) bit controls the relationshi p between the data on the MISO and MOSI pins and the clock produced or received at th e SCK pin.
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-9 When in Master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE.
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-10 F reescale Semico nductor When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment.
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-11 7.4.6.1.1 SHI Individual Reset While the SHI is in the individual.
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-12 F reescale Semico nductor It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardwa re reset and software reset.
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-13 7.4.6.9 HCSR Idle (HIDLE)—Bit 9 The read/write control/status bit Host Idle (HIDLE) is used only in the I 2 C Master mode; it is ignored otherwise.
Serial Host Interface Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-14 F reescale Semico nductor NO TE Clearing HBIE will mask a pending bus-error interr upt only after a one-instruction-cycle delay .
Serial Host Interfa ce Programming Model DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-15 NO TE Clearing HRIE[1:0] will mask a pe nding receive interrupt only after a one-instruction-cycle dela y .
SPI Bus Characteristics DSP56364 24-Bit Digital Signal Processor Users Manual, Re v . 2 7-16 F reescale Semico nductor 7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 The read-only status bit Host Receiv e FIFO Full (HRFF) indicates that the Host Receive FIFO (HRX) is full.
I 2 C Bus Characte ristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-17 the master data input line, and MOSI is the master data output line. When the SPI is conf igured as a slave device, these pins reverse roles.
I 2 C Bus Characteristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-18 F reescale Semico nductor • Stop data transfer —The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 7-8 ).
I 2 C Bus Characte ristics DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-19 the slave device is ready for the next byte transfer . The SHI supports this fe ature when operating as a master device and will wait until the slave device releases the SCL line before proceeding with the data transfer .
SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-20 F reescale Semico nductor 7.7 SHI Pr ogramming Considerations The SHI implements both SPI and I 2 C bus protocols and can be programmed to operate as a slave device or a single-master device.
SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-21 7.7.2 SPI Master Mode The SPI Master mode is initiated by enabling th e SHI (HEN = 1), selecting the SPI mode (HI 2 C = 0), and selecting the Master mode of operation (HMST = 1).
SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-22 F reescale Semico nductor • SCK/SCL is the SCL serial clock input. • MISO/SDA is the SDA open drain serial data line. • MOSI/HA0 is the HA0 slav e device address input.
SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-23 7.7.3.2 T ransmit Data In I 2 C Slave Mode A transmit session is initiated when the personal slave device address has been co rrectly identified and the R/W bit of the received slave device a ddress byte has been set.
SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-24 F reescale Semico nductor In the I 2 C Master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set.
SHI Prog ramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor 7-25 In a receive session, only the receiv e path is enabled and the HTX-to-I OSR transfers are inhibited.
SHI Pr ogramming Considerations DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 7-26 F reescale Semico nductor NO TES.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-1 Appendix A Bootstrap R OM A.1 DSP56364 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56364 - (C) Copyright 1998 Freescale Inc. ; Revised August 11, 1998. ; ; ; This is the Bootstrap program contained in the DSP56364 192-word Boot ; ROM.
Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-2 F reescale Semico nductor opt cex,mex,mu ;; ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; ;; BOOT equ .
Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-3 ; MD:MC:MB:MA=1110 - Bootstrap from SHI (I2C slave, HCKFR=1) ; MD:MC:MB:MA=1111 - Bootstrap from SHI (I2C slave, HCKFR=0) SHILD ; This is the routine which loads a program through the SHI port.
Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-4 F reescale Semico nductor ;======================================================================== ; This is the routine that loads from external EPROM.
Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-5 bra <* ;======================================================================== ; Code f.
Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-6 F reescale Semico nductor ;; write pattern to all memory locations if (EQUALDATA) ;; x/y ram symmetrical ;; write x an.
Bootstrap R OM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor A-7 eor x1,a add a,b ;; accumulate error in b _loopx ;; check yram clr a #start_yram,r1 ;; resto.
Bootstrap ROM DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 A-8 F reescale Semico nductor dc * endm ORG PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories dc $555555 dc.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-1 Appendix B BDSL File B.1 BSDL FILE -- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generate.
BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-2 F reescale Semico nductor EXTAL: in bit; TA_N: in bit; CAS_N: out bit; WR_N: out bit; RD_N: out bit; CVCC: linkage bit; CG.
BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-3 "PVCC: 31, " & "PCAP: 32, " & "PGND: 33, " & "EXTA.
BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-4 F reescale Semico nductor attribute BOUNDARY_LENGTH of DSP56364 : entity is 86; attribute BOUNDARY_REGISTER of DSP56364 : .
BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor B-5 "46 (BC_1, TA_N, input, X)," & "47 (BC_1, EXTAL, input, X)," & ".
BDSL File DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 B-6 F reescale Semico nductor.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-1 Appendix C Programmer’ s Reference C.1 Intr oduction This section has been compiled as a reference for programmers.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-2 F reescale Semico nductor DMA $FFFFF4 DMA ST A TUS REGISTER (DSTR) $FFFFF3 DMA OFFSET REGISTER 0 (D OR0) $.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-3 Reserved $FFFFD7 thru $FFFFD0 RESER VED POR T B $FFFFCF POR T B CONTROL REGISTER.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-4 F reescale Semico nductor ESAI $FFFFBC ESAI RECEIVE SLO T MASK REGISTER B (RSMB) $FFFFBB ESAI RECEIVE SLOT.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-5 Reserved $FFFF9F thr u $FFFF95 RESER VED SHI $FFFF94 SHI RECEIVE FIFO (HRX) $FFF.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-6 F reescale Semico nductor VBA:$2E 0 - 2 Reser ved VBA:$30 0 - 2 ESAI Receiv e Data VBA:$32 0 - 2 ESAI Rece.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-7 IRQD (External Interrupt) DMA Channel 0 Interr upt DMA Channel 1 Interr upt DMA .
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-8 F reescale Semico nductor C.2 Programming Sheets The following worksheets list the major programmable registers for the DSP56364.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-9 Figure C- 1. Status R egister ( SR) Application: Date: Programme r: Sheet 1 of 5.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-10 F reescale Semico nductor Figure C-2. Operating Mode Register (OMR) Chip Operating Modes MOD(D:A) Reset Vector Descri ption ( Ta b l e 4 - 1 in Section 4.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-11 Figure C-3. Interrupt Priorit y Register-Core (IPR-C) CENTRAL PROCESSOR 15 14 13 12 11 10 9 8 76543210 D1L0 IDL2 IDL1 I BL2 IBL1 IBL0 IAL2 IAL1 IAL0 D0L1 D0L0 23 22 21 20 19 18 16 17 D1L1 IAL2 Trigger 0 Level 1 Neg.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-12 F reescale Semico nductor Figure C-4. Interrupt Prior ity Register - P eripherals (IPR-P) CENTRAL PROCESS.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-13 Figure C-5. Phase Loc k Loop Contr ol Register (PCTL) PLL 15 14 13 12 11 10 9 8.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-14 F reescale Semico nductor Figure C-6. SHI Sla ve Address (HSAR) and Clock Contr ol Register (HCKR) Applic.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-15 Figure C-7. SHI Host T ransmit Data Register (HTX) and Host Receive Data Regist.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-16 F reescale Semico nductor Figure C-8. SHI Host Cont r ol/Statu s Registe r (HCSR) SHI * = Reserved, write.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-17 Figure C-9. ESAI T ransmit Clock Control Register (TCCR) TCKP 0 Transmitter Clo.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-18 F reescale Semico nductor Figure C-10. ESAI T ransmit Clock Contr ol Register (TCR) 1 5 654 19 18 17 16 1.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-19 Figure C-11. ESAI Receive Cloc k Control Register (RCCR) 15 6 5 4 19 18 17 16 1.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-20 F reescale Semico nductor Figure C-12. ESAI Receive Cloc k Contr o l Register (RCR) 1 5 654 19 18 17 16 1.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-21 Figure C-13. ESAI C ommon Control Register ( SAICR) 15 6 5 4 19 18 17 1 6 10 9 .
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-22 F reescale Semico nductor Figure C-14. ESAI Status Re gister (SAISR) 15 6 5 4 19 18 17 16 10 9 8 7 14 13 12 11 IF0 3210 IF2 23 22 21 20 IF1 RFS RDF Description Description 0 1 Holds data sent from SC KR pin.
Progra mmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 F reescale Semiconductor C-23 Figure C-15. P ort B R egisters (PCRB, PRRB, PDRB) Application: Date: Programme.
Programmer’ s Reference DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 C-24 F reescale Semico nductor Figure C-16. P ort C R egisters (PCRC, PRRC, PDRC) Application: Date: Programme.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor Index-1 Inde x A adder modulo 1-5 offset 1-5 reverse-carry 1-5 Address Attribute 4-2 address attribute 4-2 Addre.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Index-2 Freescale Semiconductor Receive Interrupt Enable Bits 7-14 SHI Control/Status Register 7-10 HDM0-HDM5 (HCKR Divider Modulus Sele.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Freescale Semiconductor Index-3 P PAB 1-7 PAG 1-6 PC register 1-6 PCU 1-6 PDB 1-7 PDC 1-6 Peripheral I/O Expansion Bus 1-6 Peripheral mo.
DSP56364 24-Bit Digital Signal Processor Users Man ual, Rev . 2 Index-4 Freescale Semiconductor Sixteen-bit Compatibility 3-1 Size register (SZ) 1-6 SP 1-6 SPI 7-1, 7-16 HCSR Bus Error 7-16 Host Busy .
An important point after buying a device Freescale Semiconductor DSP56364 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Freescale Semiconductor DSP56364 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Freescale Semiconductor DSP56364 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Freescale Semiconductor DSP56364 you will learn all the available features of the product, as well as information on its operation. The information that you get Freescale Semiconductor DSP56364 will certainly help you make a decision on the purchase.
If you already are a holder of Freescale Semiconductor DSP56364, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Freescale Semiconductor DSP56364.
However, one of the most important roles played by the user manual is to help in solving problems with Freescale Semiconductor DSP56364. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Freescale Semiconductor DSP56364 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
