Instruction/ maintenance manual of the product DS610 Xilinx
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DS610 J uly 16, 20 07 www .xil inx.com 1 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners.
Data Sheet 2 www .xilinx. com DS610 J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank..
DS610-1 (v2.0) July 16, 2007 www .xil inx.com 3 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners.
Intr oduction and Ordering Inf ormation 4 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Ar chitectural Ov er view The S par tan-3A DSP f a mily ar chitectu re cons ists of .
Intr oduction and Ordering Inf ormation DS610-1 (v2.0) July 16, 2007 www .xil inx.com 5 Pr oduct Specific ation R Figure 1 : Spar tan-3A DS P Family Ar chitecture CLB Block RAM DCM IOBs IOBs DS610-1_01_031207 IOBs IOBs DCM Block RAM / DSP48A Slice DCM CLBs IOBs DSP48A Slice Notes: 1 .
Intr oduction and Ordering Inf ormation 6 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Pa c k a g e M a r k i n g Figure 2 shows the to p mar king f or Sp ar tan -3A D SP FPGAs.
Intr oduction and Ordering Inf ormation DS610-1 (v2.0) July 16, 2007 www .xil inx.com 7 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. Date V ers ion Revision 04/02/07 1.0 Initial Xili nx release.
Intr oduction and Ordering Inf ormation 8 www .xilinx. com DS610-1 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank.
DS610-2 (v2.0) July 16, 2007 www .xil inx.com 9 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners.
Functional Description 10 www .xilinx. com DS610-2 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank..
DS610-3 (v2.0) July 16, 2007 www .xil inx.com 11 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners.
DC and Switching Characteristics 12 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R P ower S upply Specifica tions General Recomm ended Operating Conditions T able 4: Supply V oltage Thresholds for P ower -On Reset Symbol Description Min Max Units V CCINTT Threshold f or the V CCINT supply 0.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 13 Pr oduct Specific ation R General DC Characteristic s for I/O Pins T able 8: General DC Characteristics of User I/O, .
DC and Switching Characteristics 14 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Quiescent Curr ent Requiremen ts T able 9: Quiescent Suppl y Current Characteristics Symb .
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 15 Pr oduct Specific ation R Single-Ended I/O Stand ards T able 10: Recommended Operating Conditions for User I/Os Using.
DC and Switching Characteristics 16 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 11: DC Characteristic s of User I/Os Using Single-Ended St andards IOST ANDARD Attribute Te s t Conditions Logic Le vel Character istics I OL (mA) I OH (mA) V OL Max (V) V OH Min (V) L VTTL (3) 22 – 2 0 .
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 17 Pr oduct Specific ation R Differen tial I/O Standards Figure 3 : Differential Input V olt ages T able 12: Reco mmende.
DC and Switching Characteristics 18 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Figure 4: Diff erential Output V oltages T able 13: DC Characteristics of User I/Os Using .
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 19 Pr oduct Specific ation R External T ermination Requirements f or Differential I/O L VDS , RSDS, MINI_L VDS, and P PD.
DC and Switching Characteristics 20 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Switc hing Characteristics All Spa r tan- 3A DSP FPGAs s hip in two s peed grades: – 4 and the hig her pe rformanc e –5.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 21 Pr oduct Specific ation R T o c reate a X ilinx M ySuppor t use r acco unt and sign up for automa tic E-m ail notif ication w henev er this data shee t is updated: • Sign Up for Ale rts on Xilinx MySupport www .
DC and Switching Characteristics 22 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R I/O Timing T able 17: Pin-to-Pi n Clock -to-Output Times for the IOB Output P ath Symbol D.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 23 Pr oduct Specific ation R T able 18: Pin-to-Pin Setup a nd Hold Times for the IOB Input Pa th (System Sync hronous) S.
DC and Switching Characteristics 24 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 19: Setup and Hold Times for the IOB Input Path Symbol Descr iption Conditions IFD_.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 25 Pr oduct Specific ation R T able 20: Propa gation Times for the IOB Input P ath Symbol Descrip tion Conditions IFD_De.
DC and Switching Characteristics 26 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 21: Input Timin g Adjustments by IOST AND ARD Con vert Input Time fr om L VCMOS25 to the Follow ing Signal S tandar d (IOST AND ARD) Add the Adjustment Be low Units Speed Grade -5 -4 Single- Ended Standar ds L VTTL 0.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 27 Pr oduct Specific ation R T able 22: Timing for the IOB Output P ath Symbol Description Con d itions De vice Speed Gr.
DC and Switching Characteristics 28 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 24: Output Tim ing Adjustmen ts for IOB Con vert Output Time from L VCMOS25 with 12.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 29 Pr oduct Specific ation R LV C M O S 2 5 Slow 2 mA 5. 33 5.33 ns 4 mA 2.81 2.81 ns 6 mA 2.82 2.82 ns 8 mA 1.14 1.14 ns 12 mA 1.10 1.10 ns 16 mA 0.83 0.83 ns 24 mA 2.26 2.
DC and Switching Characteristics 30 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Differe ntial Standard s L VDS_25 1.16 1 .16 ns L VDS_33 0.46 0 .46 ns BL VDS_25 0.11 0 .11 ns MINI_L VDS_25 0.75 0.75 ns MINI_L VDS_33 0.40 0.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 31 Pr oduct Specific ation R Timing Measu rement Methodolog y When meas uri ng tim ing pa rameters at th e programmable I/Os, different signal stand ards ca ll for diff e rent te st conditio ns.
DC and Switching Characteristics 32 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R The cap acitive load (C L ) is connec ted be tween the ou tput and GND . The Ou tput tim ing for all standa rds, as published in the spe ed file s and th e data s heet, is a lwa ys base d on a C L val u e o f ze ro.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 33 Pr oduct Specific ation R Using IBIS Mode ls to Sim u late Load Cond itions in Application IBIS mode ls pe rm it the m ost ac curate pred ictio n of tim ing delays f or a gi ven applicatio n.
DC and Switching Characteristics 34 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 27: Recommended Number of Simult a neously Switchin g Outputs per V CCO -GND P air (V CCAUX =3 .
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 35 Pr oduct Specific ation R L VCM OS15 Slow 2 55 55 4 31 31 6 18 18 8 –1 5 12 –1 0 Fa s t 2 25 25 4 10 10 6 66 8 .
DC and Switching Characteristics 36 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Configurab le Logic Bloc k (CLB) Timing T able 28: CLB (SLICEM) Timing Symbol D escription.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 37 Pr oduct Specific ation R Cloc k Buffer/Multipl ex er Switching Charact eristics T able 29: CLB Distributed RAM Switc.
DC and Switching Characteristics 38 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Bloc k RAM Timing T able 32: Block RAM Timing Symbol Description Speed Grade Units -5 -4 M.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 39 Pr oduct Specific ation R DSP48A Timing T o reference the DSP48A block diagram, see th e XtremeDSP DSP48A f or Spar tan-3 A DSP FPGA User Guide ( UG431 ).
DC and Switching Characteristics 40 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 34: Clock to Out , Propa gation Delays, and Maximum Frequenc y for the DSP48A Symbo.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 41 Pr oduct Specific ation R Digital C lock Mana ger (DCM) Timing F or spe cificat ion pur poses, the DCM cons ists of th ree key componen ts: the Delay-Lock e d Loop (DLL), th e Digit al F requ ency Sy nthes izer (DFS), an d the P hase Shi fter (PS ).
DC and Switching Characteristics 42 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R T able 36: Switching Charact eristics for the DL L Symbol Description Device Speed Grade U.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 43 Pr oduct Specific ation R Digital Frequency Synthesizer (D FS) T able 37: Recommended Operating Conditions for the DF.
DC and Switching Characteristics 44 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Phase Shift er (PS) Miscellaneous DCM Timing T able 39: Recommend ed Opera ting Condit ion.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 45 Pr oduct Specific ation R DNA P or t Timing T able 42: DNA_PORT Interface Timing Symbol Description Min Max Units T DNASSU Setup time on SHIFT bef ore the rising edge of C LK 1 .
DC and Switching Characteristics 46 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Suspend M ode Timin g Figure 9: Suspend Mode Timing DS610-3_08_061207 Bl o cke d t SUSPEND.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 47 Pr oduct Specific ation R Confi gur atio n and JT A G Ti ming General Configurat ion P ower -On/Reconfig ure Timing F.
DC and Switching Characteristics 48 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Configurati on Cloc k (CCLK) Characterist ics T able 45: Master Mode CCLK Output P eriod b.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 49 Pr oduct Specific ation R T able 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol D escripti.
DC and Switching Characteristics 50 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Master Serial and Sla ve Serial Mode Timing Figure 11: W aveforms for Master Seria l and S.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 51 Pr oduct Specific ation R Slave P arallel Mode Timing Figure 12: W aveforms for Slave Parallel Con figurat ion T able.
DC and Switching Characteristics 52 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Serial P eripheral Interf ace (SPI) Configurat ion Timing Figure 1 3: W aveforms f or Seri.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 53 Pr oduct Specific ation R T able 52: Configuration Timing Requirements for Atta ched SPI Serial Flash Symbol Descript.
DC and Switching Characteristics 54 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Byte P eripheral Interface (BPI ) Configuration Timing Figure 14: W ave for ms f or Byt e-.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 55 Pr oduct Specific ation R T able 54: Configuration Timing Requirements for Attach e d Pa rallel NOR Flash Symbol Desc.
DC and Switching Characteristics 56 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R IEEE 1149.1/1553 JT A G T est Access P or t Timing Figure 15 : JT AG W aveforms TCK T TMST.
DC and Switching Characteris tics DS610-3 (v2.0) July 16, 2007 www .xil inx.com 57 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. Date V ersion Revis ion 04/02/07 1.0 Initial Xili nx release .
DC and Switching Characteristics 58 www .xilinx. com DS610-3 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank..
DS610-4 (v2.0) July 16, 2007 www .xil inx.com 59 Pr oduct Specific ation © 2007 Xilinx, Inc. All ri ghts reser ved. All Xilinx trademarks, registe red trademarks, paten ts, and disclaimers are as listed a t h ttp://www.xilinx.com/legal.htm . All ot her tradem ark s are th e pro per ty of th eir re spective owners.
Pinout Descriptions 60 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Pa c k a g e P i n s by Typ e Each package has t hree sep arate voltage s uppl y inputs—V CCINT , VCCA UX , and VC CO—and a c ommon ground ret ur n, GND .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 61 Pr oduct Specific ation R P ac kage Thermal Characteri stics The power dissi pated by an FPGA applicat ion ha s implic ations on package s elect ion and system desi gn.
Pinout Descriptions 62 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R CS484: 484-Ball Chip-Sca le Ball Grid Array The 484- ball ch ip-s cale ba ll gr id array , C S484, suppor ts both the XC3SD 1800A and XC3 SD3400A F PGAs. Ther e are no pi nout differences be tween the two devices.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 63 Pr oduct Specific ation R 0 IO_L1 7N_0/GCL K5 F11 G CLK 0 IP_0 F12 INPUT 0 IO_L1 3N_0 F1 3 I/O 0 IO_L1 3P_0 F14 I/O 0 IO_L0 5N_0 F1.
Pinout Descriptions 64 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IO_L03N _1/A1 V20 DUAL 1 IP_L08P_1 V22 INPUT 1 IO_L03P_1/A0 W19 D UAL 1 IP_L04N_1/VREF_1 W20 VREF 1 I.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 65 Pr oduct Specific ation R 2 IP_2/VREF_2 Y14 VREF 2 IO_L2 4N_2/D3 Y15 DU AL 2 IO_L2 9N_2 Y16 I/O 2 IO_L29P_2 Y17 I/O 2 IO_L26P_2 /D2.
Pinout Descriptions 66 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 3 IO_L36P_3 V4 I/O 3 IO_L3 5N_3 W1 I/O 3 IO_L3 7N_3 W2 I/O 3 IO_L3 7P_3 W3 I/O 3 IO_L35P_3 Y1 I/O 3 IP_.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 67 Pr oduct Specific ation R GND GND T14 GND GND GND T15 GND GND GND T19 GND GND GND T21 GND GND GND U6 GND GND GND U11 GND GND GND U1.
Pinout Descriptions 68 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os b y Bank T able 61 and Ta b l e 6 2 i ndic ates h ow the user-I /O pins ar e distr ibuted between the f our I/O b anks on the CS 484 package. The A WAKE pin is c ounted a s a Dual- Pur po se I/O .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 69 Pr oduct Specific ation R CS484 Footpr int Left Half of P acka ge (top vie w) 156 I/O: Unrestricted, general-purpos e user I/O. 41 INPUT : Unr estricted, general-purpos e input pin. 52 DU AL: Configuration, A WAKE pins, then possible user I/O.
Pinout Descriptions 70 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of CS484 P acka ge (top view) 12 13 14 15 16 17 18 19 20 21 22 INPU T I/O L11P_0 I/O L10P_0 .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 71 Pr oduct Specific ation R FG676: 676-Ball Fine-P itch Ball Gr id Arra y The 676 -ball fi ne-pitc h ball gr id array , FG67 6, sup por t s both the XC3S D1800A and th e XC3SD34 00A F PGAs.
Pinout Descriptions 72 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 0 IO_L22P _0 D16 I/O 0 IO_L21P _0 D17 I/O 0 IO_L17P _0 D18 I/O 0 IO_L11P _0 D20 I/O 0 IO_L10N_ 0 D21 I/.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 73 Pr oduct Specific ation R 0 VCCO_0 B16 VCCO 0 VCCO_0 B22 VCCO 1 IO_L01P _1/HDC Y20 DU AL 1 IO_L0 1N_1 /LDC 2 Y21 DUAL 1 IO_L13P _1 .
Pinout Descriptions 74 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IO_L50N_ 1 K21 I/O 1 IO_L46N_ 1 K22 I/O 1 IO_L46P _1 K23 I/O 1 IP_L40P_1 K24 INPUT 1 IO_L41P _1 K25 I.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 75 Pr oduct Specific ation R 2 IO_L46P _2 W17 I/O 2 IO_L09P _2 V10 I/O 2 IO_L13P _2 V11 I/O 2 IO_L16P _2 V12 I/O 2 IO_L20P _2 V13 I/O .
Pinout Descriptions 76 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 2 IO_L4 1N_2 AC20 I /O 2 IO_L4 5N_2 AC21 I /O 2 IO_2 A C22 I/O 2 IP_2/VREF_2 AB6 VREF 2 IO_L14N_ 2 AB7 .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 77 Pr oduct Specific ation R 3 IO_L48P _3 T10 I/O 3 IO_L36P _3/VREF_3 R1 VREF 3 IO_L36N_ 3 R2 I/O 3 IO_L37P _3 R3 I/O 3 IO_L37N_ 3 R4 .
Pinout Descriptions 78 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 3 IP_L04P_3 C2 INPUT 3 IO_L02N_ 3 B1 I/O 3 IO_L02P _3 B2 I/O 3 IP_L66P_3 AE1 INPUT 3 IP_L66N_3/VREF_3 A.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 79 Pr oduct Specific ation R GND GND F21 GND GND GND F26 GND GND GND C3 GND GND GND C9 GND GND GND C14 GND GND GND C19 GND GND GND C24.
Pinout Descriptions 80 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os by Bank T able 64 indi cates how the av ai lable user-I/O pi ns are distr ibuted between the four I/O banks o n the F G676 pa ckage. The A W AK E pin is coun ted as a Du al-P ur pose I/O.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 81 Pr oduct Specific ation R FG676 Footprint - XC3SD18 00A FPGA Left Half of Pac kage (top vie w) 314 I/O: Unrestricted, general-purpos e user I/O. 82 INPUT : Unr estricted, general-purpos e input pin.
Pinout Descriptions 82 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of FG676 P ackage (top view) 14 15 16 17 18 19 20 21 22 23 24 25 2 6 I/O L26N_0 GCL K7 I/O L.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 83 Pr oduct Specific ation R XC3SD3400A FPGA Ta b l e 6 5 l ists al l the FG 676 pa ckage pins for the XC3SD3400 A FPG A. They are sor ted by bank numb er and then by pin nam e. P air s of pins that form a differential I/O pair app ear togeth er in the table.
Pinout Descriptions 84 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 0 IO_L05P _0 D2 2 I/O 0 IO_L06P _0 D2 3 I/O 0 IO_L44P _0 C5 I/O 0 IO_L41N_ 0 C6 I/O 0 IO_L42N_ 0 C7 I/O.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 85 Pr oduct Specific ation R 1 IO_L12N_ 1 U18 I/O 1 IO_L12P _1 U1 9 I/O 1 IO_L10N_ 1 U20 I/O 1 IO_L14P _1 U2 1 I/O 1 IO_L21N_ 1 U22 I/.
Pinout Descriptions 86 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 1 IP_1/VREF_1 G2 5 VREF 1 IO_L58P_1/VR EF_1 F22 VREF 1 IO_L56N_ 1 F23 I/O 1 IO_L54N_ 1 F24 I/O 1 IO_L54.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 87 Pr oduct Specific ation R 2 IO_L48P_2 AF23 I/O 2 IO_L52P_2/D0 /DIN/MISO AF24 DUA L 2 IO_L51P_2 AF25 I/O 2 IO_L06P_2 AE3 I/O 2 IO_L0.
Pinout Descriptions 88 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R 2 VCCO_2 AB8 VCCO 2 VCCO_2 AB1 4 VCCO 2 VCCO_2 AB1 9 VCCO 3 IO_L53P_3 Y1 I/O 3 IO_L53N_3 Y2 I/O 3 IP_3 .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 89 Pr oduct Specific ation R 3 IO_L23N_3 K2 I/O 3 IO_L23P_3 K3 I/O 3 IO_L22N_3 K4 I/O 3 IO_L22P_3 K5 I/O 3 IO_L18P_3 K6 I/O 3 IO_L13P_.
Pinout Descriptions 90 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R GND GND P12 GND GND GND P16 GND GND GND P19 GND GND GND P24 GND GND GND N3 G ND GND GND N8 G ND GND GND.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 91 Pr oduct Specific ation R GND GND A23 GND GND GND A26 GND VCCA UX DONE AB21 CONFIG VCCA UX PROG_B A2 CONFIG VCCA UX TDI G7 JT AG VC.
Pinout Descriptions 92 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R User I/Os by Bank T able 66 indi cates how the av ai lable user-I/O pi ns are distr ibuted between the f our I/O banks on the FG 676 package. The A WAKE pin is c ounted a s a Dual- Pur po se I/O .
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 93 Pr oduct Specific ation R FG676 Footprint - XC3SD34 00A FPGA Left Half of Pac kage (top vie w) 314 I/O: Unrestricted, general-purpos e user I/O. 34 INPUT : Unr estricted, general-purpos e input pin.
Pinout Descriptions 94 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Right Half of FG676 P ackage (top view) 14 15 16 17 18 19 20 21 22 23 24 25 2 6 I/O L26N_0 GCL K7 I/O L.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 95 Pr oduct Specific ation R Footpr int Migration Di fferences There ar e multiple m igration footprin t differences be tween the XC3SD1 800A a nd the X C3SD34 00A in the FG676 package.
Pinout Descriptions 96 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R Migrat ion Recomm endations There ar e multiple p inout d ifferences be tween the XC3SD1800 A and the X C3SD3400A FPG As in the FG676 package.
Pinout Descriptions DS610-4 (v2.0) July 16, 2007 www .xil inx.com 97 Pr oduct Specific ation R Revi sion H istory The f ollo wing tab le sho ws the re vi sion hi stor y f or this docum ent. w ww . x ilinx.com/spartan3adsp Date V ers ion Revision 04/02/ 07 1.
Pinout Descriptions 98 www .xilinx. com DS610-4 (v 2.0) J uly 16, 2007 Produ ct Specificati on R This page intentionally left b lank..
An important point after buying a device Xilinx DS610 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Xilinx DS610 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Xilinx DS610 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Xilinx DS610 you will learn all the available features of the product, as well as information on its operation. The information that you get Xilinx DS610 will certainly help you make a decision on the purchase.
If you already are a holder of Xilinx DS610, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Xilinx DS610.
However, one of the most important roles played by the user manual is to help in solving problems with Xilinx DS610. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Xilinx DS610 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
