Instruction/ maintenance manual of the product M65881AFP Renesas
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Rev.1.00 2003.05.08 page 1 of 23 Digital Amplifier Processor of S - Master* Technology M65881AFP REJ03F0004-0100Z Rev.1.00 2003.05.08 DESCRIPTION The M65881AFP is a S - Master technique processor for .
Rev.1.00 2003.05.08 page 2 of 23 M65881AFP PIN CONFIGURATION VddL VssR VssL OUTL2 XOVdd XfsoOUT XOVss DVdd DVss MCKSEL SCDT SCSHIFT SCLATCH NSPMUTE INIT LRCK BCK DATA BFVdd SFLAG TEST2 TEST1 HPOUTR2 HPVssR HPOUTR1 HPVddR HPOUTL2 HPVssL HPOUTL1 HPVddL XVss XfsoIN XVdd VssLR OUTR2 OUTR1 VddR 1.
Rev.1.00 2003.05.08 page 3 of 23 M65881AFP BLOCK DIAGRAM M C K S E L F s o C K O F s o I X f s o O U T X f s o I N S F L A G OUTR1 OUTL1 OUTR2 OUTL2 Sampling Rate Converter Gain Control DATA BCK LRCK .
Rev.1.00 2003.05.08 page 4 of 23 M65881AFP ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ( Ta=25 º C, PWMVdd =3.3V, DVdd =1.8V : Unless otherwise specified.) ELECTRICAL CHARACTERISTICS Symbol Condition Min. Typ . Max Unit BFVdd 3.3 V system - 0.
Rev.1.00 2003.05.08 page 5 of 23 M65881AFP CHARACTERISTICS EVALUATION CIRCUIT OUTR2 OUTR1 16 17 18 + - + - - + M65881AFP 39 41 OUTL1 OUTL2 - + + - + - - + 2 4 HPOUTL1 HPOUTL2 - + + - 33 31 HPOUTR2 HPOUTR1 27 29 GND Power Supply GND GND Reference characteristic S/N THD+N 102 dB( typ ) 0.
Rev.1.00 2003.05.08 page 6 of 23 M65881AFP PIN DESCRIPTION Pin No. Name I/O Output Current on 3.3V Signal Level 1 VddL Power Supply for Lch PWM Power Stage (3.3V) – 2 OUTL1 O Lch PWM1 Output for Power Stage 3.3 V 3 VssL GND for Lch PWM Power Stage 4 OUTL2 O Lch PWM2 Output for Power Stage 3.
Rev.1.00 2003.05.08 page 7 of 23 M65881AFP EXPLANATION OF OPERATION DATA,BCK, and LRCK are input pins for Digital Audio Signal of CD , MD, DVD etc.. Input formats are supported by 4 ways, and are set by Serial Con trol, "System1 Mode, bit3 and bit4".
Rev.1.00 2003.05.08 page 8 of 23 M65881AFP SCDT, SCSHIFT and SCLATCH are input pins for setting M65881AFP's operation. Input format of SCDT, SCSHIFT and SCLATCH is shown below. Input Format of SCDT, SCSHIFT and SCLATCH • Mode Setting The operating mode are classified in four and assigned by bit1 a nd bit2.
Rev.1.00 2003.05.08 page 9 of 23 M65881AFP FsoCKO is clock output pin of 1fso frequency. The output is divided - clock of XfsoIN , and frequency is free - running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65881AFP, take a synchronization between M6588 1AFP and other external devices.
Rev.1.00 2003.05.08 page 10 of 23 M65881AFP OUTL1, OUTL2, OUTR1 and OUTR2 are pulse output modulated ∆Σ output to PWM signal. These pins are connected to external Power Driver ICs.The PWM ou tput can be selected PWM Output Format 1, 2, 3 and 4 by serial control data(System1 m ode, bit22,23 ).
Rev.1.00 2003.05.08 page 11 of 23 M65881AFP HPOUTL1, HPOUTL2, HPOUTR1 and HPOUTR2 are output pins for Headph one output. PWM output modulated ∆Σ output data to pulse width. The Phase of PWM Output for Power Stage and PWM Output for Head phone. The output for Headphone is reverse phase as output for Power.
Rev.1.00 2003.05.08 page 12 of 23 M65881AFP 13. Power sequences System power - on sequencing * Refer to following figure. X X X X X Power( Vddxxx , HPVddxxx , XVdd , XOVdd , DVdd , BFVdd ) Master cloc.
Rev.1.00 2003.05.08 page 13 of 23 M65881AFP SERIAL CONTROL bit Flag name Functional Explanation H L INIT 1 MODE1 Mode setting1 " L" fixed – 2 MODE2 Mode setting2 " L" fixed – 3.
Rev.1.00 2003.05.08 page 14 of 23 M65881AFP The index and Mantissa part of Gain Data (bit12 - bit24 :GAIN0 - GAIN12) The gain value is set from bit12 - bit24. Index part: bit12(MSB) to bit16(LSB) Mantissa part: bit17(MSB) to bit24(LSB) The gain data is assigned 13bits, composed of Index par t 5bits and of Mantissa part 8bits.
Rev.1.00 2003.05.08 page 15 of 23 M65881AFP • Soft Mute The Soft Mute function is executed by setting of Gain Data as 00 000/00000000b (" / " means dividing point between index part and mantissa part ). The release from Soft Mute Function must be executed by setting the gain data before soft mute.
Rev.1.00 2003.05.08 page 16 of 23 M65881AFP Table 2 - 1 Selection of input format Table 2 - 2 Setting for Input Data Word Length Table 2 - 3 Selection of Input Sampling Rate ( fsi :32k to 48kHz, 2fsi:.
Rev.1.00 2003.05.08 page 17 of 23 M65881AFP Fs Selection for De - emphasis filter (De - emphasis is "ON" except for bit9="L" and bit10="L".
Rev.1.00 2003.05.08 page 18 of 23 M65881AFP 3. System2 Mode No setting bits means "Don't care". Table 3 - 1 DC dithering selection at ∆Σ block Table 3 - 2 AC dithering selection at .
Rev.1.00 2003.05.08 page 19 of 23 M65881AFP Flag to " Enable " of Asynchronous Detection for secondary block ( bit8: ASYNCEN2) ASYNCEN2 (bit8 ) controls " Enable" and " Disable" for seco ndary asynchronous detector.
Rev.1.00 2003.05.08 page 20 of 23 M65881AFP AC CHARACTERISTICS ( Ta=25 º C, PWMVdd =3.3V, DVdd =1.8V) AC CHARACTERISTICS TIMING CHART (1) XfsoIN , XfsiIN Duty Ratio (2) SCSHIFT, SCDT, SCLATCH Input T.
Rev.1.00 2003.05.08 page 21 of 23 M65881AFP APPLICATION EXAMPLE Low Pass Filter / Headphone Amplifier Input Mode Select1 Secondary synchronized clock (For Multi channel ) Secondary Clock Select L:1024.
Rev.1.00 2003.05.08 page 22 of 23 M65881AFP DETAILED DIAGRAM OF PACKAGE OUTLINE SSOP42-P-450-0.80 W eight(g) –– JEDEC Code EIAJ P ac kage Code Lead Material Cu Allo y+42 Allo y 42P2R-E Plastic 42pin 450mil SSOP Symbol Min Nom Max A A 2 b c D E L L 1 y Dimension in Millimeters H E A 1 I 2 – – .
Rev.1.00 2003.05.08 page 23 of 23 M65881AFP Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. http://www. renesas .
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