Instruction/ maintenance manual of the product DS33R11 Maxim
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceive r ww w .maxim-ic.com GENERAL DESCRIPTION The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. The device performs store-and-forward of packets with full wire-speed transport capability.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 2 of 344 TABLE OF CONTENTS 1 DESCRIPTION ............................................................................................................................... .... 9 2 FEATURE HIGHLIGHTS .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 3 of 344 9.14.1 DTE and DCE Mode ............................................................................................................................. 58 9.15 E THER NET MAC .......
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 4 of 344 10.17.4 FIFO Information ............................................................................................................................... ....96 10.17.5 Receive Packet-Bytes Available .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 5 of 344 12.4 E1 M ODE ............................................................................................................................... ..... 308 13 OPERATING PARAMETERS ....
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 6 of 344 LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 7 of 344 Figure 12-19. Transmit-Side 2.048MHz B oundary Timing (Elastic Store Enabled) ................................................ 307 Figure 12-20. Receive-Side Timing ...............
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 8 of 344 LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 9 of 344 1 DESCRIPTION The DS33R11 provides interconnection and mapping functi onality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM ) systems.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 10 of 344 The integrated Ethernet Mapper is software compatible wi th the DS33Z11 Ethernet mapper. There are a few things to note when porting a DS33Z11 application to this device: • The SPI and hardware modes are not supported.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 11 of 344 2 FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 12 of 344 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 13 of 344 2.9 T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 14 of 344 2.12 T1/E1/J1 Framer • Fully independent transmit and receive functionality • Full receive and transmit path transparency .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 15 of 344 2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom pattern.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 16 of 344 2.15 Specifications Compliance The DS33R11 meets relevant telecommuni cations specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 17 of 344 3 APPLICATIONS The DS33R11 is ideal for application areas such as trans parent LAN service, LAN ext ension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1 /EC-1, G.SHDSL, or HDSL2/4.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 18 of 344 4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interfac.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 19 of 344 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit para llel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 20 of 344 6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram TTIP TRING RTIP RRING SYSCLKI (RMII MODE) RXD[0:1] RX_CLK CRS_DV RX_ERR REF_CLK .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 21 of 344 Figure 6-2. Block Diagra m of T1/E1/J1 Transceiver TX LIU CLO C K ADAPT ER BACKPL ANE INTERFACE CIRCUIT HOST I NTE RF AC E T1/ E.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 22 of 344 Figure 6-3. Receive and Transmit T1/E1/J1 LIU LOCAL LOOPBACK TRI NG TTIP JI TTER AT TENU ATOR TRAN SMIT OR RECEI VE PATH RECEIVE LINE I/F RRING RTIP REMOTE LO OPBACK VCO / PLL MCLK 8XCLK 32 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 23 of 344 Figure 6-4. Receive and Transmit T1/E1/J1 Framer RECEIVE FRAM ER TRAN SMIT FRAM ER DATA CLOCK SYNC SYNC CLOCK DATA FRAME R LOOP .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 24 of 344 Figure 6-5. T1/E1/J1 Backplane Interface RLINK RLCLK RSIG RSIGFR RSERO RCLKO RSYNC RDATA RFSYN C RMSYNC ELASTIC STORE SIGNAL ING.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 25 of 344 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 26 of 344 NAME PIN TYPE FUNCTION RD / DS B11 I Read Data Strobe (Intel Mode): The DS33R11 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 27 of 344 NAME PIN TYPE FUNCTION MII/RMII PHY PORT COL_DET N18 I Collision Detect (MII): Asserted by the MAC PHY to indicate that a collision is occurring. In DCE Mode this signal should be connected to ground.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 28 of 344 NAME PIN TYPE FUNCTION TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 O Transmit Data 0 through 3(MII): TXD [3:0] is presented synchronously with the rising edge of TX_CLK. TXD [0] is the least significant bit of the data.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 29 of 344 NAME PIN TYPE FUNCTION PHY MANAGEMENT BUS MDC C19 O Management Data Clock (MII): Clocks management data between the PHY and DS33R11. The clock is derived from theSYSCLKI, with a maximum frequency is 1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 30 of 344 NAME PIN TYPE FUNCTION SDATA[0] W2 SDATA[1] Y4 SDATA[2] Y2 SDATA[3] Y5 SDATA[4] Y3 SDATA[5] W5 SDATA[6] V5 SDATA[7] W6 SDATA[8] .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 31 of 344 NAME PIN TYPE FUNCTION T1/E1/J1 ANALOG LINE INTERFACE TTIP R1, R2 O Transmit Analog Tip Output for the T1/E1/J1 Transceiver: Analog line-driver outputs. Tw o connections are provided to improve signal quality.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 32 of 344 NAME PIN TYPE FUNCTION TSIG B4 I Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 33 of 344 NAME PIN TYPE FUNCTION RSYNC G4 I/O Receive Sy nc for the T1/E1/J1 Transceiver: An extracted pulse, one RCLKO wide, is output at this pi n, which identifies either frame (TR.IOCR1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 34 of 344 NAME PIN TYPE FUNCTION ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI H1 I Receive Serial Data Input to Ethernet Mapper: Receive Serial data arrives on the rising edge of RCLKI. Normally connected to RSERO.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 35 of 344 NAME PIN TYPE FUNCTION TDCLKO C2 O Transmit Clock Output from the T1/E1/J1 Framer: Buffered clock that is used to clock data through the transmit-side formatter (either TCLKT or RDCLKI).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 36 of 344 NAME PIN TYPE FUNCTION HARDWARE AND STATUS PINS LIUC B2 I Line Interface Unit Connect: When a logic low is present on this input pin, the T1/E1/J1 Fram er and LIU are not internally connected.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 37 of 344 NAME PIN TYPE FUNCTION SYSTEM CLOCKS SYSCLKI V8 I System Clock In for Ethernet Mapper: 100MHz System Clock input to the DS33R11, used for internal operation. This clock is buffered and provided at SDCLKO for the SDRAM interface.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 38 of 344 NAME PIN TYPE FUNCTION JTAG INTERFACE JTCLK1 A7 Ipu JTAG Clock 1 for the Ethernet Mapper: This signal is used to shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 39 of 344 NAME PIN TYPE FUNCTION POWER SUPPLIES RVDD K3, L1 — Receive Analog Positive Supply : Connect to 3.3V power supply. RVSS J1, J2, K2, L2, M2 — Receive Analog Signal Ground: Connect to the common supply ground.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 40 of 344 Figure 7-1. 256-Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A RCHBLK TCHBLK RFSYNC TDATA TSSYNC JT CLK2 JTCLK1 RS T N.C. INT CS D6 D3 D0 VSS A6 A3 A0 REF_CLK REF_ CLKO B BPCLK LIUC TPOSI T SIG RCL JT DI2 JTDO1 JTRST2 J TMS2 VDD1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 41 of 344 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functi onality between Ethernet packet LANs and T1/E1/J1 WAN Time-Division Multiplexed (TDM ) systems.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 42 of 344 Both the transmit and receive path of the integrated T1/E 1/J1 transceiver also have two HDLC controllers. The HDLC controllers transmit and receive data through the fr amer block.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 43 of 344 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 44 of 344 Figure 9-1. Clocking for the DS33R11 TTIP TRING RTIP RRING SYSCLKI REF_CLKO RX_CLK REF_CLK TX_CLK MDC MCLK XTALD 8XCLK BPCLK TDC.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 45 of 344 9.1.1 Ethernet Interface Clock Modes The Ethernet PHY interface has several different cl ocking requirements, depending on the mode of operation. Table 9-1 outlines the possible clocking modes for the Ether net Interface.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 46 of 344 9.2 Resets and Low Pow er Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the GL.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 47 of 344 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section 9.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 48 of 344 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pi n.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 49 of 344 Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet 7 Receive A borted Packet 6 Receive Inv alid Pa.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 50 of 344 9.7 Interrupt Information Registers The interrupt information registers provide an indicati on of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the hos t can read TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 51 of 344 9.11 Connections and Queues The multi-port devices in this product family provide bidirectional cross-c onnections between the multiple Ethernet ports and Serial ports when operating in software mode.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 52 of 344 It is recommended that the user reset the queue pointers fo r the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/c onnect procedure is not followed, incorrect data may be transmitted.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 53 of 344 9.13 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11 allows for optional flow control based on the queue high wa termark or through host processor intervention.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 54 of 344 9.13.1 Full Duplex Flow Control Automatic flow control is enabled by default. The hos t processor can disable this functionality with SU.GCR .ATFLOW. The flow control mechanism is governed by the high watermarks ( SU.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 55 of 344 Figure 9-3. Flow Control Using Pause Control Frame Receive Queue Growth Receive Queue High W ater Mark Initiate Flo w con trol 8 Rx Data Receive Queue Low Wa te r 9.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 56 of 344 9.14 Ethernet Interface Port The Ethernet port interface allows for direct connecti on to an Ethernet PHY. The interface consists of a 10/100Mbit/s MII/RMII interface and an Ethernet MAC.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 57 of 344 The MAC circuitry generates a frame status for every frame t hat is received. This real time status can be read by SU.RFSB0 to SU.RFSB3 . Note the frame status is the “real ti me” status and hence the value will change as new frames are received.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 58 of 344 9.14.1 DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE m ode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 59 of 344 Figure 9-6. DS33R11 Configured as a DCE in MII Mode MAC TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_ER R RX_ERR TX_EN RX_CRS COL_DET COL_DET DTE DCE TX_EN RX DV MDC MDIO TXD[3:0] RXD[3:0] TX_CLK DS33Z11 MAC RX_CLK RXDV RX_CRS MDIO MDC Rx Tx Tx Rx 9.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 60 of 344 Table 9-6. MAC Control Registers ADDRESS REGISTER DESCRIPTION 0000h-0003h SU.MACCR MAC Control Register. This register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 61 of 344 9.15.1 MII Mode Options The Ethernet interface can be configured for MII operati on by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocki ng the Ethernet Interface while in MII mode, see Section 9.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 62 of 344 9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 63 of 344 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receiv e pattern generator to the incoming pattern.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 64 of 344 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization sync hronizes the receive pattern generator to the incoming repetitive pattern.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 65 of 344 9.16.4.1 Error Insertion Error insertion inserts errors into t he outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interf ace.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 66 of 344 9.18 Receive Packet Processor The Receive Packet Processor accepts data from the Re ceive Serial Interface performs packet descr.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 67 of 344 Bit reordering changes the bit order of each byte. If bit reordering is dis abled, the incoming 8-bit data stream DT[1:8] with D.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 68 of 344 9.19 X.86 Encoding and Decoding X.86 protocol provides a method fo r encapsulating Ethernet Frame onto L APS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 69 of 344 Figure 9-13. X.86 Encapsulation of the MAC frame Flag(0x7E) Address(0x04) Control(0x03) 1st Octect o f SAPI(0xfe ) 2nd Octect of.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 70 of 344 The X86 received frame is aborted if: • If 7d,7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 71 of 344 9.20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used rest ricts the transport of received MAC data to a programmable rate.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 72 of 344 10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 73 of 344 Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 TRANSMIT CLOCK SOURCE 0 0 The TCLKT pin (C) is always the source of transmit clock. 0 1 Switch to the recovered clock (B ) when the signal at the TCLKT pin fails to transition after one channel time.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 74 of 344 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control regist ers. Typically, the control registers are only accessed when the system is first pow ered up.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 75 of 344 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 76 of 344 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control regist ers. Typically, the control registers are only accessed when the system is first powered up.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 77 of 344 10.5.1 Automatic Alarm Generation The device can be programmed to automatically transmit AI S or remote alarm.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 78 of 344 10.7 Error Counters The transceiver contains four c ounters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options incl ude one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 79 of 344 10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF fram ing mode, TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 80 of 344 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) In T1 mode, TR.FOSCR is used to count the number of mult iframes that the receive sy nchronizer is out of sync.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 81 of 344 10.8 DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64k bps channel in the transmit direction and one DS0 channel in the receive direction at the same time.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 82 of 344 10.9 Signaling Operation There are two methods to access receive signaling dat a and provide transmit signaling data, processor-based (software-based) or hardware-based.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 83 of 344 10.9.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 84 of 344 Figure 10-3. Simplified Diagram of Transmit Signaling Path TRANSM I T SIGNA LING RE GI ST ERS SIGNA LING BUF FER S PER-CH ANNEL CONTROL TSER TSI G T1/E1 DATA STREA M PER-CHA NNEL CONTROL TR .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 85 of 344 10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. Th is information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 86 of 344 10.10 Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 87 of 344 10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 88 of 344 10.11 Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/T R.RCBR2/TR.RCBR3/TR.RCBR4 ) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR 3/TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 89 of 344 10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for informati on about clock and I/O configurations. The operation of the transmit elastic store is very sim ilar to the receive side.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 90 of 344 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 91 of 344 10.14 T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 92 of 344 10.15 Additional (Sa) and Internati onal (Si) Bit Operation (E1 Only) When operated in the E1 mode, the tran sceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 93 of 344 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FD L (T1 mode).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 94 of 344 Table 10-12. HDLC Controller Registers REGISTER FUNCTION CONTROL AND CONFIGURATION TR.H1TC , HDLC #1 Transmit Control Register TR.H2TC , HDLC #2 Transmit Control Register General control over the transmit HDLC controllers TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 95 of 344 10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 96 of 344 10.16.4 FIFO Information The transmit FIFO buffer-available register indicates the num ber of bytes that can be written into the transmit FIFO.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 97 of 344 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver main tains the circuitry that existed in the previous generation of the T1 framer.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 98 of 344 10.17.3 Transmit Section The transmit section shifts out into the T1 data stream eit her the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 99 of 344 10.19 Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeati ng bit pattern from one to eight bits or 16 bits in length.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 100 of 344 10.20 Line Interface Unit (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuat or.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 101 of 344 10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports the signal strengt h at RTIP and RRING in 2.5dB in crements through RL3–RL0 located in Information Register 2 (TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 102 of 344 10.20.3 Transmitter The transceiver uses a phase-lock loop along with a prec ision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 103 of 344 10.21 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz cl ock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 104 of 344 10.24 Recommended Circuits Figure 10-7. Basic Interface Refer to Application Note 324: T1/E1 Network Interface Design for more information on protected interfaces. TTIP TRING RTIP RRING DVDD TVDD RVDD VDD DVSS TVSS RVSS DS33R11 R R 2:1 1:1 C 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 105 of 344 Figure 10-8. E1 Transmit Pulse Template 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 TIME (ns) SCALED AMPLITUDE 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (IN 75 Ω SYSTEMS, 1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 106 of 344 Figure 10-10. Jitter Tolerance FREQUENCY (Hz) UNIT INTERVALS (UI P-P ) 1k 100 10 1 0.1 10 100 1k 10k 100k DEVICE TOLERANCE 1 TR 62411 (DEC. 90) ITU-T G. 823 Figure 10-11. Jitter Tolerance (E1 Mode) FREQUENCY (Hz) UNIT INTERVALS (UI P-P ) 1k 100 10 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 107 of 344 Figure 10-12. Jitter Attenuation (T1 Mode) FREQUE NCY (Hz) 0dB -20dB -40dB -60dB 1 10 100 1K 10K JITTER ATT ENUATION (dB) 100K TR 62 41 1 (De c . 9 0) Pr ohibit ed A rea C u r v e B Curve A T1 MOD E Figure 10-13.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 108 of 344 Figure 10-14. Optional Crystal Connections XTALD C1 C2 1.544MHz/2.048MHz MCLK NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 109 of 344 Figure 10-15. Simplified Diagram of BERT in Network Direction PER-CHANNEL AND F-BIT (T1 MODE) MAPPING BERT TRANSMITTER BERT RECEIVER 1 0 FROM RECEIVE FRAMER TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM TRANSMIT SYSTEM BACKPLANE INTERFACE TO TRANSMIT FRAMER Figure 10-16.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 110 of 344 10.25.3 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 111 of 344 10.26 Payload Error-Insertion Function (T1 Mode Only ) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 112 of 344 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer t hat generates a user-selectabl e clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO ).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 113 of 344 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram ESCR. 4 TESE TSER TSIG HSIE1-3 through PCPR TX ESTORE Off-Chip Connecti on RDATA From T1_rcv_l ogic LBCR1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 114 of 344 B8ZS Encoding Bipolar/ NRZ coding T1TCR2.7 B8ZSE IOCR1.0 ODF 1/2 CLK/ FULL CLK CCR1.4 ODM TPOS TNEG FDL Mux ESF Yellow From BOC Mux From F-bit Mux From ESF Yellow Alarm TFPT T1TCR1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 115 of 344 Figure 10-18. E1 Transmit Flow Diagram TSER TSIG HSIE1-4 through PCPR TX ESTO RE ESCR.4 TESE TESO TDATA Off-Chip Connect ion RDATA From E1_rcv _logic LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 116 of 344 Per-Channel Loopback From Idle Code Mux RDATA From E1_rcv_logic PCLR1-4 Sa-bit Mux TNAF THMS1 THMS2 H1TC.4 H2TC.4 TS0 Mux TAF/TNAF(non Sa) Si-bit Mux E1TCR1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 117 of 344 11 DEVICE REGISTERS Ten address lines are used to address the register space. Table 11-1 shows the register map for the DS33R11. The addressable range for the device is 0000h to 08FFh.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 118 of 344 11.1 Register Bit Maps Table 11-2 , Table 11-3 , Table 11-4 , Table 11-5 , Table 11-6 , and Table 11-7 contain the regist ers of the DS33R11. Bits that are reserved are noted with a single dash “-“.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 119 of 344 11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 40h AR . R QS C 1 RQSC7 RQSC6 RQSC5 RQSC4 RQSC3 RQSC2 RQSC1 RQSC0 41h AR .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 120 of 344 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C0h LI.TSLCR - - - - - - - TDENPLT 0C1h LI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 121 of 344 A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 114h LI.RSPCB0 RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 115h LI.RSPCB1 RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 116h LI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 122 of 344 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 140h SU.MACRA DL MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 141h SU.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 123 of 344 11.1.6 MAC Register Bit Map Table 11-7. MAC Indir ect Register Bit Map A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0000h SU.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 124 of 344 A DDR N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 112h RESERVED – initialize to FF Reserved Reserved Reser.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 125 of 344 Table 11-8. T1/E1/J1 Transceiver Re gister Bit Map (Active when CST = 0) A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 000 h TR.MSTRREG — — — — TEST1 TEST0 T1/E1 SFTRST 001 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 126 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 01A h TR.SR3 LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA 01B h TR.IMR3 LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA 01C h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 127 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 035 h TR.E1TCR1 TFPT T16S TUA1 TSi S TSA1 THDB3 TG802 TCRC4 036 h TR.E1TCR2 Reserved Reserved Reserved Reserved Reserved AEBE AAIS ARA 037 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 128 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 h 050 h TR.TS1 Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition. 051 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 129 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 06A h TR.RS11 Receive Signaling Bit Format Changes With Op erating Mode. See Register Definition. 06B h TR.RS12 Receive Signaling Bit Format Changes With Op erating Mode.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 130 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 085 h TR.RCICE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 086 h TR.RCICE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 087 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 131 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0A0 h TR.H2TC NOFS TEOML THR THMS TFS TEOM TZSD TCRCD 0A1 h TR.H2FC — — TFLWM2 TFLWM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 0A2 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 132 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C1 h TR.TFDL TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0 0C2 h TR.RFDLM1 RFDLM7 RFDLM6 RFDLM5 RFDLM4 RFDLM3 RFDLM2 RFDLM1 RFDLM0 0C3 h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 133 of 344 A DD R N AM E B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0DC h TR.BRP1 RPAT7 RPAT6 RPAT5 RPAT4 RPAT3 RPAT2 RPAT1 RPAT0 0DD h TR.BRP2 RPAT15 RPAT14 RPAT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 0DE h TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 134 of 344 11.2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: fram er reset, LIU reset, device ID, and BERT interrupt status.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 135 of 344 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name - - - - .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 136 of 344 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity Latched Status Register Ad.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 137 of 344 Register Name: GL.LIS Register Description: Global Serial Interface Interrupt Status Register Address: 07h Bit # 7 6 5 4 3 2 1 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 138 of 344 Register Name: GL.TRQIE Register Description: Global Transmit Receive Queue Interrupt Enable Register Address: 0Ah Bit # 7 6 5 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 139 of 344 Register Name: GL.BIS Register Description: Global BERT Interrupt Status Register Address: 0Dh Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - BIS Default 0 0 0 0 0 0 0 0 Bit 0: BERT Interrupt Status (BIS) This bit is set to 1 if the BERT has an enabled interrupt generating event.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 140 of 344 Register Name: GL.C1QPR Register Description: Connection 1 Queue Pointer Reset Register Address: 12h Bit # 7 6 5 4 3 2 1 0 Name.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 141 of 344 Register Name: GL.BISTPF Register Description: BIST Pass-Fail Register Address: 21h Bit # 7 6 5 4 3 2 1 0 Name - - - - - - BISTDN BISTPF Default 0 0 0 0 0 0 0 0 Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has comp leted the BIST Test initiated by BISTE.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 142 of 344 Register Name: GL.SDMODE2 Register Description: Global SDRAM Mode Register 2 Register Address: 3Bh Bit # 7 6 5 4 3 2 1 0 Name -.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 143 of 344 11.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 144 of 344 11.4 BERT Registers Register Name: BCR Register Description: BERT Control Register Register Address: 80h Bit # 7 6 5 4 3 2 1 0 Name - PMU RNPL RPIC MPR APRD TNPL TPIC Default 0 0 0 0 0 0 0 0 Bit 7: This bit must be kept low for proper operation.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 145 of 344 Register Name: BPCLR Register Description: BERT Pattern Configuration Low Register Register Address: 82h Bit # 7 6 5 4 3 2 1 0 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 146 of 344 Register Name: BSPB0R Register Description: BERT Pattern By te0 Register Register Address: 84h Bit # 7 6 5 4 3 2 1 0 Name BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0 Default 0 0 0 0 0 0 0 0 Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 147 of 344 Register Name: TEICR Register Description: Transmit Error Insertion Control Register Register Address: 88h Bit # 7 6 5 4 3 2 1 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 148 of 344 Register Name: BSRL Register Description: BERT Status Register Latched Register Address: 8Eh Bit # 7 6 5 4 3 2 1 0 Name - - - -.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 149 of 344 Register Name: RBECB0R Register Description: Receive Bit Error Count By te 0 Register Register Address: 94h Bit # 7 6 5 4 3 2 1 0 Name BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 150 of 344 Register Name: RBCB1 Register Description: Receive Bit Count By te 1 Register #1 Register Address: 99h Bit # 7 6 5 4 3 2 1 0 Name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Bit Count (BC[8:15]) Eight bits of a 32 bit value.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 151 of 344 11.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport ci rcuitry and the associated serial port. The Serial Interface register map consists of registers that are comm on functions, transmit functi ons, and receive functions.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 152 of 344 Register Name: LI.LPBK Register Description: Serial Interface Loopback Control Register Register Address: 0C2h Bit # 7 6 5 4 3 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 153 of 344 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping Control Register Register Address: 0C5h Bit # 7 6 5 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 154 of 344 Register Name: LI.TEPHC Register Description: Transmit Errored Packet High Control Register Register Address: 0C7h Bit # 7 6 5 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 155 of 344 Register Name: LI.TPPSR Register Description: Transmit Packet Processor Status Register Register Address: 0C8h Bit # 7 6 5 4 3 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 156 of 344 Register Name: LI.TPCR0 Register Description: Transmit Packet Count By te 0 Register Address: 0CCh Bit # 7 6 5 4 3 2 1 0 Name TPC7 TPC6 TPC5 TPC4 TPC3 TPC2 TPC1 TPC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 157 of 344 Register Name: LI.TBCR0 Register Description: Transmit By te Count Byte 0 Register Address: 0D0h Bit # 7 6 5 4 3 2 1 0 Name TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 158 of 344 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 159 of 344 11.5.2 X.86 Registers X.86 transmit and common registers are used to c ontrol the operation of the X.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 160 of 344 Register Name: LI.TRX86SAPIL Register Description: Transmit Receive X.86 SAPIL Register Address: 0DCh Bit # 7 6 5 4 3 2 1 0 Nam.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 161 of 344 11.5.3 Receive Serial Interface Serial Receive Registers are used to control the HDLC Rece iver associated with each Seri al Interface. Note that throughout this document HDLC Processor is also refe rred to as “Packet Processor”.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 162 of 344 Register Name: LI.RMPSCL Register Description: Receive Maximum Packet Size Control Low Register Register Address: 102h Bit # 7 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 163 of 344 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Status Register Latched Register Address: 105h Bit # 7 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 164 of 344 Register Name: LI.RPPSRIE Register Description: Receive Packet Processor Status Register Interrupt Enable Register Address: 106.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 165 of 344 Register Name: LI.RPCB0 Register Description: Receive Packet Count By te 0 Register Register Address: 108h Bit # 7 6 5 4 3 2 1 0 Name RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 166 of 344 Register Name: LI.RFPCB0 Register Description: Receive FCS Errored Packet Count By te 0 Register Register Address: 10Ch Bit # 7.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 167 of 344 Register Name: LI.RAPCB0 Register Description: Receive Aborted Packet Count By te 0 Register Register Address: 110h Bit # 7 6 5.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 168 of 344 Register Name: LI.RSPCB0 Register Description: Receive Size Violation Packet Count By te 0 Register Register Address: 114h Bit .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 169 of 344 Register Name: LI.RBC0 Register Description: Receive Byte Count 0 Register Register Address: 118h Bit # 7 6 5 4 3 2 1 0 Name RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 Default 0 0 0 0 0 0 0 0 Bits 0 - 7: Receive By te Count (RBC [7:0]) Eight bits of a 32-bit value.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 170 of 344 Register Name: LI.RAC0 Register Description: Receive Aborted Byte Count 0 Register Register Address: 11Ch Bit # 7 6 5 4 3 2 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 171 of 344 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 172 of 344 Register Name: LI.RX86LSIE Register Description: Receive X.86 Interrupt Enable Register Address: 123h Bit # 7 6 5 4 3 2 1 0 Name - - - - SAPINE01IM SAPINEFEIM CNE3LI M ANE4IM Default 0 0 0 0 0 0 0 0 Bit 3: SAPI Octet not equal to LI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 173 of 344 Register Name: LI.TQTIE Register Description: Serial Interface Transmit Queue Cross Threshold Interrupt Enable Register Address.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 174 of 344 11.6 Ethernet Interface Registers The Ethernet Interface registers are used to configur e RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addr essed directly from the Processor port.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 175 of 344 Register Name: SU.MACRD1 Register Description: MAC Read Data By te 1 Register Address: 143h Bit # 7 6 5 4 3 2 1 0 Name MACRD15 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 176 of 344 Register Name: SU.MACWD1 Register Description: MAC Write Data 1 Register Address: 147h Bit # 7 6 5 4 3 2 1 0 Name MACWD15 MACWD.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 177 of 344 Register Name: SU.MACAWH Register Description: MAC Address Write High Register Address: 14Bh Bit # 7 6 5 4 3 2 1 0 Name M A C A.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 178 of 344 Register Name: SU.LPBK Register Description: Ethernet Interface Loopback Control Register Register Address: 14Fh Bit # 7 6 5 4 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 179 of 344 Register Name: SU.TFRC Register Description: Transmit Frame Resend Control Register Address: 151h Bit # 7 6 5 4 3 2 1 0 Name - .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 180 of 344 Register Name: SU.TFSL Register Description: Transmit Frame Status Low Register Address: 152h Bit # 7 6 5 4 3 2 1 0 Name UR EC .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 181 of 344 Register Name: SU.RFSB0 Register Description: Receive Frame Status By te 0 Register Address: 154h Bit # 7 6 5 4 3 2 1 0 Name FL.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 182 of 344 Register Name: SU.RFSB3 Register Description: Receive Frame Status By te 3 Register Address: 157h Bit # 7 6 5 4 3 2 1 0 Name MF.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 183 of 344 Register Name: SU.RMFSRL Register Description: Receiver Maximum Frame Low Register Register Address: 158h Bit # 7 6 5 4 3 2 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 184 of 344 Register Name: SU.QRIE Register Description: Receive Queue Cross Threshold enable Register Address: 15Ch Bit # 7 6 5 4 3 2 1 0 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 185 of 344 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control Register Address: 15Eh Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 186 of 344 11.6.2 MAC Registers The control Registers related to the control of the individual Mac’s are s hown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 187 of 344 Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retr ansmission of late collisions is disabled.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 188 of 344 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Address Register Register Address: 0014h (indirect) 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 189 of 344 Register Name: SU.MACMIID Register Description: MAC MII (MDIO) Data Register Register Address: 0018h (indirect) 0018h: Bit # 31.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 190 of 344 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Register Address: 001Ch (indirect) 001Ch: Bit # 31 30 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 191 of 344 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Register Address: 0100h (indirect) 0100h: Bit # 31 30 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 192 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 010Ch (indirect) 010Ch: Bit # 31 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 193 of 344 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 0110h (indirect) 0110h: Bit # 31 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 194 of 344 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Counter Register Address: 0200h (indirect) 0200h: Bit .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 195 of 344 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counter Register Address: 0204h (indirect) 0204h: Bit.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 196 of 344 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted Counter Register Address: 0300h (indirect) 0300h: B.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 197 of 344 Register Name: SU.TxBytesCtr Register Description: MAC All By tes Transmitted Counter Register Address: 0308h (indirect) 0308h:.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 198 of 344 Register Name: SU.TxBytesOkCtr Register Description: MAC By tes Transmitted OK Counter Register Address: 030Ch (indirect) 030Ch.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 199 of 344 Register Name: SU.TxFrmUndr Register Description: MAC Transmit Frame Under Run Counter Register Address: 0334h (indirect) 0334h.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 200 of 344 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted Counter Register Address: 0338h (indirect) 0338h: Bit.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 201 of 344 11.7 T1/E1/J1 Transceiver Registers Register Name: TR.MSTRREG Register Description: Master Mode Register Register Address: 00h .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 202 of 344 Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 5 4 3 2 1 0 Name RSM.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 203 of 344 Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name RCL.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 204 of 344 Register Name: TR.T1RCR1 Register Description: T1 Receive Control Register 1 Register Address: 03h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 205 of 344 Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 206 of 344 Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 207 of 344 Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 208 of 344 Register Name: TR.T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 5 4 3 2 1 0 Name — — — TRAI-CI TAIS-CI TFM PDE TLOOP Default 0 0 0 0 0 0 0 0 Bit 4: Transmit RAI-CI Enable (TRAI-CI).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 209 of 344 Register Name: TR.SSIE1 (E1 Mode) Register Description: Softw are Signaling Insertion Enable 1 Register Address: 08h Bit # 7 6 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 210 of 344 Register Name: TR.SSIE3 (T1 Mode) Register Description: Softw are Signaling-Insertion Enable 3 Register Address: 0Ah Bit # 7 6 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 211 of 344 Register Name: TR.T1RDMR1 Register Description: T1 Receive Digital-Milliwatt Enable Register 1 Register Address: 0Ch Bit # 7 6 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 212 of 344 Register Name: TR.IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default 1 0 1 1 X X X X Bits 4 - 7: Device ID (ID4 to ID7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 213 of 344 Register Name: TR.INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 5 4 3 2 1 0 Name BSYNC BD TCLE TOCD RL3 RL2 RL1 RL0 Default 0 0 0 0 0 0 0 0 Bit 7: BERT Real-Time Sy nc hronization Status (BSYNC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 214 of 344 Register Name: TR.INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 5 4 3 2 1 0 Name — — — — — CRCRC FASRC CASRC Default 0 0 0 0 0 0 0 0 Bit 2: CRC Resync Criteria Met Ev ent (CRCRC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 215 of 344 Register Name: TR.SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 7: Input Level Under Threshold (ILUT).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 216 of 344 Register Name: TR.IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 5 4 3 2 1 0 Name ILUT TI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 217 of 344 Register Name: TR.SR2 Register Description: Status Register 2 Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 7: Receive Yellow Alarm Clear Event (RYELC) (T1 Only).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 218 of 344 Register Name: TR.IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Name RYELC R.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 219 of 344 Register Name: TR.SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 7: Spare Code Detected Condition (LSPARE) (T1 Only).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 220 of 344 Register Name: TR.IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name LSPARE .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 221 of 344 Register Name: TR.SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI RSAO RSAZ TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only ).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 222 of 344 Register Name: TR.IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 5 4 3 2 1 0 Name RAIS-CI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 223 of 344 Register Name: TR.SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name — — TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 5: Transmit Elastic Store Full Event (TESF).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 224 of 344 Register Name: TR.IMR5 Register Description: Interrupt Mask Register 5 Register Address: 1Fh Bit # 7 6 5 4 3 2 1 0 Name — —.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 225 of 344 Register Name: TR.SR6, TR.SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 5 4 3 2 1 0 Name — TMEND RPE RPS RHWM RNE TLWM TNF Default 0 0 0 0 0 0 0 0 Bit 6: Transmit Message-End Event (TMEND).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 226 of 344 Register Name: TR.IMR6, TR.IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Reg.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 227 of 344 Register Name: TR.INFO5, TR.INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 5 4 3 2 1 0 Name — — TEMPTY TFULL REMPTY PS2 PS1 PS0 Default 0 0 0 0 0 0 0 0 Bit 5: Transmit FIFO Empty (TEMPTY).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 228 of 344 Register Name: TR.SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 5 4 3 2 1 0 Name — — BOCC RFDLAD RFDLF TFDLE RMTCH RBOC Default 0 0 0 0 0 0 0 0 Bit 5: BOC Clear Event (BOCC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 229 of 344 Register Name: TR.SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 5 4 3 2 1 0 Name — BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 6: BERT Bit-Error Det ected (BED) Event (BBED).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 230 of 344 Register Name: TR.IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 5 4 3 2 1 0 Name — BBE.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 231 of 344 Register Name: TR.PCPR Register Description: Per-Channel Pointer Register Register Address: 28h Bit # 7 6 5 4 3 2 1 0 Name RSAO.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 232 of 344 Register Name: TR.PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — — Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name: TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 233 of 344 Register Name: TR.INFO7 Register Description: Information Register 7 (Real-T ime, Non-Latched Register) Register Address: 30h B.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 234 of 344 Register Name: TR.E1RCR1 Register Description: E1 Receive Control Register 1 Register Address: 33h Bit # 7 6 5 4 3 2 1 0 Name R.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 235 of 344 Register Name: TR.E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 236 of 344 Register Name: TR.E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 237 of 344 Register Name: TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 Register Description: Receive Signaling Change-of-State Informati.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 238 of 344 Register Name: TR.SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 5 4 3 2 1 0 Name GRSRE — — RFE RFF RCCS TCCS FRSAO Default 0 0 0 0 0 0 0 0 Bit 7: Global Receive Signaling Reinsertion Enable (GRSRE).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 239 of 344 Register Name: TR.ERCNT Register Description: Error-Counter Configuration Register Register Address: 41h Bit # 7 6 5 4 3 2 1 0 Name — MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF Default 0 0 0 0 0 0 0 0 Bit 6: Manual Error-Counter Update (MECU).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 240 of 344 Register Name: TR.LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 5 4 3 2 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 241 of 344 Register Name: TR.FOSCR1 Register Description: Frames Out-of-Sync Count Register 1 Register Address: 46h Bit # 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 242 of 344 Register Name: TR.LBCR Register Description: Loopback Control Register Register Address: 4Ah Bit # 7 6 5 4 3 2 1 0 Name — — — LIUC LLB RLB PLB FLB Default 0 0 0 0 0 0 0 0 Bit 4: Line Interface Unit Mux Control (LIUC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 243 of 344 Register Name: TR.PCLR1 Register Description: Per-Channel Loopback Enable Register 1 Register Address: 4Bh Bit # 7 6 5 4 3 2 1 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 244 of 344 Register Name: TR.ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 5 4 3 2 1 0 Name TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Elastic Store Align (TESALGN).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 245 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 246 of 344 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 247 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 248 of 344 Register Name: TR.TS1 to TR.TS12 Register Description: Transmit Signaling Registers (T1 Mode, D4 Format) Register Address: 50h .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 249 of 344 Register Name: TR.RS1 to TR.RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 250 of 344 Register Name: TR.RS1 to TR.RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 251 of 344 Register Name: TR.CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 5 4 3 2 1 0 Name MCLKS CRC4R SIE ODM DICAI TCSS1 TCSS0 RLOSF Default 0 0 0 0 0 0 0 0 Bit 7: MCLK Source (MCLKS).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 252 of 344 Register Name: TR.CCR2 Register Description: Common Control Register 2 Register Address: 71h Bit # 7 6 5 4 3 2 1 0 Name — — — — — BPCS1 BPCS0 BPEN Default 0 0 0 0 0 0 0 0 Bits 1 – 2: Backplane Clock Selects (BPCS0, BPCS1) BPCS1 BPCS0 BPCLK Frequency (MHz) 0 0 16.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 253 of 344 Register Name: TR.CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 5 4 3 2 1 0 Name RLT3 RL.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 254 of 344 Register Name: TR.TDS0M Register Description: Transmit DS0 Monitor Register Register Address: 75h Bit # 7 6 5 4 3 2 1 0 Name B1 B2 B3 B4 B5 B6 B7 B8 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Transmit DS0 Channel Bits (B1 to B8).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 255 of 344 Register Name: TR.LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 5 4 3 2 1 0 Name L2 L1 L0 EGL JAS JABDS DJA TPD Default 0 0 0 0 0 0 0 0 Bits 5 – 7: Line Build-Out Select (L0 to L2).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 256 of 344 Register Name: TR.TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 5 4 3 2 1 0 Name — AGCE GC5 GC4 GC3 GC2 GC1 GC0 Default 0 0 0 0 0 0 0 0 Bit 6: Automatic Gain Control Enable (AGCE).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 257 of 344 Register Name: TR.LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 5 4 3 2 1 0 Name ETS LIRS.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 258 of 344 Register Name: TR.LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 5 4 3 2 1 0 Name — TCES RCES MM1 MM0 RSCLKE TSCLKE TAOZ Default 0 0 0 0 0 0 0 0 Bit 6: Transmit-Clock Edge Select (TCES).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 259 of 344 Register Name: TR.LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 5 4 3 2 1 0 Name CMIE CMI.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 260 of 344 Register Name: TR.IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 5 4 3 2 1 0 Name GRIC GTIC IAA5 IAA4 IAA3 IAA2 IAA1 IAA0 Default 0 0 0 0 0 0 0 0 Bit 7: Global Receive-Idle Code (GRIC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 261 of 344 Register Name: TR.TCICE2 Register Description: Transmit-Channel Idle-Code Enable Register 2 Register Address: 81h Bit # 7 6 5 4.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 262 of 344 Register Name: TR.RCICE2 Register Description: Receive-Channel Idle-Code Enable Register 2 Register Address: 85h Bit # 7 6 5 4 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 263 of 344 Register Name: TR.RCBR2 Register Description: Receive Channel Blocking Register 2 Register Address: 89h Bit # 7 6 5 4 3 2 1 0 N.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 264 of 344 Register Name: TR.TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 5 4 3 2 1 0 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 265 of 344 Register Name: TR.H1TC, TR.H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 266 of 344 Register Name: TR.H1FC, TR.H2FC Register Description: HDLC # 1 FIFO Control HDLC # 2 FIFO Control Register Address: 91h, A1h Bi.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 267 of 344 Register Name: TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 TR.H2RCS1, TR.H2RCS2, TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 268 of 344 Register Name: TR.H1RTSBS, TR.H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Tim.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 269 of 344 Register Name: TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 TR.H2TCS1, TR.H2TCS2, TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 270 of 344 Register Name: TR.H1TTSBS, TR.H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit T.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 271 of 344 Register Name: TR.H1TF, TR.H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 5 4 3 2 1 0 Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 THD0 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit HDLC Data Bit 7 (THD7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 272 of 344 Register Name: TR.H1TFBA, TR.H2TFBA Register Description: HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 273 of 344 Register Name: TR.TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Code-Definition Bit 7 (C7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 274 of 344 Register Name: TR.RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 275 of 344 Register Name: TR.RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 276 of 344 Register Name: TR.RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 5 4 3 2 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 277 of 344 Register Name: TR.RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this register resets t he detector’s integration period.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 278 of 344 Register Name: TR.RFDL (TR.BOCC.4 = 1) Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 5 4 3 2 1 0 Name — — RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 Default 0 0 0 0 0 0 0 0 RFDL register bit definitions w hen TR.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 279 of 344 Register Name: TR.TFDL Register Description: Transmit FDL Register Register Address: C1h Bit # 7 6 5 4 3 2 1 0 Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 TFDL2 TFDL1 TFDL0 Default 0 0 0 0 0 0 0 0 Note: Also used to insert Fs framing pattern in D4 framing mode.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 280 of 344 Register Name: TR.RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 5 4 3 2 1 0 Name Si 0 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 281 of 344 Register Name: TR.RSiAF Register Description: Received Si Bits of the Align Frame Register Address: C8h Bit # 7 6 5 4 3 2 1 0 N.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 282 of 344 Register Name: TR.RRA Register Description: Received Remote Alarm Register Address: Cah Bit # 7 6 5 4 3 2 1 0 Name RRAF1 RRAF3 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 283 of 344 Register Name: TR.RSa5 Register Description: Received Sa5 Bits Register Address: CCh Bit # 7 6 5 4 3 2 1 0 Name RSa5F1 RSa5F3 R.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 284 of 344 Register Name: TR.RSa7 Register Description: Received Sa7 Bits Register Address: CEh Bit # 7 6 5 4 3 2 1 0 Name RSa7F1 Rsa7F3 R.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 285 of 344 Register Name: TR.TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 5 4 3 2 1 0 Name Si 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 286 of 344 Register Name: TR.TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: D2h Bit # 7 6 5 4 3 2 1 0 N.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 287 of 344 Register Name: TR.TRA Register Description: Transmit Remote Alarm Register Address: D4h Bit # 7 6 5 4 3 2 1 0 Name TRAF1 TRAF3 .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 288 of 344 Register Name: TR.TSa5 Register Description: Transmitted Sa5 Bits Register Address: D6h Bit # 7 6 5 4 3 2 1 0 Name TSa5F1 TSa5F.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 289 of 344 Register Name: TR.TSa7 Register Description: Transmit Sa7 Bits Register Address: D8h Bit # 7 6 5 4 3 2 1 0 Name TSa7F1 TSa7F3 T.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 290 of 344 Register Name: TR.TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 5 4 3 2 1 0 Name.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 291 of 344 Register Name: TR.BRP1 Register Description: BERT Repetitive Pattern Set Register 1 Register Address: DCh Bit # 7 6 5 4 3 2 1 0.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 292 of 344 Register Name: TR.BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 5 4 3 2 1 0 Name TC TINV RINV PS2 PS1 PS0 LC RESYNC Default 0 0 0 0 0 0 0 0 Bit 7: Transmit Pattern Load (TC).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 293 of 344 Register Name: TR.BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 Default 0 0 0 0 0 0 0 0 Bits 5 – 7: Error Insert Bits 0 to 2 (EIB0 to EIB2).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 294 of 344 Register Name: TR.BBC1 Register Description: BERT Bit Count Register 1 Register Address: E3h Bit # 7 6 5 4 3 2 1 0 Name BBC7 BBC6 BBC5 BBC 4 BBC3 BBC2 BBC1 BBC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 295 of 344 Register Name: TR.BEC1 Register Description: BERT Error-Count Register 1 Register Address: E7h Bit # 7 6 5 4 3 2 1 0 Name EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Error Counter Bits 0 to 7 (EC0 to EC7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 296 of 344 Register Name: TR.BIC Register Description: BERT Interface Control Register Register Address: EAh Bit # 7 6 5 4 3 2 1 0 Name .
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 297 of 344 Register Name: TR.ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 5 4 3 2 1 0 Name WNOE — — CE ER3 ER2 ER1 ER0 Default 0 0 0 0 0 0 0 0 Bit 7: Write NOE Registers (WNOE).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 298 of 344 Register Name: TR.NOE1 Register Description: Number-of-Errors 1 Register Address: ECh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bits 0 – 7: Number-of-Errors Counter Bits 0 to 7 (C0 to C7).
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 299 of 344 11.7.1 Number-of-Errors Left Register The host can read the TR.NOELx registers at any time to determine how many errors are left to be inserted.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 300 of 344 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an input signal that can be used to enable or block the T SERO data.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 301 of 344 The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 302 of 344 In Half-Duplex (DTE) Mode, the DS 33R11 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the CO L input, the DS33R11 will replace the data nibbles with jam nibbles.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 303 of 344 RMII Receive data on RXD[1:0] is ex pected to be synchronous with the ri sing edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PH Y asynchronously drives CRS_DV low during carrier loss.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 304 of 344 Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled) CHANNEL 23 CHANNEL 24 CHANNEL 1 CHANNEL 23 CHANNEL 24 CHANNEL 1 RCLKO RSERO RSYNC RFSYN C RSIG RCHCLK RCHBLK 1 B A C/A D/B A C/A D/B LSB F MSB MS B LSB AB NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 305 of 344 Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSER O CHANNEL 1 RCHCLK RCHBLK RSY SCLK RSYNC CHANN.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 306 of 344 Figure 12-16. Transmit-Side ESF Timing 12345 6789 1 0 1 1 1 2 1 2 3 TSSY NC FRAM E# TSYNC TSYNC TSYNC 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 2345 NOTE 1: TSYNC IN FRAME MODE (TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 307 of 344 Figure 12-18. Transmit-Side 1.544MHz Bounda ry Timing (Elastic Store Enabled) LSB F MS B LSB MS B CHANNEL 1 CHANNEL 24 AB C / A .
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 308 of 344 12.4 E1 Mode Figure 12-20. Receive-Side Timing FRAME# 1 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 RSYNC 1 RSYNC RFSYN C 2 NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 309 of 344 Figure 12-22. Receive-Side Bounda ry Timing, RSYSCLK = 1.544MHz (E-Store Enabled) R SERO CHANNEL 23/31 CHANNEL 24/3 2 CHANNEL 1/.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 310 of 344 Figure 12-24. G.802 Timing, E1 Mode Only 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 311 of 344 Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled) LSB MSB LSB MS B CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 ABC D TCLK T TSERI TSYNC TSYNC TSI G TCHCLK TCHBLK 1 2 3 Si 1 A Sa 4 Sa5 Sa 6 Sa 7 Sa8 D NOTE 1: TSYNC IS IN THE OUTPUT MODE (TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 312 of 344 Figure 12-28. Transmit-Side Boundary Timi ng, TSYSCLK = 2.048MHz (Elastic Store Enabled) LSB F LSB MSB CHANNEL 1 CHANNEL 32 A B .
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 313 of 344 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V SS (except V DD )….………………………………………..-0.5V to +5.5V Supply Voltage (VDD3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 314 of 344 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMETER MIN TYP MAX Ambient Temperature (Note 1) -40°C +85°C Junction Temperature (Note 2) +125°C Theta-JA ( θ JA ) in Still Air for 256-Pin 27mm BGA (Notes 2, 3) +20.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 315 of 344 13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13- 1 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TY.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 316 of 344 Table 13-6. Receive MII Interface (Note 1, Figure 13- 2 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK P.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 317 of 344 13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13- 3 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN .
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 318 of 344 Table 13-8. Receive RMII Interface (Note 1, Figure 13- 4 ) 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 319 of 344 13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13- 5 ) PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 320 of 344 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, Figure 13- 6 ) PARAMETER SYMBOL MIN TYP MAX UNITS TCLKE Frequency 52 MHz TCLKE Period t1 19.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 321 of 344 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Figure 13- 7 ) PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 322 of 344 13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing (Note 1, Figure 13- 8 ) 100 MHz PARAMETER SYMBOL MIN TYP MAX UNITS SDCLKO Period t1 9.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 323 of 344 Figure 13-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) t1 SDATA (input) SRAS, SCAS, SW E, SDCS (output) t2 t3 t5 t6 .
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 324 of 344 13.8 Microprocessor Bus AC Characteristics Table 13-13. AC Characteristi cs—Microprocessor Bus Timing (VDD3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 325 of 344 Figure 13-9. Intel Bus Read Timing (MODEC = 00) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12:0] DAT A[7 :0] CS RD WR t1 Figure 13-10.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 326 of 344 Figure 13-11. Motorola Bus Read Timing (MODEC = 01) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12:0] DAT A[7 :0] DS RW t1 CS /CST Figure 13-12.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 327 of 344 13.9 AC Characteristics: Receive-Side Table 13-14. AC Charact eristics: Receive Side (V DD = 3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 328 of 344 Figure 13-13. Receive-Side Timing t D1 1 t D2 RSERO / RDA TA / RSIG RCHCLK RCHBLK RSYNC RCLKO RFSYNC / RM SYNC t D2 t D2 t D2 1ST FR AME BIT NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 329 of 344 Figure 13-14. Receive-Side Timi ng, Elastic Store Enabled F t t R t D3 t D4 t D4 t D4 t t SU HD RSERO / RS IG RCHCLK RCHBLK 1 RSYNC 2 RSYNC RSYSCLK SL t t SP SH t t D4 RMSYNC SEE N OTE 3 NOTE 1: RSYNC IS IN THE OUTPUT MODE.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 330 of 344 Figure 13-15. Receive Line Interface Timing t F t R RPOSI, RNEGI RDCLKI CL t t CP CH t t SU t HD t DD RPOSO, RNEGO RDCLKO LL t t.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 331 of 344 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Characteristics: Backplane Clock Synthesis (V DD = 3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 332 of 344 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteris tics: Transmit Side (V DD = 3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 333 of 344 Figure 13-17. Transmit-Side Timing t F t R 1 TCLKT TSERI / TS IG / TDATA TCHCLK t t CL t CH CP TSY NC TSY NC TLIN K TLC LK TCHBLK t D2 t D2 t D2 t t t t t t HD SU D2 SU HD D1 t HD 2 5 TESO t SU NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 334 of 344 Figure 13-18. Transmit-Side Timing, Elastic Store Enabled t F t R TSYSCLK TSERI TCHCLK t t SL t SH SP TSS YNC TCHBLK t D3 t D3 t t t SU HD SU t HD NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSC LK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 335 of 344 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%,VDD1.
DS33R11 Ethernet Mapper with Int egrated T1/E1/J1 Transceiver 336 of 344 14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the Ethernet Mapper, and Port 2 is for the T1/E1/J1 Transceiver. Because of this, this device requires special consideration during JTAG test design.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 337 of 344 14.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Te st Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 338 of 344 Update-DR A falling edge on JTCLK while in the Update-DR state will latc h the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 339 of 344 Figure 14-2. TAP Controller State Diagram 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 Select DR-Scan Captur e DR .
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 340 of 344 Table 14-1. Instruction Cod es for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGISTER INSTRUCTION CODES SAMPLE:PRELOAD Bound.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 341 of 344 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] Ethernet Mapper 0000 0000 0000 0110 0001 000 1010 0001 1 T1/E1/J1 Transceiver 0000 0000 0000 0001 0000 000 1010 0001 1 14.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 342 of 344 14.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 343 of 344 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect t he most current specif ications . The package number provided for each package is a link to the latest package outline inf ormation.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 344 of 344 Maxim/Dallas Semiconductor cannot assume re sponsibility for use of any circuitry other than circuitry entirely embodied in a M a xim/Dallas Semiconductor product. No circuit patent licenses are im plied.
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