Instruction/ maintenance manual of the product HSC-ADC-EVALC Analog Devices
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High Speed Converter Evaluation Platform HSC-ADC-EV ALC Rev. 0 Evalua tion boards are only in tended for dev ice ev aluation and no t for production purposes.
HSC-ADC-EVALC Rev. 0 | Page 2 of 32 T ABLE OF CONTENTS Fea tures .............................................................................................. 1 Equipm ent N eede d .....................................................................
HSC-ADC-EVALC Rev. 0 | Page 3 of 32 PRODUCT D ESCRIPTION The Analog Devices, In c. high speed con v erter evalua tion pla tform (HSC-ADC-EV ALC) inc ludes the la test v e rs i on o f V isual Analo g a.
HSC-ADC-EVALC Rev. 0 | Page 4 of 32 EV ALUA TION BOARD HARDW ARE HSC-ADC-EVALC ADC CAPTURE BOARD EASY START Requirements • HSC-ADC-EV ALC AD C capt ure board, V isualAnalog, 5 V wal l t ransfor mer,.
HSC-ADC-EVALC Rev. 0 | Page 5 of 32 ROHDE & S CH WARZ, SMHU, 2V p-p SIGN A L SYNTHESI ZER ROHDE & S CH WARZ, SMHU, 2V p -p SI G NAL SYNTHE SI ZER BAND- P ASS FIL TER USB CO NNEC TI O N 06676-0.
HSC-ADC-EVALC Rev. 0 | Page 6 of 32 HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES 06676-002 GEN ERAL PUR POSE I/O, USB/S P I CONT ROL DAT A BUS 1 DAT A BUS 2 FPGA LOA D SELECT ON BO ARD POW ER S UPPL Y 100.
HSC-ADC-EVALC Rev. 0 | Page 7 of 32 06676-003 Figure 4. HSC-ADC-EVALC Components (Bottom View) HSC-ADC-EVALC SUPPORTED ADC EVALUATION BOARDS Refer to the Analog Devices ADC capt ure board pr oduct page a t www .anal og.co m/F IFO for a lis t of HSC-AD C-EV ALC-com patible ADC evaluation boards.
HSC-ADC-EVALC Rev. 0 | Page 8 of 32 THEOR Y OF OPERA TION The HSC-AD C-EV ALC evaluation platform is based around the V irtex-4 FPGA (X C4VFX20-10FFG672C) from Xilinx®, which can be programmed through V isualAnalog to operate with a variety of data con verters.
HSC-ADC-EVALC Rev. 0 | Page 9 of 32 EV ALUA TION BOARD SCHEMA TICS AND ARTWORK HSC-ADC-EVALC SCHEMATICS 0 6676-0 05 TYC O A ND DS P EZ–K IT C ONN E CTOR TO FP GA XC4V FX20- 10FF G 672C XC4V FX 20-10F FG 672C XC4VF X20- 10FF G 672C XC4V FX20- 10FF G 672C R38 100 Ω R39 100 Ω R50 51.
HSC-ADC-EVALC Rev. 0 | Page 10 of 32 0 6676-00 6 SRAM ADDRESS AND CONTRO L FPGA CONT ROL S U21 NC7SZ 05M5X R1 100 Ω R40 3.74K Ω R44 3.74K Ω R42 3.74K Ω R41 3.74K Ω R43 3.74K Ω XC4VF X20- 10FF G 672C R28 3.74K Ω R27 249 Ω R33 249 Ω R25 3.
HSC-ADC-EVALC Rev. 0 | Page 11 of 32 FPG A TO S R AM D A T A XC4VF X20- 10FF G 672C 06676- 007 XC4VF X20- 10FF G 672C Figure 7..
HSC-ADC-EVALC Rev. 0 | Page 12 of 32 A D19 T O BE USED WIT H HIGHER DENSI TY SRAM DE VICES 06676-008 Figure 8..
HSC-ADC-EVALC Rev. 0 | Page 13 of 32 SRAM AND F PG A POWE R 06676-009 XC4VF X20- 10FF G 672C XC4VF X20- 10FF G 672C R66 499 Ω R64 499 Ω R65 499 Ω R63 499 Ω Figure 9.
HSC-ADC-EVALC Rev. 0 | Page 14 of 32 06676-0 10 REFCLK Osc illator for I DELAYCTRL FPG A BYPASS CA P SRAM A BYPASS CA P SRAM B BYPASS CA P + + + + R15 24 Ω Figure 10.
HSC-ADC-EVALC Rev. 0 | Page 15 of 32 06676-011 DEBU G PINS UNUSED ROCKET I /0 CONNECT IONS XC4VF X20- 10FF G 672C XC4V FX20- 10FF G 672C Figure 11..
HSC-ADC-EVALC Rev. 0 | Page 16 of 32 06676-0 12 ROCKET I/0 CONNECTIONS Figure 12..
HSC-ADC-EVALC Rev. 0 | Page 17 of 32 06676-013 USB CONNECTI ONS R49 3.74 Ω R71 3.74 Ω R48 100K Ω SDI & SDO DI RECTI O NS A RE WI T H RESPECT TO THE DE VI CE UNDER CO NTRO L.
HSC-ADC-EVALC Rev. 0 | Page 18 of 32 USB CONNECTI ONS (CONT INUED) 06676-014 4 5 2 1 3 6 R52 3.74K Ω R72 3.74K Ω R46 499 Ω XC4VF X20- 10FF G 672C XC4V FX20- 10F FG 672C J6 Figure 14.
HSC-ADC-EVALC Rev. 0 | Page 19 of 32 06676-015 EZ–KI T EXPANSION INT ERFACE – F OR DSPs P1 P2 P3 Figure 15..
HSC-ADC-EVALC Rev. 0 | Page 20 of 32 , 06676- 016 TYCO HM – Zd CONNECTOR S J1 HS- SERIAL/SPI/AUX J2 DATA B US 1 J3 DATA B US 2 Figure 16..
HSC-ADC-EVALC Rev. 0 | Page 21 of 32 0 6676-01 7 CONFI GURATIO N EEPRO M JTAG CO NNECTOR EEPROM HARDWARE RECONFI GURATIO N PUSH BUTT O N R57 3.74K Ω R73 ZER O R77 100 Ω R78 100 Ω R75 3.
HSC-ADC-EVALC Rev. 0 | Page 22 of 32 POWER AND VOLT AGE REGULATO RS 06676-0 18 + + + + + + + + + TSW–102–0 8–G–D DO NO T REMO VE R68 147k Figure 18.
HSC-ADC-EVALC Rev. 0 | Page 23 of 32 PCB LAYOUT 06676-019 GENERAL PU RPOSE I/O, USB/S P I CONT ROL DAT A BUS 1 DAT A BUS 2 XIL INX VIRTEX-4 FPGA DEBUG PINS EXTERNAL SYNC I/O CYPRE SS USB CONT ROL LE R.
HSC-ADC-EVALC Rev. 0 | Page 24 of 32 I/O CONNECTOR—J1, J2, AND J3 PIN MAPPING D C B A D C B A D C B A D17A– D16A– D14A– D12A– D10A – D8A– D6A– D4A– D2A– D0A– D17A+ D16A+ D14A+ D1.
HSC-ADC-EVALC Rev. 0 | Page 25 of 32 D C B A D C B A MGT CL K1– SD1– SD2– SD3– SD4– SD5– SD6 – SD7– SD 8– MG TCL K2– MGTCLK1+ SD1+ SD 2+ SD3+ SD4+ SD 5+ SD6+ SD7+ SD8+ MGTCLK2+ I/O.
HSC-ADC-EVALC Rev. 0 | Page 26 of 32 Table 3. HSC-ADC-EVALC J1 I/O Connections to FPG A (U1) Connector J1 (HS-Serial, SPI, AUX) Schematic Net Name FPGA Pin A1 USB_5 none B1 USB_4 none C1 MGTCLK2+ AF10.
HSC-ADC-EVALC Rev. 0 | Page 27 of 32 Table 5. HSC-ADC-EVALC J3 I/O Connections to FPG A (U1) Connector J3 (DA T A BUS 2) Schematic Net Name FPGA Pin A1 DCLKA2+ C14 B1 DCLKA2− B14 C1 D0A+ D6 D1 D0A.
HSC-ADC-EVALC Rev. 0 | Page 28 of 32 ORDERING INFORMA TION BILL OF MATERIALS (RoHS COMPLIANT) Table 6. Qty Reference Designator Description Manufacturer Part Number 1 PCB PCB, ADC evalua tion platform.
HSC-ADC-EVALC Rev. 0 | Page 29 of 32 Qty Reference Designator Description Manufacturer Part Number 17 L3 to L19 F errite chip, 220 Ω, 2 A, 0603, 100 MHz TDK MP Z1608S221A 3 P1 to P3 Connector , 0.050 in × 0.050 in, Samtec TFM se ries, 2R Samtec , Inc.
HSC-ADC-EVALC Rev. 0 | Page 30 of 32 Qty Reference Designator Description Manufacturer Part Number 2 U6, U7 IC, P-channel enhancement mode field effect transistor F air child Semiconductor NDT456P 1 U8 V oltage regulator , high accurac y ultralow IQ , 1.
HSC-ADC-EVALC Rev. 0 | Page 31 of 32 NOTES.
HSC-ADC-EVALC Rev. 0 | Page 32 of 32 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
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