Instruction/ maintenance manual of the product 317698-001 Intel
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Intel ® 82575 Gigabit Ethernet Controller Design Guide V1.00 June 2007 317698-001.
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iii 82575 Ethernet Controller Design Guide Contents 1.0 Introduction ..... ........... .......... ........... .......... ........... .......... ........... .......... ........... .......... 1 1.1 Scope ....... ........... .......... ........... ......
82575 Ethernet Controller Design Guide iv 5.3 Frequency T olerance .... ............ ............. ............. ............ ........... ............. ............32 5.4 Temperature Stability and Environmental Requir ements........... ............ ..
v 82575 Ethernet Controller Design Guide Revision History Date Revision Description 0.25 Jan 2006 Initial publication of pr eliminar y design guide information. 0.50 July 2006 Added features listings, NC -SI, LE D , strapping, pull-up/pull-do wn information.
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1 82575 Ethernet Controller Design Guide 1.0 Introduction The Intel ® 82575 Ethernet Controller is a single, compact component that offers two fully-integr ated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. This device uses the PCI Express* (PCIe) architecture (Rev .
82575 Ethernet Controller Design Guide 2 1.2 Reference Docum ents This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: • 82575 Ethernet Controller Product Datasheet .
3 82575 Ethernet Controller Design Guide 2.0 PCI Express Port Connection to the Device PCI Express (PCIe*) is a dual simplex point- to-point serial differential low- voltage interconnect. The signaling bit rate is 2.5 Gbps per lane per direction. Each po rt consists of a group of tr ansmitters and receivers located on the same chip.
82575 Ethernet Controller Design Guide 4 • If Maximum Link Width = x2, then the 82575 Ethernet Controller ne gotiates to either x2 or x1 • If Maximum Link Width = x1, then the 82575 Ethernet Controller only negotiates to x1 2.3.2 Polarity Inversion If polarity inversion is detected the R eceiver must invert the r eceived data.
5 82575 Ethernet Controller Design Guide Figure 1. Lane R eversal supported modes Configuration bits: EEPROM "Lane reversal disable" bit - disables lane reversal altogether 2.4 PCI Express Routing F or information regarding the PCIe signal rout ing, please refer to the Intel PCIe Design Guide.
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7 82575 Ethernet Controller Design Guide 3.0 Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins.
82575 Ethernet Controller Design Guide 8 consistent from sample to sample and that measurements meet the published specifications. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. V ary temperature and voltage while performing system level tests.
9 82575 Ethernet Controller Design Guide 3.2.1 LAN Disable for 82575 Ethern et Controller Gi gabit Ethernet Controller The 82575 Ethernet Controller device has three signals that can be used for disabling Ethernet functions from system BIOS .
82575 Ethernet Controller Design Guide 10 Table 2. Strapping Options for LAN Disable Table 3. Control Options for LAN Disable 3.2.2 Serial EEPROM The 82575 Ethernet Controller Gigabit Ethernet Controller uses an Serial Peripher al Interface (SPI)* EEPROM.
11 82575 Ethernet Controller Design Guide • Legacy W ake On LA N (magic packets) is not supported • All the initializations normally loaded from the EEPROM will be loaded by the host driver .
82575 Ethernet Controller Design Guide 12 Table 5. 82575 Ethernet Contro ller EEPROM Memory Layout 3.2.3.1 EEUPDATE Intel has an MS-DOS* software utility called EEUPDA TE, which can be used to program EEPROM images in development or production line environments.
13 82575 Ethernet Controller Design Guide 2. A particular address range of the IOADDR register defined by the IO Base Address R egister (PCIe Control Register at offset 18h or 20h). 3. The Expansion ROM Base Address Register (PCIe Control R egister at offset 30h).
82575 Ethernet Controller Design Guide 14 Note: Sector erase by SW is not suppor ted. In order to delete a sector , the serial (bit bang) interface should be used. 3.2.4.3 FL ASH Device Information While Intel does not make specific reco mmendations regarding FLASH devices, the following devices hav e been used successfully in previou s designs: 3.
15 82575 Ethernet Controller Design Guide Figure 2. External BMC Connections with NC-SI and SMB The 82575 Ethernet Controller also supports the DMTF protocol. F or more information about NC -SI and DMTF , see the 82575 Family System Management Application Note .
82575 Ethernet Controller Design Guide 16 Figure 3. Example Switching Voltag e Regulator for 1.0 V and 1.8 V D N G G N I H C T I W S _ 0 V 1 C C V 3 V 3 C C V > > n o i t c e l e S r o t s i s e R r o t a l u g e R < < ) ) t f e l R + t h g i r R ( / p u R + 1 ( * 8 .
17 82575 Ethernet Controller Design Guide The 1.8 V rail has a lower current requirem ent; however , the use of a SVR is still recommended for adequate margin. Using an L VR in this application is acceptable as long as adequate margin exists in the desi gn, and sequencing can be controlled.
82575 Ethernet Controller Design Guide 18 Figure 5. Proper power se quencing for 82575 Ethernet Controller Figure 6. Power On Flowchart In addition, the following limitations exist: W Y Y .
19 82575 Ethernet Controller Design Guide • 1.8 V must not excee d 3.3 V . • 1.0 V must not excee d 3.3 V . • 1.0 V must not excee d 1.8 V . The power supplies are all expected to ra mp during a short power -up internal (approximately 20ms or better).
82575 Ethernet Controller Design Guide 20 logic input to the 82575 Ethernet Controller that denotes auxiliary power is available. If AUX_PWR is asserted, the 82575 Ethernet Controller device will advertise that it supports wake up from a D3cold state.
21 82575 Ethernet Controller Design Guide Figure 8. PCIe Power Man agement Flow/State Diagram 3.4.4.2 825 75 Ethernet Controller Power Management If DisableD3Cold=0, the 82575 uses the AUX_ PWR indication that auxiliary power is av ailable to the controller , and therefore advertises D 3cold W ake Up support.
82575 Ethernet Controller Design Guide 22 3.5 82575 Ethernet Controller Device Test Capability The 82575 Ethernet Controller Gigabit Ethernet Controller contains a test access port (3.3 V only) conforming to the IEEE 1149 .1a-1994 (JT AG) Boundary Scan specification.
23 82575 Ethernet Controller Design Guide 3.6.2 Smartspeed SmartSpeed is an enhancement to auto-negot iation that allows the PHY to react to network conditions that are preventing a 1000BASE- T link, such as cable problems. These problems may allow auto-negotiation to complete, but then inhibit completion of the training phase.
82575 Ethernet Controller Design Guide 24 The table below summarizes link speed as function of power management state, link speed control, and gigabit speed enabling: 3.6.5 Link Energy Detect The PHY de- asserts the Lin k Energy Detec t Bit (PHYREG 2 5.
25 82575 Ethernet Controller Design Guide 3.6.7 Auto-Negotiation differences between PHY, SerDes and SGMII SGMII protocol includes an auto-negotiation process in order to establish the MAC - PHY connection.
82575 Ethernet Controller Design Guide 26 is complete, the driver must read the PHY registers to determine the resolved flow control behavior of the lin k and reflect th ese in the MAC register settings (CTRL.TFCE and CTRL.RFCE). Note: Once PHY Auto-negotiation is complete, the PHY will assert a link indication (LINK) to the MAC.
27 82575 Ethernet Controller Design Guide • The 82575 will put the PHY in power down unless CONNSW .ASCLR_DIS is set. In such a case the host driver is responsible for the clearing of the AUT OSENSE_EN bit According to the result of the interrupt, the software can then decide to switch to the other core.
82575 Ethernet Controller Design Guide 28 Note that if the device is configured to provide a 50MHz N C- SI cloc k (via the NC-SI Output Clock EEPROM bit), then the NC- SI clock must be provided in Device Disable mode as well the device should not be disabled.
29 82575 Ethernet Controller Design Guide Note: T o avoid signal contention, all four pins are set as input pins until after EEPROM configuration has been loaded. In addition to all four pins being individua lly configurable as inpu ts or outputs, they may be configured for use as gener al-purp ose interrupt (GPI) inputs.
82575 Ethernet Controller Design Guide 30 4.0 Frequency Control Device Design Considerations This section provides information regarding frequency control devices, including crystals and oscillators, for use with all Intel Ethernet controllers.
31 82575 Ethernet Controller Design Guide 4.1.3 Programmable Crystal Oscillators A programmable oscillator can be configured to oper ate at many frequencies. The device contains a crystal frequency refe rence and a phase lock loop (PLL) clock generator .
82575 Ethernet Controller Design Guide 32 5.0 Crystal Selection Parameters All crystals used with Intel Ethernet controllers are described as “ A T -cut, ” which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone.
33 82575 Ethernet Controller Design Guide Note: Crystals also carry other specifications for storage temper ature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cy cle to discuss the application and its environmental requirements.
82575 Ethernet Controller Design Guide 34 An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stra y capacitance of about 5 pF . Individual stray capacitance components can be estimated and added.
35 82575 Ethernet Controller Design Guide Even with a perfect support circuit, most crysta ls will oscillate slightly higher or slightly lower than the exact center of the target frequency . Therefore, freque ncy measurements (which determine the correct v alue for C1 and C2) should be performed with an ideal reference crystal.
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37 82575 Ethernet Controller Design Guide 6.0 Oscillator Support The 82575 clock input circuit is optimized for use with an external crystal. However , an oscillator can also be used in place of the crystal with the proper design considerations: • The clock oscillator has an internal voltage regulator of 1.
82575 Ethernet Controller Design Guide 38 A low capacitance, high impedance probe (C < 1 pF , R > 500 K Ω ) should be used for testing. Probing the par ameters can affect the measurement of the clock amplitude and cause errors in the adjustment.
39 82575 Ethernet Controller Design Guide 7.0 Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout pr actices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements.
82575 Ethernet Controller Design Guide 40 Minimizing the amount of space needed fo r the Ethernet LAN interface is important because other interfaces will compete for physical space on a motherboard near the connector . The Ethernet LAN circuits need to be as close as possible to the connector .
41 82575 Ethernet Controller Design Guide Figure 13. Layou t for Integr ated Magnetics Figure 14. Layo ut for Discrete Magnetics T ermination resistors placed within 250 mils of silicon TVS Diodes for.
82575 Ethernet Controller Design Guide 42 7.1.2 Crystals and Oscillators Clock sources should not be placed near I/O ports or board edges. R adiation from these devices may be coupled into the I/O ports and r adiate beyond the system chassis. Crystals should also be kept aw ay from the Ethernet magnetics module to prevent interference.
43 82575 Ethernet Controller Design Guide Figure 15. Recommended Crystal Plac ement and Layout 7.1.3 Board Stack Up Recommendations Printed circuit boards for these designs typi cally have six, eight, or more layers.
82575 Ethernet Controller Design Guide 44 7.1.4 Differential Pair Trace Routing for 10/100/1000 Designs T race routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist.
45 82575 Ethernet Controller Design Guide 7.1.4.1 Signal Termination and Coupling The four differential pairs of each port are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82575 controller . One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace.
82575 Ethernet Controller Design Guide 46 7.1.6.1 Sig nal Detect Each port of the 82575 controller has a Signal Detect pin for connection to optical transceivers. F or designs without optical transceivers, these signals can be left unconnected because they hav e internal pull-up resistors.
47 82575 Ethernet Controller Design Guide • Isolate I/O signals from high-speed signals to minimize crosstalk, which can increase EMI emission and susceptibility to EMI from other signals.
82575 Ethernet Controller Design Guide 48 7.1.14 Thermal Design Considerations The 82575 Gigabit Ethernet Controller contains a thermal sensor that is accessible through the SMBus.
49 82575 Ethernet Controller Design Guide where the traces enter or exit the magnetics, the RJ-45 connector , and the Ethernet silicon. 6. Use of a low-quality magnetics module. 7. R e-use of an out-of -date physical la yer schematic in a Ethernet silicon design.
82575 Ethernet Controller Design Guide 50 8.0 Thermal Management Please see the 82575 Thermal Application Note, available on the Intel Developer site. 9.0 Reference Design Bill of Materials The bill of materials for Intel’s reference designs is available on the Intel Developer site.
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