Instruction/ maintenance manual of the product 315889-002 Intel
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Reference Nu mber: 315889-002 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines April 2008.
2 315889-002 INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRE SS OR IMPLIED, BY ESTOPPEL OR O THERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT .
315889-002 3 Contents 1A p p l i c a t i o n s .......... ............. ............... ............ ............... ............... ............ ............... .... 9 1.1 Introduction and Terminology .......... ............... ................ .....
4 315889-002 8.10 Safety - PRO POSED ........... ............... ............... ............ ............... ............... ........ 46 9 Manufacturing Con siderations ................... ............. .............. ............. ............... ..
315889-002 5 2-6 Recommended Decoupling and Othe r Specifications for Supported (Highest SKU) Pro cessors - Summary ....... ................. .........
6 315889-002 Revision History Rev # Description Rev. Date 001 • Initial Release November 2006 002 • Gener al- Update Harpertown and W olfdale-DP to public name s • T able 2-3 correction - Loadli.
315889-002 7 The following table lists the revision schedule based on revision number and dev elopment stage of the product. Note: Not all revisions may be published. § Revision Project Document State Projects Covered 0.5 Preliminary T argets HW , SW 0.
8 315889-002.
315889-002 9 Applications 1 Applications 1.1 Introduction and Terminology This document defines the DC-to-DC co nverters to meet the processor power requirements of the following platforms: The requir.
Applications 10 315889-002 • New power-on sequence • Extended VR 10.x VID table with a 7th bit for 6. 25 mV re solution and 0.83125 V to 1.6 V range, only 12.5 mV resolution will be used in Dual-Core Intel Xeon Processor-Based Platform and Intel E8500 platforms.
315889-002 11 Outp ut Vo ltag e Req uire ments 2 Output Voltage Requirements 2.1 Voltage and Current - REQUIRED There will be independent selectable voltag e identification (VID) codes for the core voltage regulator .
Output Voltage Requirements 12 315889-002 The continuous load current ( I CCTDC ) can also be referred to as the Thermal Design Current (TDC). It is the sustained DC equiv alent current that the processor is capable of drawing indefinitely and defines the curre nt that is used for the voltage regulator temperature assessment.
315889-002 13 Outp ut Vo ltag e Req uire ments Notes: 1. These values are either pre-silicon or the latest known v alu es and are subject to ch ange. See the respective Processor’s Electrical, Mechanical, and Thermal Specif ications (EMTS) for the latest IccTDC and IccMAX specifications.
Output Voltage Requirements 14 315889-002 The upper and lower load lines represent the allowable range of v oltages that must be presented to the processor . T he voltage must always stay within these boundaries for proper operation of the processor .
315889-002 15 Outp ut Vo ltag e Req uire ments Notes: 1. The Vcc values are the expec ted voltage measu red at the processor d ie. 2. The Dual-Core Intel® Xeon® 7100 series / Dual-Cor e Intel® Xeon® processor 7000 sequence entry is required for backward compatibility for VR ‘modul es’ only using the EVRD/VRM 10.
Output Voltage Requirements 16 315889-002 2.4 Processor V CC Overshoot - REQUIRED The VRM/EVRD 11.0 is permitted short tr an sient overshoot events where Vcc exceeds the VID voltage when transitioning from a high-to-low current load condition ( Figure 2-2 ).
315889-002 17 Outp ut Vo ltag e Req uire ments dependent upon the selection of the bulk capacitors, cer amic capacitors, power plane routing and the tuning of the PWM controller’ s feedback network.
Output Voltage Requirements 18 315889-002 3. See Section 2.5 and Ta b l e 2 - 4 , Impedance Measurement pa rameters and definitions Notes: 1. Z LL is the target impedance for each processor and Z( f ) value coincides with it’ s Load Line slope.
315889-002 19 Outp ut Vo ltag e Req uire ments Notes: 1. VT T_PWRGD can be designed to be driving d irectly the OUTEN input. 2. Tb and Td voltage sl opes are determined by soft start logic of the PWM controller . 3. Vboot is a default power-on V cc (Core) value.
Output Voltage Requirements 20 315889-002 Note: 1. Minimum delays must be selected in a manner which will guarantee complia nce to voltage tolerance specifications. 2.8 Dynamic Voltage Identification (D-VID) - REQUIRED VRM/EVRD 11.0 supports dynamic VID acro ss the entire VID table.
315889-002 21 Outp ut Vo ltag e Req uire ments Figure 2-6 is an example of dynamic VID. The diagr am assumes steady state, constant current during the dynamic VID transition for ease of illustr ation; actual processor behavior allows for any dIcc/dt during the tr ansitions, depending on the code it is executing at that time.
Output Voltage Requirements 22 315889-002 2.9 Overshoot at Turn-On or Turn-Off - REQUIRED The core VRM/EVRD output v oltage should re main within the load-line regulation band for the VID setting, while the VRM/EVRD is turning on or turnin g off , with no over o r undershoot out of regulation.
315889-002 23 Outp ut Vo ltag e Req uire ments The platform processor decoupling design incorporates fifteen 560 µF Aluminum- polymer bulk capacitors and forty four 10 µF 1206 package ceramic high-f.
Output Voltage Requirements 24 315889-002 Note: The amount of bulk decoupling needed is dependent on the voltage regulator design. Some multiphase buck regulators may ha ve a higher switching frequency that would require a different output decoupling solu tion to meet the processor load line requirements than describ ed in this document.
315889-002 25 Outp ut Vo ltag e Req uire ments Notes: 1. Dual-Core Intel Xeon 5000 Series processor s with In tel 5400 Chipsets platform has 8-layer stackup. R efer to the latest Dual-Core Intel X eon 5000 Series processo rs with Intel 5400 Chipsets Platform Design Guide for baseboa rd stack-up details.
Output Voltage Requirements 26 315889-002 2.11 Shut-Down Response - REQUIRED Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 m s and latch off until power is cycled.
315889-002 27 Control Signals 3 Control Signals 3.1 Output Enable (OUTEN) - RE QUIRED The VRM/EVRD must accept an input signal to enable its output v oltage. When disabled, the regulator’s output should go to a high impedance state and should not sink or source current.
Control Signals 28 315889-002 Note: An OFF VID code is equiv alent to de -asserting the output enable input ( Section 3.1 ). Table 3-3. Extended V R 10 Voltage Identi fication (VID) Table VI D4 VI D3 VI D2 VI D1 VI D0 VI D5 VI D6 Vol t ag e VI D4 VI D3 VI D2 VI D 1 VI D0 VI D5 VI D6 Vo l t a ge 400 m V 200 m V 100 m V 50 m V 25 m V 12.
315889-002 29 Control Signals Note: Only VID [6.0] are used for VRM/EVRD 11.0 platform s. The eighth VID bit is pro visional for future Itanium-based platforms.
Control Signals 30 315889-002 Notes: F or each processor , refer to the appropriate p lat form design guide (PDG) for the recommended VR’ s remote sense r outing. The sense line s should be routed based on the following guidelines: • Route differentially with a maximum of 5 mils separation.
315889-002 31 Control Signals 3.4 Load Line Select (LL0, LL1, VID_Select) - REQUIRED The VID_Select, LL1 and LL0 control signal fo rm a 3-bit load line selection and will used to configure the VRM/EVRD to supply the proper load line for the processors.
Control Signals 32 315889-002.
315889-002 33 Input Voltage and Current 4 Input Voltage and Current 4.1 Input Voltages - EXPECTED The power source for the VRM/EVRD is 12 V +5% / –8%. This voltage is supplied by a separate power supply . For input v oltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down.
Input Voltage and Current 34 315889-002.
315889-002 35 Processor Voltage Output Protection 5 Processor Voltage Output Protection These are features built into the VRM/EVRD to prevent fire, s moke or damage to itself , the processor , or other system components.
Processor Voltage Output Protection 36 315889-002.
315889-002 37 Output Indicators 6 Output Indicators 6.1 Voltage Regulator Ready (VR_Ready) - REQUIRED The VRM/EVRD VR_Ready signal is an outp ut signal that indicates the start-up sequence is complete and the output voltage has mov ed to the programmed VID valu e.
Output Indicators 38 315889-002 to the FORCEPR# pin or through system manage ment logic. As sertion of this signal will lower processor power consumption and reduce current dr aw through the voltage regulator , resulting in lower compone nt temper atures.
315889-002 39 Output Indicators § Figure 6-1. VRM 11.0 and Platform Present Detection V RM_Pres# (MB Pull-up, VRM Pull - DW N) V RID# (MB PullUP , VRM Pull DW N ) VID_SELECT (VRM P ulldwn, Pla tform pullup) LL1 (MB PullUP, CPU Pul l DWN) LL0 (MB Pull UP, CPU Pull DW N) Outcome VRD11 .
Output Indicators 40 315889-002.
315889-002 41 VRM – Mechanical Guidelines 7 VRM – Mechanical Guidelines 7.1 VRM Connector - EXPECTED The part number and vendor n ame for VR M 11.0 connectors that can be found in Ta b l e 7 - 1 . The VRM reference in Section 7.2 , Section 7.3 and Section 7.
VRM – Mechanical Guidelines 42 315889-002 Note: VID7 bit is not routed from the PWM control IC to t he VRM connector; VID7is to be he ld Low on the VRM board.
315889-002 43 VRM – Mechanical Guidelines 7.4 Mechanical Dimensions - PROPOSED The mechanical dimensions for the VRM 11.0 module and connector are shown in Figure 7-1 . 7.4.1 Gold Finger Specification The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that is 1.
VRM – Mechanical Guidelines 44 315889-002 § Figure 7-1. VRM 11.0 Module an d Connector 96. 52m m ( 3. 80") MA X 65.34mm ( 2. 57") MAX 93. 34mm ( 3. 6 75" ) MAX 13.50mm ( 0. 531") 66.34mm (2. 6 12" ) MAX 59. 3m m (2.3 3 ") Ref .
315889-002 45 Environmental Conditions 8 Environmental Conditions The VRM/EVRD design, including materi als, should meet the environmental requirements specified below.
Environmental Conditions 46 315889-002 8.5 Altitude - PROPOSED 3.05 km [10 k feet] – operating 15.24 km [50 k feet] – non-oper ating 8.6 Electrostatic Discharge - PROPOSED T esting shall be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level.
315889-002 47 Manufacturing Considerations 9 Manufacturing Considerations 9.1 Lead Free (Pb Free) The use of lead in electronic products is an increasingly visible environmental and political concern.
Manufacturing Considerations 48 315889-002.
315889-002 49 Z(f) Constant Output Impedance Design A Z(f) Constant Output Impedance Design A.1 Introduction - PROPOSED The VRM/EVRD performance specification is ba sed on the concept of output impedance, commonly known as the load line.
Z(f) Constant Output Impedance Design 50 315889-002 The impedance plot Z(f ) shown in Figure A-2 can be divided up into three major areas of interest. • Low frequency , Zero Hz (DC) to the VR loop bandwidth. This is set by AVP and loop compensation of the VR controller or PWM control IC.
315889-002 51 Z(f) Constant Output Impedance Design capacitors in parallel. The effect of the mid frequency resonant point must be investigated and v alidated with Vdroop test ing to ensure any current load tr ansient pattern, does not violate the V min load line.
Z(f) Constant Output Impedance Design 52 315889-002 frequency applied by the application. Hence a better method is needed to extract the impedance profile with the VR operating. Th e following sections introduce the theory behind using a VT T tool to create an impedance profile for the VR system.
315889-002 53 Z(f) Constant Output Impedance Design A.3 VTT Z(f) Measurement Method An electronic load that has the capability to change the repetition rate up to 3 MHz of the load step is needed. The Intel LGA771 /775V2 VT T by Cascade Systems Design, will meet this requirement.
Z(f) Constant Output Impedance Design 54 315889-002 current was 40 A. The wa veforms show the effect of capacitor depopulation on the impedance profile above 1 MHz as p airs of high frequency MLCC capacitors are removed (banks 1-9) per the bank designations depicted in Figure A-7 .
315889-002 55 Z(f) Constant Output Impedance Design Figure A-6. Measured Platform Impedance Profile Showing Change in Impedance as Capacitors Are Removed Figure A-7. Designations of ML CC Cavity Capaci tor Banks Magn it u de of impedan ce pr ofil e 0 1 2 3 4 5 6 7 8 9 10 0.
Z(f) Constant Output Impedance Design 56 315889-002 A.5 Output Decoupling Design Procedure 1. Select type and number of bulk capacito rs. Normally the equiv alent ESR needs to be approximately ½ the load line target impedance. For a 1.25 m Ω load line, the equivalent ESR should be less than 0.
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