Instruction/ maintenance manual of the product CY7C1248V18 Cypress
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CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-W ord Burst Architecture (2.0 Cycle Read Latency) Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06348 Rev .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 2 of 27 Logic Block Diagram (CY7C1246V18) Logic Block Diagram (CY7C1257V18) CLK A (20:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 3 of 27 Logic Block Diagram (CY7C1248V18) Logic Block Diagram (CY7C1250V18) CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 4 of 27 Pin Configurations CY7C1246V18 ( 4M x 8) 165-Ball FBGA (15 x 17 x 1.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 5 of 27 Pin Configurations (continued) CY7C1248V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input/Output- Synchronous Data Input/Output Sign al s . Inputs are sampled on the rising edge of K and K clocks during valid write operations .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 7 of 27 ZQ Input Output Impedanc e Matching Input . T his input is used to tune t he device outputs to the system data bus impedance. CQ, CQ , and Q [x:0] output impedance are set to 0.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 8 of 27 Functional Overview The CY7C1246V18, CY7C1257 V18, CY7C1248V18, and CY7C1250V18 are synch ronous pipelined Bu rst SRAMs equipped with a DDR inte rface. Accesses for both ports are initia ted on the Positive Input Clock (K).
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 9 of 27 V alid Data Indicator (QVLD) QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is ge nerated by the DDR-II+ device along with data output.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 10 of 27 Write Cycle Descriptions The write cycle descriptions table for CY7C1246V18 and CY7C 1248V18 follows.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 1 1 of 27 Write Cycle Descriptions The write cycle descriptions ta ble for CY7C1250V18 follows.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 12 of 27 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan test access port (T AP) in the FBGA package. This part is fully compliant with IEEE S tandard #1 149.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 13 of 27 IDCODE The IDCODE instruction loads a vendor-sp ecific, 32-bit code into the instruction register .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 14 of 27 T AP Controller St ate Diagram The stat e di a g ram for the T AP controller follows.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 15 of 27 T AP Controller Block Diagram T AP Electrical Ch aracteristics Over the Operatin g Range [10, 1 1, 12] Parameter Descriptio n T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 16 of 27 T AP AC Switchi ng Characteristics Over the Operatin g Range [13, 14] Parameter Descriptio n Min Max.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 17 of 27 Identification Regi ster Definitions Instruction Field Va l u e Description CY7C1246V18 CY7C1257V1 8 CY7C1248V18 CY7C1 250V18 Revision Number (31:29) 000 000 000 000 V ersion number .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialize d in a predefined manner to prevent undefined opera tions. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 20 of 27 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emp erature .....
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 21 of 27 Cap acit ance T ested initially and after any design or proc ess change that may affect these parameters. Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 22 of 27 Switching Characteristics Over the Operatin g Range [20, 21] Cypress Parameter Consortium Parameter .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 23 of 27 Switching W aveforms Read/Write /Deselect Sequence [28, 29, 30] Figure 5.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 24 of 27 Ordering Information Not all of the speed, package and temperat ure ranges are avail able. Please contact your local sales representative or visit www .
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 25 of 27 300 CY7C1246V18-300 BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1257V18-300BZC CY7C1248V18-300BZC CY7C1250V18-300BZC CY7C1246V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev . *D Page 26 of 27 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.
Document Number: 001-06348 Rev . *D Revised March 1 1, 2008 Page 27 of 27 All product and company name s mentione d in this docume nt are the tr ademar ks of their res pective holders. CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 © Cypress Semicondu ctor Corpor ation, 2006-2008.
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