Instruction/ maintenance manual of the product CY7B9920 Cypress
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CY7B9910 CY7B9920 Low Skew Clock Buf fer Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-07135 Rev . *B Revised August 07, 2007 Features ■ All outputs skew <100 ps typical (250 max.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 2 of 1 1 Pin Configuration T est Mode The TEST input is a three level in put. In normal system operat ion, this pin is connected to groun d, allowing the CY7B9910 and CY7B9920 to ope rate as described i n Block Diagram Description .
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 3 of 1 1 Maximum Ratin gs Operating outside these boundaries may affect the performance and life of the d evice. These user guidelin es are not tested. S torage T emperature ................ .
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 4 of 1 1 Electrical Characteristics Over the Operating Range CY7B9910 CY7B9920 Parameter Description T est Conditions Min Max Min Max Unit V OH Output HIGH V oltage V CC = Min, I OH = –16 mA 2.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 5 of 1 1 AC T est Loads and W aveforms Cap acita nce T ested initially and after any design or proces s changes that may affect these parameters. Parameter Descriptio n T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V CC = 5.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 6 of 1 1 CY7B9910–5 CY7B9920–5 Parameter D escription Min Typ Max Min Typ Ma x Unit f NOM Operating Clock Frequency in MHz FS = LOW [1, 2] 15 30 15 30 MHz FS = MID [1, 2] 25 50 25 50 FS = HIGH [1, 2, 3] 40 80 40 80 [12] t RPWH REF Pulse Width HIGH 5.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 7 of 1 1 Switching Characteristics Over the Operating R ange [1 1] (continued) CY7B9910–7 CY7B9920–7 Parameter Des cription Min Ty p Max .
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 8 of 1 1 AC Timing Diagrams Figure 1. AC Timing Diagrams Figure 2. Zero Skew and Zero Delay Clock Driver t ODCV t ODCV t REF REF FB Q OTHER Q.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 9 of 1 1 Operational M ode Descriptions Figure 2 shows the devi ce configured as a zero ske w clock buffer . In this mode the 7B9910/9920 is used as the basis for a low skew clock distribution tree.
CY7B9910 CY7B9920 Document Number: 38-0713 5 Rev . *B Page 10 of 1 1 Ordering Information Accuracy (p s) Ordering Code Package T ype Operating Range 250 CY7B9910–2SC 24-Pb Small Outline IC Commercia.
Document Number: 38-07135 Rev . *B Revised August 07, 2007 Page 1 1 of 1 1 PSoC Designer™, Programmable System-on-Chip ™, an d PS oC Exp re ss™ are tra demarks a nd PSo C® is a registe red t rade mark of Cypress S emi con ductor Corp.
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If you already are a holder of Cypress CY7B9920, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Cypress CY7B9920.
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