Instruction/ maintenance manual of the product XAPP721 Xilinx
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© 2005 – 2006 Xilinx, Inc. All rights reserved. XI LINX, the Xilinx logo , and other de signated br ands included herein are tradem a rks of Xilinx, Inc. All other trademarks are the property of their respectiv e owners . Summary This application note describes a data capture techniq ue fo r a high-perf ormance DDR2 SDRAM interf ace.
Write Datapath R Write Datapath The write datapath uses the built-in OSER DES av ailable in e ver y Vir tex-4 I/O . The OSERDES transmits the data (DQ) and strobe (DQS) signals. The memory specification r equires DQS to be transmitted cent er-aligned with D Q.
Write Datapath R Figure 3: Write Data T ransmitted Using OSERDES Figure 4: Write Str obe (DQS) and Data (DQ) Timing f or a Write Latency of Four D1 D2 D3 D4 CLKDIV CLK CLKdiv_90 CLKfast_90 OSERDES DQ .
Write Datapath R Write Timing Analysis Ta b l e 1 shows the write timing analys is f or an interface at 333 MHz (667 Mb/s). Ta b l e 1 : Write Timing Analysis at 333 MHz Uncertainty Parameter s V alue Uncer tainties before DQS Uncer tain ties after DQS Meaning T CLOCK 3000 Clock period.
Write Datapath R Controller to Writ e Datapath Interface Ta b l e 2 lists the signals required f rom the controller to th e write datapath. Ta b l e 2 : Controller to Write Datapath Signals Signal Name Signal Width Signal Description Notes ctrl_WrEn 1 Output from the con troller to the write datapath .
Write Datapath R Figure 5: Write DQ Generation with a Write Latenc y of 4 and a Bur st Length of 4 Figure 6: Write DQS Generation for a Write La tenc y of 4 and a Burst Length of 4 CLKdiv_0 CLKdiv_90 .
Read Datapath R Read Datapath The read datapath co mprises the read data capture and recaptur e stages . Both stages are implemented in the built-in ISERDES a vailable in e very Vir te x-4 I/O . The IS ERDES has three clock inputs: CLK, OCLK, and CLKDIV .
Read Datapath R Ta b l e 3 shows the read timing analysis at 333 MHz re quired to deter mine the dela y required on DQ bits f or center ing DQS in the data v alid window .
Read Datapath R Figure 8 shows the timing w avef orm f or read data and strobe dela y deter mination. The wa vef or ms on the left show a case where the DQS is dela yed due to BUFIO and clo cking resource, and the ISE RDES outputs do not match the expected data patter n.
Read Datapath R Controller to Read Datapath Interface Ta b l e 4 lists the control signals between the contro ller and the read datapath. Ta b l e 4 : Signals between Contr oller and Read Datapath Signal Name Signal Width Signal Description Notes ctrl _Dummyread_Star t 1 Output fro m the controlle r to the read data path.
Reference Design R The ctrl_RdEn signal is requir ed to validate read data because the DDR2 SDRAM de vices do not provide a r ead v alid or read-enab le signal along with read data. The controlle r generates this read-enable signal based on the CAS latency and the b urst length.
Reference Design Utilization R Reference Design Utilization Ta b l e 5 lists the resource utilization f or a 64-bit interf ace including the physical la yer , the controller , the user interf ace, and a synthesizab le test bench.
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