Instruction/ maintenance manual of the product TLP511U Toshiba
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FILE NO. 336-9707 TECHNICAL TRAINING MANU AL 3 LCD D A T A PR OJECT OR PRINTED IN JAP AN, No v ., 1997 S TLP511U TLP510U TLP511E TLP510E.
i 1. MAIN PO WER SUPPL Y CIRCUIT ..................................... 1-1 1-1. Description ................................................. 1-1 1-2. Output Control .......................................... 1-1 1-3. V oltage Switching ..............
1-1 1. MAIN PO WER SUPPL Y CIRCUIT 1-1. Description This power supply boosts up at boost-up-con verter just after bridge-rectifying A C input v oltage, supplies the voltage smoothed to DC 350V to the lamp output.
1-2 1-5. Ov er -curr ent Protection In S6V and +6V lines, the volta ge drop owing to the current flowing in L203 is detected b y pins 5 and 6 of IC401, when the total current amount exceeds 8A, pin 7 de velops high and the v oltage biasses the base v oltage of transistor Q401 passing through the zener diode D402 and diode D401.
2-1 2. LAMP PO WER SUPPL Y CIRCUIT (LAMP DRIVER) 2-1. Conf iguration The lamp pow er supply cicrcuit recei ves a DC220 to 390V (primary side) from the system po wer supply and provides a A C voltage (70 to 100V AC at ev er turning on the lamp) to turn on the lamp.
3-1 3. OPTICAL SYSTEM 3-1. Conf iguration Lamp unit Mirror box unit Prism unit Projec- tion lens No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name UHP lamp P arabolic reflector UV IR filter Multi-lenses A,.
3-2 Fig. 3-1-1 Optical conf iguration diagram XGA 1.3 inch 3 plates system B -2 -1 UHP (120W) A 15 9 9 11 8 8 7 4 5 4 3 2 1 6 13 14 12 13 13 10 12 10 10 9 -3 -1 -2.
4-1 4. R.G.B. DRIVE CIRCUIT 4-1. Outline The outline of RGB drive circuit is described belo w using the G process of the RGB driv e circuit as an example. Fig. 4-1-1 In the panel, 1024 pixels are arranged in a horizontal direction and 768 lines of the pixels are in a ve rtical as sho wn in Fig.
4-2 1 2 3 4 5 6 7 8 9 10 11 12 Pixel Inverted phase 2 voltage Inverted phase 1 voltage Center voltage 1st line 2nd line 1 2 3 4 5 6 7 8 9 10 11 12 Pixel Normal phase 1 voltage Normal phase 2 voltage I.
4-3 4-2. Operation Description The video signal of the odd number pixel (e ven number pixel) is sent to Q501 (Q503) base and supplied to pin 16 of Q502 (Q504), LM1201M. The signal is clamped at pin 16 and the pedestal voltage is adjusted at pin 6 after the DC lev el is stabilized and then AC le vel is adjusted at pin 3.
4-4 T able 4-2-2 Input terminal function description Name DX CLX, CLX DIRX, DIRX ENB1 – ENB2 VID1 – VID12 DY CL Y , CL Y DIR Y , DIR Y LCCOM VDDX VDD Y VSSX VSSY NRG NRS1 – NRS2 Function Star t pulse input ter minal of X shift register composing X dr iver .
5-1 5. MICROPR OCESSOR 5-1. System Outline The system microprocessor has features as sho wn belo w . In considering easy maintenance for specif ication modification, etc.
5-2 Fig. 5-1-1 System block diagram PL001 PL001 2 / 2 / 2 / 3 / HC125 QL012 HC125 QL005 PL003 PL006 QL003 PL002 HC14 QL010 HC165 PL009 DRIVE SENSOR PQ20VZ1U QL004 RN5VD27A CA T24C16J QL006 SW LED HC54.
5-3 5-2. System Micr oprocessor The system microprocessor QL002 employs an 8 bit micro-controller (HD64F3337YF16). In this system microprocessor , a program area is pro- vided inside the non-volatile memor y .
5-4 5-3. P ower Suppl y Reset Pr ocess In the po wer supply reset process, power supply reset IC (RN5VD27A), QL004 is employed. The reset IC,QL004, dev elops the reset signal when the po wer supply v .
5-5 5-8. Status Display Pr ocess In the status display process, two-color lighting LEDs of DL037, DL038 and DL039 turn ON for each kind of status shown in the table belo w by using LED0 to LED5 terminal output of the microprocessor .
5-6 T able 5-10-1 I 2 C control f or each kind of video system 5-10. V ideo System Contr ol Pr ocess In the video system control process, control signals are supplied to v arious video system process ICs shown in the table below . T a ble 5-10-1 shows the I 2 C control for each kind of video system.
5-7 5-12. Drive System Control Pr ocess In the driv e system control process, the control signal is supplied to each kind of driv e system process ICs sho wn in the the table below .
5-8 5-14. Applicable Signal V arious kinds of signals are used as the applicable signals in the preset mode (standard v alue) as sho wn in T a ble 5-14-1.
5-9 5-15. RS-232C Control Method Signals are connected to the RS-232C connector in a straight format as shown in T able 5-15-1 RS-232C connection signals. This is because a crossing connec- tion is provided inside the unit. Communication condi- tions are set to meet the conditions giv en in T able 5-15-2.
5-10 Item Normal status RGB Camera (f or TLP511) Common adjustment Video Command PON POF IN1 IN2 IN3 VUP VD W DON DOF MON MOF AO N AO F FON FOF RON ROF CFU CFD CZU CZD ALF ARG AU P AD W RST SA V VCN V.
6-1 6. DIGIT AL CIRCUIT 6-1. Outline A Configuration of digital circuit is sho wn in Fig. 6-1-1. The functions of digital circuit are described on the following pages.
6-2 6-1-1. PLL Circuit The PLL circuit dev elops the clock signal synchronized with the horizontal sync signal, using the horizontal sync signal entered. For RGB signals, a highly stable CXA3106 (QX028) is used. For video signal, a highly traceable TLC2932 (QX029) is used.
6-3 6-2. Each IC Description 6-2-1. PLL IC CXA3106Q (QX028) for RGB Signals A configuration of CXA3106Q is sho wn in F ig. 6-2-1. The PLL IC of CXA3106Q is an IC with high perfor- mance and lo w jitter , and can generate the clock signal synchronized with the horizontal sync signal of max.
6-4 6-2-2. PLL IC TLC2932 (QX029) f or V ideo Signal The PLL IC of TLC2932 is composed of a phase comparator and a VCO. As a frequency di viding circuit is not b uilt in, so the IC works as a PLL circuit by connect- ing to the external VCO terminal of QX028 and using the frequency di viding circuit of QX028.
6-5 INV V RT V RM3 V RM2 V RM1 V RB (ECL) (TTL) CLK (ECL) (TTL) NRSET SELECT CLK OUT P2D7 (MSB) P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 (LSB) (MSB) (LSB) V IN R1 R/2.
6-6 6-2-6. Pictur e Size of V iew Con version IC T -FORC (QX204, QX404, QX604) A configuration of T -FORC is shown in Fi g. 6-2-5. The T -FORC is a newly dev eloped picture size con v ersion IC. By using the IC, smooth picture enlargement and reduction, and format conv ersion will be made.
7-1 7 . VIDEO CIRCUIT 7-1. Circuit Component The video circuit performs selection of input signals, video signal (NTSC, P AL, SECAM) demodulation to RGB signals, RGB input signal amplification and audio signal amplification. Fig. 7-1-1 shows the block diagram.
7-2 Fig. 7-1-1 Block diagram.
7-3 25 26 9 11 3 5 6 34 31 29 37 39 13 14 33 32 QV005 TDA9141 Y2 C2 S2 LEV REV Y3 SCL L OUT 1 C OUT 1 Y OUT 1 V OUT 1 Y IN 1 C IN 1 AUDIO Microprocessor R OUT 1 SDA C3 L R Y S1/S2 C Y C CAMERA S RGB AUDIO 44 46 LV1 RV1 L R VIDEO AUDIO 43 45 V1 Y1 VIDEO COMB FILTER QV001 CXA1855Q QV002 TC9090AN 7-2.
7-4 Fig. 7-2-2 Internal block diagram of CXA1855Q 34 6 dB VOUT1 YIN1 YOUT1 TRAP1 6 dB 0 dB 0 dB 0 dB 0 dB 41 TV 27 EV 43 V1 1 V2 7 V3 45 Y1 3 Y2 9 Y3 47 C1 5 C2 11 C3 31 37 35 6 dB 6 dB 6 dB COUT1 39 .
7-5 7-3. V ideo Demodulation Block 7-3-1. Y/C Separation Circuit This circuit separates Y and C signals from a composite video signal. Fig. 7-3-1 shows the pin configuration of TC9090AN and Fig. 7-3-2 shows the block diagram. The composite video signal enters pin 3.
7-6 Serial data input/output Serial clock input Horizontal PLL filter Sand castle output Vertical acquisition synchronization pulse Clamping pulse/ H A synchronization pulse input/output RED input GRE.
7-7 SIGNAL CLAMPING SIGNAL CLAMPING ± (R-Y) ± (R-Y) ± (B-Y) ± (B-Y) Color difference input signals V P1 Sand castle pulse input analog supply SANDCASTLE DETECTOR GND 1 FREQUENCY PHASE DETECTOR DIV.
7-8 7-3-4. Color Signal Process Circuit The color signal is lev el adjusted in the A CC (automa tic color control) circuit, corrected in passing through a band pass circuit in the NTSC/P AL system, or a bell filter correction is carried out in the SECAM system, and then enters the color demodulation circuit.
7-9 Fig. 7-3-9 Block diagram of TDA4672 7-3-6. RGB Demodulation The demodulation from Y and color difference signals to RGB signals is carried out by QV008, T D A4780. Fig. 7- 3-10 shows the pin conf iguration of TD A4780 and Fig. 7-3-11 sho ws the block diagram.
7-10 T able 7-3-4 T erminal function of TD A4780 Fig. 7-3-11 Block diagram of TDA4780 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name FSW 2 R 2 G 2 B 2 V P –(B–Y) –(R–Y) Y GND R 1 G 1 B 1 FSW 1 .
7-11 QV001 INPUT SELECTOR CXA1855Q VIDEO RGB LINEOUT BUFFER BUFFER DAC VOL / MUTE SOUND OUT SPEAKER 1.5W VOLUME MUTE L R L R L R CXA1315M QA01 M5222FP QA02 TDA7056A 7-3-7. A udio Circuit Fig. 7-3-12 shows the audio circuit block diagram. Signal path from the QV001 to the LINE OUT terminal is: QV001 ® transistor buffer ® LINE OUT terminal.
7-12 7-4. RGB Signal Amplification Section 7-4-1. RGB Signal Switch Circuit The RGB input signals and the video signal demodu- lated into RGB signals are switched by QB011 (Analog SW: M52348FP). The block diagram of QB011 is shown in Fig. 7-4-1. 7-4-2.
7-13 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 R BRIGHTNESS G BRIGHTNESS B BRIGHTNESS R HOLD R AMP G HOLD G AMP B HOLD B AMP R BLANKING R OSD M.
7-14 7-5. Microprocessor Interface The peripheral block diagram of the microprocessor sho ws in Fig. 7-5-1. All kinds of control suc h as signal SW , etc .
7-15 QB012 (M52347FP) Input status Pin 6: HD . COMP HD . COMP . (POS.) HD . COMP . (POS.) HD . COMP . (POS.) HD . COMP . (NEG.) HD . COMP . (NEG.) HD . HD . COMP . (NEG.) NON NON NON Pin 8: VD NON VD (POS .) VD (NEG.) NON VD (POS .) VD (NEG.) NON VD (POS .
8-1 8. CCD CAMERA CIRCUIT (F or TLP511) 8-1. Outline The camera section of the unit employs the color board camera with 3 times zoom lens. T he camera video circuit is assembled in one PC board and co.
8-2 Fig. 8-1-1 CCD camera circuit block diagram.
9-1 9. FLUORESCENT LAMP INVER TER CIRCUIT (F or TLP511) 9-1. Operating Description The base current at start-up passes through QI002, RI003, RI004, RI009 and then flows into the base of QI003. QI002 works as a ON/OFF switch for start-up operation and turns ON when the base v oltage de v elops “L”.
9-2 CI005 and CI006 are capacitor s to stabilize the fluores- cent lamp discharging current. After the discharging starts, C I005 and CI006 limit the flo w of the current with the reactance (X C = 1/ w c) of C I005 and CI006. Before the fluorescent lamp turns on, the collector pulse of Q I007 is 70 – 80 V(p-p).
TOS H I B A AMERICA CONSUMER PRODUCTS, INC. NA TIONAL SER VICE DIVISION 1420-B T OSHIBA DRIVE LEBANON, TN 37087.
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