Instruction/ maintenance manual of the product TMS320DM648 Texas Instruments
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TMS320DM647/DM648 Video Port/VCXO Interpolated Control (VIC) Port User's Guide Literature Number: SPRUEM1 May 2007.
2 SPRUEM1 – May 2007 Submit Documentation Feedback.
Contents Preface .............................................................................................................................. 13 1 Overview .............................................................................................
3.3.3 Y/C Image Window and Capture ............................................................................. 50 3.3.4 Y/C FIFO Packing .............................................................................................. 51 3.4 BT.656 and Y/C Mode Field and Frame Operation .
3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) ................................................... 86 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM) .................................................. 87 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) .
4.12 Video Display Registers ........................................................................................... 122 4.12.1 Video Display Status Register (VDSTAT) ................................................................ 122 4.12.2 Video Display Control Register (VDCTL) .
6.3 Operational Details .................................................................................................. 169 6.4 Enabling VIC Port .................................................................................................... 170 6.
List of Figures 1-1 Video Port Block Diagram ................................................................................................. 18 1-2 BT.656 Video Capture FIFO Configuration .............................................................
3-39 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) ............................................ 90 3-40 TCI System Time Clock Ticks Interrupt Register (TCITICKS) ........................................................ 90 4-1 NTSC Compatible Interlaced Display .
4-52 Video Display Event Register (VDDISPEVT) ......................................................................... 142 4-53 Video Display Clipping Register (VDCLIP) ............................................................................ 143 4-54 Video Display Default Display Value Register (VDDEFVAL) .
List of Tables 1-1 Video Capture Signal Mapping ........................................................................................... 26 1-2 Video Display Signal Mapping ...........................................................................
4-5 Video Display Control Registers ....................................................................................... 122 4-6 Video Display Status Register (VDSTAT) Field Descriptions ....................................................... 123 4-7 Video Display Control Register (VDCTL) Field Descriptions .
Preface SPRUEM1 – May 2007 Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs). Notational Conventions This document uses the following conventions.
www.ti.com Related Documentation From Texas Instruments SPRUEK8 — TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP).
www.ti.com Related Documentation From Texas Instruments SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP).
SPRUEM1 – May 2007 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs). An overview of the video port functions, FIFO configurations, and signal mapping are included. Topic ................
www.ti.com 1.1 Video Port Video Port The video port peripheral can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. It provides the following functions: • Video capture mode: – Capture rate of up to 80 MHZ.
www.ti.com Internal peripheral bus Memory mapped registers Raw video display pipeline Channel B Channel A Raw video display pipeline Y/C video display pipeline BT .656 display pipeline Y/C video capture pipeline Capture/display buf fer (2560 bytes) Raw video capture pipeline BT .
www.ti.com 1.2 Video Port FIFO 1.2.1 EDMA Interface Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with EDMA transfers to move data between the video port FIFO and external or on-chip memory.
www.ti.com 1.2.2 Video Capture FIFO Configurations VDIN[9−2] VDIN[19−12] Capture FIFO A Y Buf fer A (1280 bytes) Cb Buf fer A (640 bytes) 8 8 64 64 Cb Buf fer B (640 bytes) Cr Buf fer B (640 bytes.
www.ti.com VDIN[19−12] 8 Buf fer B (2560 bytes) Capture FIFO B YSRCB 64 VDIN[9−2] 8 Buf fer A (2560 bytes) Capture FIFO A YSRCA 64 Video Port FIFO For 8-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1-3 .
www.ti.com VDIN[19−12] Cr Buf fer (1280 bytes) Cb Buf fer (1280 bytes) 8 8 64 64 CRSRCA CBSRCA Y Buf fer (2560 bytes) VDIN[9−2] 8 64 Capture FIFO YSRCA Video Port FIFO For Y/C video capture, the F.
www.ti.com Data Buf fer (5120 bytes) VDIN[19−2] 16 Capture FIFO YSRCA 64 1.2.3 Video Display FIFO Configurations Y Buf fer (2560 bytes) Cb Buf fer (1280 bytes) Cr Buf fer (1280 bytes) YDST A CBDST C.
www.ti.com Buf fer A (2560 bytes) YDST A VDOUT[9−2] 64 8 Display FIFO A Buf fer B (2560 bytes) YDSTB VDOUT[19−12] 64 8 Display FIFO B Data Buf fer (5120 bytes) YDST A VDOUT[19−2] 64 16 Display FIFO Video Port FIFO For locked raw video, the FIFO is split into channel A and B.
www.ti.com Cr Buf fer (1280 bytes) Cb Buf fer (1280 bytes) CRDST CBDST 64 64 VDOUT[19−12] 8 8 Y Buf fer (2560 bytes) YDST A 64 VDOUT[9−2] Display FIFO 8 1.
www.ti.com 1.4 Video Port Pin Mapping Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1-1 .
www.ti.com 1.4.1 VDIN Bus Usage for Capture Modes Video Port Pin Mapping The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1-3 .
www.ti.com 1.4.2 VDOUT Data Bus Usage for Display Modes 1.5 Video Port Pin Multiplexing 1.6 VideoPort Clocking Video Port Pin Multiplexing The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1-4 . Table 1-4. VDOUT Data Bus Usage for Display Modes (1) Display Mode BT.
SPRUEM1 – May 2007 Video Port This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, EDMA operation, external clock inputs, video port throughput and latency, and the video port control registers.
www.ti.com 2.1 Reset Operation 2.1.1 Power-On Reset 2.1.2 Peripheral Bus Reset 2.1.3 Software Port Reset Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections.
www.ti.com 2.1.4 Capture Channel Reset 2.1.5 Display Channel Reset 2.2 Interrupt Operation Interrupt Operation Note: The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should be polled to make sure the bit is cleared prior to writing to the video port registers.
www.ti.com 2.3 EDMA Operation 2.3.1 Capture EDMA Event Generation EDMA Operation • Display complete not acknowledged (DCNA) bit is set. • GPIO interrupt (GPIO) bit is set. The interrupt signal is a pulse only and does not hold state. The interrupt pulse is generated only when the number of set flags in VPIS transitions from none to one or more.
www.ti.com 2.3.2 Display EDMA Event Generation 2.3.3 EDMA Size and Threshold Restrictions EDMA Operation Display EDMA events are generated based on the amount of room available in the FIFO. The VDTHRLD n value indicates the level at which the FIFO has room to receive another EDMA.
www.ti.com 2.3.4 EDMA Interface Operation 2.4 Video Port Control Registers Video Port Control Registers When the video port is configured for capture (or TCI) mode, it only accepts read requests from the EDMA interface. Write requests are false acknowledged (so the bus does not stall) and the data is discarded.
www.ti.com 2.4.1 Video Port Control Register (VPCTL) Video Port Control Registers The video port control register (VPCTL) determines the basic operation of the video port. Not all combinations of the port control bits are unique. The control bit encoding is shown in Table 2-3 .
www.ti.com Video Port Control Registers Table 2-2. Video Port Control Register (VPCTL) Field Descriptions (continued) Bit field (1) symval (1) Value Description 5 VCT2P OF( value ) VCTL2 pin polarity bit. Does not affect GPIO operation. DEFAULT 0 Indicates the VCTL2 control signal (input or output) is active high.
www.ti.com 2.4.2 Video Port Status Register (VPSTAT) Video Port Control Registers The video port status register (VPSTAT) indicates the current condition of the video port. The video port status register (VPSTAT) is shown in Figure 2-2 and described in Table 2-4 .
www.ti.com 2.4.3 Video Port Interrupt Enable Register (VPIE) Video Port Control Registers The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The video port interrupt enable register (VPIE) is shown in Figure 2-3 and described in Table 2-5 .
www.ti.com Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) Bit field (1) symval (1) Value Description 17 COVRB OF( value ) Capture overrun on channel B interrupt enable bit. DEFAULT 0 Interrupt is disabled.
www.ti.com 2.4.4 Video Port Interrupt Status Register (VPIS) Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) Bit field (1) symval (1) Value Description 3 SERRA OF( value ) Channel A synchronization error interrupt enable bit.
www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) Bit field (1) symval (1) Value Description 23 LFDB OF( value ) Long field detected on channel B interrupt detected bit.
www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) Bit field (1) symval (1) Value Description 17 COVRB OF( value ) Capture overrun on channel B interrupt detected bit. COVRB is set when data in the FIFO was overwritten before being read out (by the EDMA).
www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) Bit field (1) symval (1) Value Description 7 LFDA OF( value ) Long field detected on channel A interrupt detected bit.
www.ti.com Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) Bit field (1) symval (1) Value Description 1 COVRA OF( value ) Capture overrun on channel A interrupt detected bit. COVRA is set when data in the FIFO was overwritten before being read out (by the EDMA).
SPRUEM1 – May 2007 Video Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, an EDMA is performed to move data from the FIFO into DSP memory.
www.ti.com 3.1 Video Capture Mode Selection 3.2 BT.656 Video Capture Mode 3.2.1 BT.656 Capture Channels 3.2.2 BT.656 Timing Reference Codes Video Capture Mode Selection The video capture module operates in one of five modes as listed in Table 3-1 .
www.ti.com BT.656 Video Capture Mode Table 3-2. BT.656 Video Timing Reference Codes Data Bit 1 st Byte (FFh) 2 nd Byte (00h) 3 rd Byte (00h) 4 th Byte (XYh) 9 (MSB) 1 0 0 1 8 1 0 0 F (field) (1) 7 1 0.
www.ti.com 3.2.3 BT.656 Image Window and Capture Capture Image Ystart Xstart Ystop Xstop Field 1 Capture Image Ystart Xstart Ystop Xstop Field 2 Hcount=0 Ycount=1 Ycount=1 BT.
www.ti.com 3.2.4 BT.656 Data Sampling 3.2.5 BT.656 FIFO Packing BT.656 Video Capture Mode Table 3-5. Common Video Source Parameters Number of Active Lines Video Source (Field 1/Field 2) Number of Active Pixels Field Rate (Hz) square pixel 240/240 640 60 60 Hz/525 lines BT.
www.ti.com Cr 1 Cr 9 Cb 1 Cb 9 Y 1 Y 9 Y 17 Y 25 Cr 2 Cr FIFO Little-Endian Packing Cr 6 Cr 14 Cb 6 Cb 14 Y 6 Y 14 Y 22 Y 30 Cb 0 Y 23 Cr 7 Cr 15 63 Cb 7 Cb 15 63 Y 7 Y 15 Cb FIFO Y FIFO 55 56 55 56 Y.
www.ti.com 3.3.4 Y/C FIFO Packing Cr 9 Cr 1 Cb 9 Cb 1 Y 9 Y 1 Y 25 Y 17 Cb 5 Y 10 Little-Endian Packing Cr 14 Cr 6 Y 0 Cb 0 Cb 14 Cb 6 Y 14 Y 6 Y 30 Y 22 Y 23 Cr 15 Cr 7 Cb 15 Cb 7 Y 15 Y 7 Cr FIFO Cb.
www.ti.com 3.4.1 Capture Determination and Notification BT.656 and Y/C Mode Field and Frame Operation to which a continuous stream of fields are stored without DSP intervention. In other cases, the DSP may need to modify EDMA pointer addresses after each field or frame is captured.
www.ti.com 3.4.2 Vertical Synchronization BT.656 and Y/C Mode Field and Frame Operation Table 3-6. BT.656 and Y/C Mode Capture Operation (continued) VC x CTL Bit CON FRAME CF2 CF1 Operation 1 0 0 1 Continuous field 1 capture. Capture only field 1. F1C is set after field 1 capture and causes CCMPx to be set (CCMPx interrupt can be disabled).
www.ti.com V F 5 1 1 Line VRST=0 1 0 525 1 262 VCOUNT Field 1 Blanking Field 2 Blanking Field 1 Active Field 2 Active Field 1 FINV=0 FINV=1 Field 2 1 1 1 1 0 1 0 1 4 3 2 1 2 3 4 5 19 20 21 0 1 0 0 0 0.
www.ti.com 3.4.3 Horizontal Synchronization VDIN[9−2] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Cr 359 Y 719 Y 0 Cr 0 Y 1 Cb 1 One Line XY .0 10.
www.ti.com n n n 140 2 60 n 1440 Active V ideo 124 Y 2 Blanking Data 1 721 779 843 VCOUNT VCOUNT EXC=1 HRST=1 EXC=1 HRST=0 HCOUNT 720 HCOUNT VCOUNT 0 A VID EXC=1 HRST=0 EXC=1 HRST=1 HCOUNT 842 HCOUNT .
www.ti.com HSYNC# (VCTL1) VCLKIN VSYNC# (VCTL2) 64 Clocks 64 Clocks 3.4.5 Short and Long Field Detect 3.5 Video Input Filtering Video Input Filtering The field indicator method uses the FID input directly to determine the current field. This is useful for Y/C data streams that do not have embedded EAV and SAV codes.
www.ti.com 3.5.1 Input Filter Modes 3.5.2 Chrominance Re-sampling Operation YCbCr 4:2:2 co-sited input samples chroma-resampled capture results Luma (Y) sample - Chroma (Cb/Cr) samples a b c d e f g h i j k l Cb’ ef = (-3Cb c + 101Cb e + 33Cb g -3Cb i ) / 128 Cr’ ef = (-3Cr c + 101Cr e + 33Cr g - 3Cr i ) / 128 3.
www.ti.com YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results Luma (Y) sample Y’ h = (-3Y e + 32Y g + 70Y h + 32Y i - 3Y k ) / 128 - Chroma (Cb/Cr) samples - a b c d e f g h i j .
www.ti.com a Luma (Y) sample - Chroma (Cb/Cr) samples - b c d e d c b n - 1 n n - 1 n - 2 n - 3 n - 4 n - 3 n - 2 a b c d e SA V n - 1 n EA V n - 4 n - 3 n - 2 Leading edge replicated pixels T railing.
www.ti.com 3.6.1 Horizontal Ancillary (HANC) Data Capture 3.6.2 Vertical Ancillary (VANC) Data Capture 3.7 Raw Data Capture Mode 3.7.1 Raw Data Capture Notification Raw Data Capture Mode No special provisions are made for the capture of HANC data.
www.ti.com 3.7.2 Raw Data FIFO Packing Raw FIFO VDIN[9−2] / VDIN[19−12] VCLKINA / VCLKINB 63 56 55.
www.ti.com Raw FIFO VDIN[19−12] / VDIN[9−2] VCLKINA 63 48 47 32 Raw 2 Raw 3 Raw 6 Raw 7 Little-End.
www.ti.com P ACSTR T VCLKIN CAPEN VDIN[9:2] Sync Byte Byte 1 Byte 2 Byte 3 Byte 4 Start Capture 3.8.3 TCI Capture Error Detection 3.8.4 Synchronizing the System Clock TCI Capture Mode Figure 3-15. Parallel TCI Capture The video port checks for two types of errors during TCI capture.
www.ti.com 27 MHz Modulo 300 Counter 233 PCR Extension PCR Base CTMODE 0 1 STCLK 90 kHz External VCXO 3.8.5 TCI Data Capture Notification TCI Capture Mode counter counts from 0 to 299 at 27 MHz. Each time the 9-bit counter rolls over to 0, the 33-bit counter is incremented by 1.
www.ti.com 3.8.6 Writing to the FIFO TSI FIFO VDIN[9−2] VCLKIN 63 56 55 48 47 40 39 32 TSI 5 TSI 4 T.
www.ti.com 3.9 Capture Line Boundary Conditions Y FIFO Cb FIFO VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Y 5 Y 4 Y 7 .
www.ti.com 3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode 3.11 Capturing Video in Raw Data Mode Capturing Video in Raw Data Mode number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVT x , CbEVT x , and CrEVT x are generated by the video capture module.
www.ti.com 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode 3.12 Capturing Data in TCI Capture Mode Capturing Data in TCI Capture Mode 5. Write to VC x THRLD to set the capture threshold. The threshold needs to be set in units of double word. One double word is equal to 8 bytes.
www.ti.com 3.12.1 Handling FIFO Overrun Condition in TCI Capture Mode 3.13 Video Capture Registers Video Capture Registers 5. Write to TCISTCMPL, TCISTCMPM, TCISTMSKL, and TCISTMSKM if needed to initiate an interrupt, based on STC absolute time. 6. Write to TCITICKS if an interrupt is desired every x cycles of STC.
www.ti.com 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) Video Capture Registers Table 3-13. Video Capture Control Registers (continued) Offset Address (1) Acronym Register Name Section 154h VCBSTOP2 Video Capture Channel B Field 2 Stop Register Section 3.
www.ti.com 3.13.2 Video Capture Channel A Control Register (VCACTL) Video Capture Registers Table 3-14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 31 FSYNC OF( value ) Current frame sync bit.
www.ti.com Video Capture Registers Figure 3-22. Video Capture Channel A Control Register (VCACTL) 31 30 29 24 RSTCH BLKCAP Reserved R/WS-0 R/W-1 R-0 23 22 21 20 19 18 17 16 Reserved RDFE FINV EXC FLDD.
www.ti.com Video Capture Registers Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 19 EXC OF( value ) External control select bit.
www.ti.com 3.13.3 Video Capture Channel x Field 1 Start Register (VCxSTRT1) Video Capture Registers Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 7 CON (2) OF( value ) Continuous capture enable bit.
www.ti.com 3.13.4 Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Video Capture Registers Figure 3-23. Video Capture Channel x Field 1 Start Register (VCxSTRT1) 31 28 27 16 Reserved VCYSTART R-0 R/W-0 15 14 12 11 0 SSE Reserved VCXSTART/VCVBLNKP R/W-1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 3-16.
www.ti.com 3.13.5 Video Capture Channel x Field 2 Start Register (VCxSTRT2) Video Capture Registers Figure 3-24. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) 31 28 27 16 Reserved VCYSTOP R-0 R/W-0 15 12 11 0 Reserved VCXSTOP R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 3-17.
www.ti.com 3.13.6 Video Capture Channel x Field 2 Stop Register (VC xSTOP2) Video Capture Registers Table 3-18. Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 31-28 Reserved - 0 Reserved.
www.ti.com 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCxVINT) Video Capture Registers The video capture channel x vertical interrupt register (VCAVINT, VCBVINT) controls the generation of vertical interrupts in each field.
www.ti.com 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) Video Capture Registers The video capture channel x threshold register (VCATHRLD, VCBTHRLD) determines when EDMA requests are sent. The VCTHRLD1 bits determine when capture EDMA events are generated.
www.ti.com 3.13.9 Video Capture Channel x Event Count Register (VCxEVTCT) 3.13.10 Video Capture Channel B Control Register (VCBCTL) Video Capture Registers The video capture channel x event count register (VCxEVTCT) is programmed with the number of EDMA events to be generated for each capture field.
www.ti.com Video Capture Registers Figure 3-30. Video Capture Channel B Control Register (VCBCTL) 31 30 29 24 RSTCH BLKCAP Reserved R/WS-0 R/W-1 R-0 23 21 20 19 18 17 16 Reserved FINV Reserved VRST HR.
www.ti.com Video Capture Registers Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 16 HRST OF( value ) HCOUNT reset method bit.
www.ti.com 3.13.11 TCI Capture Control Register (TCICTL) Video Capture Registers Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 4 CF1 (2) OF( value ) Capture field 1 bit.
www.ti.com 3.13.12 TCI Clock Initialization LSB Register (TCICLKINITL) Video Capture Registers Table 3-24. TCI Capture Control Register (TCICTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656, Y/C Mode, or Raw Data Mode TCI Mode 3 STEN OF( value ) System time clock interrupt enable bit.
www.ti.com 3.13.13 TCI Clock Initialization MSB Register (TCICLKINITM) 3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) Video Capture Registers The transport stream interface clock initialization MSB register (TCICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock.
www.ti.com 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM) Video Capture Registers Figure 3-34. TCI System Time Clock LSB Register (TCISTCLKL) 31 0 PCR R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 3-27. TCI System Time Clock LSB Register (TCISTCLKL) Field Descriptions Description Bit field symval (1) Value BT.
www.ti.com 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) 3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM) Video Capture Registers The transport stream interface system time clock compare LSB register (TCISTCMPL) is used to generate an interrupt at some absolute time based on the STC.
www.ti.com 3.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) 3.13.19 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) Video Capture Registers Table 3-30. TCI System Time Clock Compare MSB Register (TCISTCMPM) Field Descriptions Description Bit field symval (1) Value BT.
www.ti.com 3.13.20 TCI System Time Clock Ticks Interrupt Register (TCITICKS) Video Capture Registers Figure 3-39. TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) 31 16 Reserved R-0 15 1 0 Reserved ATCM R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 3-32.
www.ti.com 3.14 Video Capture FIFO Registers Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3-34 . These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access.
SPRUEM1 – May 2007 Video Display Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TCI) capture port. This chapter discusses the video display port. Topic .........................
www.ti.com 4.1 Video Display Mode Selection 4.1.1 Image Timing Line 20 Line 21 Line 22 Line 261 Line 262 Line 263 Line 282 Line 283 Line 284 Line 523 Line 524 Line 525 Field 1 Field 2 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4-1 .
www.ti.com Line 26 Line 28 Line 30 Line 742 Line 744 Field 1 Line 27 Line 29 Line 745 Line 743 Line 741 Video Display Mode Selection Figure 4-2. SMPTE 296M Compatible Progressive Scan Display 94 Video.
www.ti.com Field 1 V ertical Blanking Horizontal Blanking Field 1 Image Horiz. Of fset Field 1 Image V ertical Of fset Field 1 Image Width Field 1 Image Height Field 1 Active V ideo Field 1 Frame Field 2 V ertical Blanking Horizontal Blanking Field 2 Image Horiz.
www.ti.com Field 1 Image Width Field 1 Frame Field 1 Image Horizontal Of fset Field 1 Image Height Horizontal Blanking Field 1 V ertical Blanking Field 1 Image V ertical Of fset Field 1 Active V ideo 4.1.2 Video Display Counters Video Display Mode Selection Figure 4-4.
www.ti.com 718 FPCOUNT HBLNK HSYNC 719 720 735 736 799 800 857 0 1 FPCOUNT = HBLNKST AR T FPCOUNT = HBLNKST OP FPCOUNT = HSYNCST OP FPCOUNT = HSYNCST AR T FLCOUNT VBLNK VSYNC FLCOUNT = VSYNCYST OP1 FP.
www.ti.com 4.1.3 Sync Signal Generation 4.1.4 External Sync Operation 4.1.5 Port Sync Operation V ideo port 0 display Can sync to V ideo port 1 display Can sync to V ideo port 2 display 4.2 BT.656 Video Display Mode Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 VDOUT[9−2] VCLKOUT BT.
www.ti.com 4.2.1 Display Timing Reference Codes VDOUT[9−2] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Y 718 Cr 359 Y 719 Y 0 Cr 0 Y 1 Cb 1 One Line XY .
www.ti.com Blanking Optional blanking Line 4 Image: Field 1 Blanking Line 266 Optional blanking Image: Field 2 Line 3 H = 1 (EA V) H = 0 (SA V) 1(V = 1) 10 (V = X) 20 (V = 0) 264 (V = 1) 273 (V = X) 2.
www.ti.com 4.2.2 Blanking Codes 4.2.3 BT.656 Image Display 4.2.4 BT.656 FIFO Unpacking VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Y FIFO Cb FIFO Cb 0 Cr 0 Cb 1 Cr 1 Y 0 Y 1 Y 2 Y 3 Cb 2 Cr 2 Y 4 Y 5.
www.ti.com 4.3 Y/C Video Display Mode 4.3.1 Y/C Display Timing Reference Codes VDOUT[9−2] 80.0 80.0 80.0 FF .C 00.0 00.0 Y 0 Y 5 Y 1916 Y 1917 Y 1918 Y 1919 Y 1 Y 2 Y 3 Y 4 One Line XY .0 80.0 10.0 10.0 FF .C 00.0 00.0 XY .0 80.0 80.0 80.0 FF .C 00.
www.ti.com 4.3.4 Y/C FIFO Unpacking Y FIFO Cb FIFO Y 2 Y 4 Y 6 Y 1 Y 3 Y 5 Y 7 VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Y 21 Y 20 Y 23 Y 22 Y 29 Y 28 Y 31 Y 30 Y 5 Y 4 Y 7 Y 6 Y 13 Y 12 Y 15 Y 14 .
www.ti.com 4.4.2 Chrominance Re-sampling Operation YCbCr 4:2:2 interspersed source pixels YCbCr 4:2:2 co-sited output results Luma (Y) sample Cb’ f = (-3Cb a b + 33Cb cd + 101Cb ef - 3Cb gh ) / 128 Cr’ f = (-3Cr ab + 33Cr cd + 101Cr ef - 3Cr gh ) / 128 Chroma (Cb/Cr) samples - a b c d e f g h i j k l - 4.
www.ti.com 2x upscaled YCbCr 4:2:2 co-sited output YCbCr 4:2:2 interspersed source pixels Luma (Y) sample Cb’ d = (-3Cb ab + 101Cb cd + 33Cb ef - 3Cb gh ) / 128 Cr’ d = (-3Cr ab + 101Cr cd + 33Cr .
www.ti.com a a’ b b’ c c’ d w w’ x x’ a b c d w x y y Cb’ a = (-3Cb c d + 33Cb ab + 101Cb ab -3Cb cd )/128 Cr’ a = (-3Cr cd + 33Cr ab + 101Cr ab -3Cr cd )/128 y’ ab cd z Horizontal Ima.
www.ti.com 4.6.1 Raw Mode RGB Output Support 4.6.2 Raw Data FIFO Unpacking Raw FIFO VDOUT[9−2] VCLKO.
www.ti.com 4.7 Video Display Field and Frame Operation 4.7.1 Display Determination and Notification Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals.
www.ti.com 4.7.2 Video Display Event Generation 4.8 Display Line Boundary Conditions Display Line Boundary Conditions Table 4-4. Display Operation (continued) VDCTL Bit CON FRAME DF2 DF1 Operation 0 1 1 1 Single frame display. Display both fields. FRMD is set after field 2 display and causes DCMPx to be set.
www.ti.com YFIFO CbFIFO VDOUT[9−2] VCLKOUT 63 56 55 48 47 4039 32 Y5 Y4 Y7 Y6 Y69 Y68 Y71 Y70 Y77 Y76 Cb37 Cb36 Cb38 Little-Endian Packing VDOUT[19−12].
www.ti.com 720 721 722 723 735 736 799 800 855 856 857 0 1 7 8 9 10 710 71 1 712 718 719 720 721 703 703 703 703 703 703 703 703 703 703 703 703 0 1 2 702 703 703 703 703 703 703 n + 1 n FLCOUNT VCLKO.
www.ti.com Display Timing Examples The interlaced BT.656 vertical output timing is shown in Figure 4-26 . The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen.
www.ti.com 525 2 1 4 3 6 5 19 Field1active Field1image 20 21 22 23 262 263 264 265 266 267 268 269 282 Field2active 283 284 285 286 Field2image 524 525 1 Field1blanking 1.
www.ti.com FLCOUNT VDOUT[19−2 ] (B) VCLKOUT VCLKIN IPCOUNT VCTL1 (HBLNK) (A)(B) VCTL1 (HSYNC) (A)(B) Blanking n − 1 n + 1 n Raw 0 (R0) Raw 1 (G0) Raw 2 (B0) Raw 3 (R1) Raw 4 (G1) Raw 5 (B1) Raw 21.
www.ti.com 525 2 1 4 3 6 5 19 Field1active Field1image 20 21 22 23 262 263 264 265 266 267 268 269 282 Field2active 283 284 285 286 Field2image 524 525 1 Field1blanking 1.
www.ti.com 4.9.3 Y/C Progressive Display Example Display Timing Examples This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 x 720/60 system. The example is for a 1264 x 716 progressive output image.
www.ti.com (B) VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK) (A)(C) VCTL1 (HSYNC) (A)(C) VCLKOUT VDOUT[9−2] (C) VDOUT[19−2] (C) FLCOUNT n − 1 n + 1 n EA V Blanking Data SA V EA V Blanking Active V ideo D.
www.ti.com 5 FLCOUNT 750 716 716 ILCOUNT Field 1 Blanking Field 1 Blanking Field 1 Active 4 3 2 1 716 716 716 716 25 26 27 716 716 716 745 746 747 748 749 716 716 716 716 716 28 29 Field 1 Image 744 1.
www.ti.com 4.10 Displaying Video in BT.656 or Y/C Mode Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps are needed: 1. To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that the multiplexed pins work as Video Port Pins.
www.ti.com 4.11 Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode 22. Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized.
www.ti.com 4.11.1 Handling Under-run Condition of the Display FIFO Displaying Video in Raw Data Mode by total double words per Y EDMA. 20. Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired. 21. Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and the FPCOUNT increment rate (INCPIX bit).
www.ti.com 4.12 Video Display Registers 4.12.1 Video Display Status Register (VDSTAT) Video Display Registers The registers for controlling the video display mode of operation are listed in Table 4-5 . See the device-specific datasheet for the memory address of these registers.
www.ti.com 4.12.2 Video Display Control Register (VDCTL) Video Display Registers Figure 4-31. Video Display Status Register (VDSTAT) 31 30 29 28 27 16 Reserved FRMD F2D F1D VDYPOS R-0 R/WC-0 R/WC-0 R/WC-0 R-0 15 14 13 12 11 0 Reserved VBLNK VDFLD VDXPOS R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-6.
www.ti.com Video Display Registers The video display is controlled by the video display control register (VDCTL). The video display control register (VDCTL) is shown in Figure 4-32 and described in Table 4-7 .
www.ti.com Video Display Registers Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 23 FXS OF( value ) Field external synchronization enable bit.
www.ti.com Video Display Registers Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 11 DVEN OF( value ) Default value enable bit. DEFAULT 0 Blanking value is output during Not used.
www.ti.com 4.12.3 Video Display Frame Size Register (VDFRMSZ) 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) Video Display Registers The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT).
www.ti.com 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Video Display Registers Figure 4-34. Video Display Horizontal Blanking Register (VDHBLNK) 31 28 27 16 Reserved HBLNKSTOP R-0 R/W-0 15 14 12 11 0 HBDLA Reserved HBLNKSTART R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-9.
www.ti.com 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Video Display Registers Figure 4-35. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 31 28 27 16 Reserved VBLNKYSTART1 R-0 R/W-0 15 12 11 0 Reserved VBLNKXSTART1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-10.
www.ti.com 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Video Display Registers Table 4-11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved - 0 Reserved.
www.ti.com 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Video Display Registers Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.
www.ti.com 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) Video Display Registers The video display field 1 image offset register (VDIMGOFF1) defines the field 1 image offset and specifies the starting location of the displayed image relative to the start of the active display.
www.ti.com 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) Video Display Registers Table 4-14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.
www.ti.com 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) Video Display Registers The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display.
www.ti.com 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) Video Display Registers The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active display.
www.ti.com 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) Video Display Registers Figure 4-43. Video Display Field 1 Timing Register (VDFLDT1) 31 28 27 16 Reserved FLD1YSTART R-0 R/W-0 15 12 11 0 Reserved FLD1XSTART R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-18.
www.ti.com 4.12.15 Video Display Threshold Register (VDTHRLD) Video Display Registers Table 4-19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions (continued) Bit field (1) symval (1) Value Description 11-0 FLD2XSTART OF( value ) 0-FFFh Specifies the pixel on the first line of field 2 where the FLD output is asserted.
www.ti.com 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Video Display Registers Table 4-20. Video Display Threshold Register (VDTHRLD) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.
www.ti.com 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Video Display Registers The video display field 1 vertical synchronization start register (VDVSYNS1) is shown in Figure 4-47 and described in Table 4-22 . Figure 4-47.
www.ti.com 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Video Display Registers Table 4-23.
www.ti.com 4.12.21 Video Display Counter Reload Register (VDRELOAD) Video Display Registers Figure 4-50. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) 31 28 27 16 Reserved VSYNCYSTOP2 R-0 R/W-0 15 12 11 0 Reserved VSYNCXSTOP2 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-25.
www.ti.com 4.12.22 Video Display Event Register (VDDISPEVT) 4.12.23 Video Display Clipping Register (VDCLIP) Video Display Registers The video display event register (VDDISPEVT) is programmed with the number of EDMA events to be generated for display field 1 and field 2.
www.ti.com 4.12.24 Video Display Default Display Value Register (VDDEFVAL) Video Display Registers Figure 4-53. Video Display Clipping Register (VDCLIP) 31 24 23 16 CLIPCHIGH CLIPCLOW R/W-1111-0000 R/W-0001-0000 15 8 7 0 CLIPYHIGH CLIPYLOW R/W-1110-1011 R/W-0001-0000 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-28.
www.ti.com 4.12.25 Video Display Vertical Interrupt Register (VDVINT) Video Display Registers Figure 4-54. Video Display Default Display Value Register (VDDEFVAL) 31 24 23 16 CRDEFVAL CBDEFVAL R/W-0 R/W-0 15 8 7 0 Reserved YDEFVAL R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Figure 4-55.
www.ti.com 4.12.26 Video Display Field Bit Register (VDFBIT) Video Display Registers Figure 4-56. Video Display Vertical Interrupt Register (VDVINT) 31 30 28 27 16 VIF2 Reserved VINT2 R/W-0 R-0 R/W-0 15 14 12 11 0 VIF1 Reserved VINT1 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-30.
www.ti.com 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Video Display Registers Figure 4-57. Video Display Field Bit Register (VDFBIT) 31 28 27 16 Reserved FBITSET R-0 R/W-0 15 12 11 0 Reserved FBITCLR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 4-31.
www.ti.com 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Video Display Registers Table 4-32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 31-28 Reserved - 0 Reserved.
www.ti.com 4.13 Video Display Registers Recommended Values Video Display Registers Recommended Values Table 4-33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.
www.ti.com 4.14 Video Display FIFO Registers Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4-35 . These registers provide EDMA write access to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access.
SPRUEM1 – May 2007 General-Purpose I/O Operation Signals not used for video display or video capture can be used as general-purpose input/output (GPIO) signals. Topic ..................................................................................
www.ti.com 5.1 GPIO Registers GPIO Registers The GPIO register set includes required registers such as peripheral identification and emulation control. The GPIO registers are listed in Table 5-1 . See the device-specific datasheet for the memory address of these registers.
www.ti.com 5.1.1 Video Port Peripheral Identification Register (VPPID) GPIO Registers The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The video port peripheral identification register (VPPID) is shown in Figure 5-1 and described in Table 5-2 .
www.ti.com 5.1.2 Video Port Peripheral Control Register (PCR) GPIO Registers The video port peripheral control register (PCR) determines operation during emulation. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend.
www.ti.com 5.1.3 Video Port Pin Function Register (PFUNC) GPIO Registers The video port pin function register (PFUNC) selects the video port pins as GPIO. Each bit controls either one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO.
www.ti.com GPIO Registers Table 5-4. Video Port Pin Function Register (PFUNC) Field Descriptions (continued) Bit field (1) symval (1) Value Description 10 PFUNC10 OF( value ) PFUNC10 bit determines if VDATA[19-12] pins function as GPIO. DEFAULT 0 Pins function normally.
www.ti.com 5.1.4 Video Port Pin Direction Register (PDIR) GPIO Registers The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as an input.
www.ti.com GPIO Registers Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions (continued) Bit field (1) symval (1) Value Description 12 PDIR12 OF( value ) PDIR12 bit controls the direction of the VDATA[15–12] pins. DEFAULT 0 Pins function as input.
www.ti.com 5.1.5 Video Port Pin Data Input Register (PDIN) GPIO Registers PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin's input buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit.
www.ti.com 5.1.6 Video Port Pin Data Output Register (PDOUT) GPIO Registers The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output. Writes do not affect pins not configured as GPIO outputs. The bits in PDOUT are set or cleared by writing to this register directly.
www.ti.com GPIO Registers Table 5-7. Video Port Pin Data Out Register (PDOUT) Field Descriptions (continued) Bit field (1) symval (1) Value Description 20 PDOUT20 OF( value ) PDOUT20 bit drives the VCTL1 pin only when the GPIO is configured as output.
www.ti.com 5.1.7 Video Port Pin Data Set Register (PDSET) GPIO Registers PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT.
www.ti.com 5.1.8 Video Port Pin Data Clear Register (PDCLR) GPIO Registers PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT.
www.ti.com 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) GPIO Registers The GPIOs can be used to generate DSP interrupts or EDMA events. The PIEN selects which pins may be used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set.
www.ti.com 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) GPIO Registers The PIPOL determines the GPIO pin signal polarity that generates an interrupt. The video port pin interrupt polarity register (PIPOL) is shown in Figure 5-10 and described in Table 5-11 .
www.ti.com 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) GPIO Registers PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt.
www.ti.com 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) GPIO Registers PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect.
SPRUEM1 – May 2007 VCXO Interpolated Control Port This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic .................................................................................................. Page 6.1 Overview .
www.ti.com 6.1 Overview 22k Ω 100pF 5VDC 2.2k Ω 0.1 m F VCXO 27MHz VDAC VIC STCLK VDA T A[7−0](TSIdatain) VCLK1(TSIclock) VCTL1(CAPENA) VCTL2(P ACSTR T) VCTL3(P ACERR) Satellite/ cable decoder with FEC Video port A DSP 6.
www.ti.com 6.3 Operational Details R + kf k u ( 3 Ǹ ( p 2 (2 b * 1) 2 ) ń 3) Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems. This is addressed in the MPEG transport packets by transmitting timing information in the adaptation fields of selected data packets.
www.ti.com 6.4 Enabling VIC Port 6.5 VIC Port Registers Enabling VIC Port Perform the following steps to enable the VIC port. 1. Clear the GO bit in the VIC control register (VICCTL) to 0. 2. Set the PRECISION bits in VICCTL to the desired precision. 3.
www.ti.com 6.5.1 VIC Control Register (VICCTL) VIC Port Registers The VIC control register (VICCTL) is shown in Figure 6-3 and described in Table 6-4 . Figure 6-3. VIC Control Register (VICCTL) 31 16 Reserved R-0 15 4 3 1 0 Reserved PRECISION GO R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 6-4.
www.ti.com 6.5.2 VIC Input Register (VICIN) VIC Port Registers The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1.
www.ti.com 6.5.3 VIC Clock Divider Register (VICDIV) Divider + Rou nd ƪ DCLK ń R ] VIC Port Registers The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. The VIC interpolation frequency is obtained by dividing the module clock.
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