Instruction/ maintenance manual of the product TMS320DM646X DMSOC Texas Instruments
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TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide Literature Number: SPRUEQ7C February 2010.
2 SPRUEQ7C – February 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated.
Preface ....................................................................................................................................... 6 1 Introduction ..........................................................................................
www.ti.com List of Figures 1 EMIF Functional Block Diagram .......................................................................................... 9 2 EMIF Asynchronous Interface .....................................................................
www.ti.com List of Tables 1 EMIF Pins .................................................................................................................. 10 2 Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode .........................
Preface SPRUEQ7C – February 2010 Read This First About This Manual This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices.
www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule.
User's Guide SPRUEQ7C – February 2010 Asynchronous External Memory Interface (EMIF) 1 Introduction This document describes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
EM_CS[5:2] EM_OE EM_RW EM_W AIT[5:2] EM_WE EM_BA[1:0] EM_D[15:0] EM_A[22:0] EMIF SCR VICP DSP ARM EDMA3 Master peripherals www.ti.com Architecture 1.3 Functional Block Diagram Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins.
Architecture www.ti.com 2.3 Signal Descriptions Table 1 describes the function of each of the EMIF pins. Table 1. EMIF Pins Pins(s) I/O Description EM_ A[22:0] O EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is sent to the device.
EM_CS[5:2] EM_WE EM_OE EM_RW EM_W AIT[5:2] EM_BA[1:0] EM_D[15:0] EM_A[22:0] EMIF EM_D[7:0] EM_A[21:0] EM_BA[1:0] DQ[7:0] A[23:2] A[1:0] EMIF 8−bit asynchronous memory a) EMIF to 8-bit memory interface EM_D[15:0] EM_A[21:0] EM_BA[1] DQ[15:0] A[22:1] A[0] EMIF 16−bit asynchronous memory b) EMIF to 16-bit memory interface www.
Architecture www.ti.com 2.5.2 Programmable Asynchronous Parameters The EMIF allows a high degree of programmability for shaping asynchronous accesses. The programmable parameters are: • Setup: The t.
www.ti.com Architecture Table 3. Description of the Asynchronous Configuration Register (ACFG n ) (continued) Parameter Description ASIZE Asynchronous Device Bus Width.
Architecture www.ti.com 2.5.4 Read and Write Operations in Normal Mode Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selected when the SS bit in the asynchronous configuration register (ACFG n ) is cleared to 0.
Internal clock EM_CS[5:2] EM_A/EM_BA EM_D EM_OE EM_WE EM_R W Setup Strobe Hold 2 3 2 Address Data www.ti.com Architecture Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode 15 SPRU.
Architecture www.ti.com 2.5.4.2 Asynchronous Write Operations (Normal Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.
Internal clock EM_CS[5:2] EM_A/EM_BA EM_D EM_OE EM_WE EM_R W Setup Strobe Hold 2 3 2 Address Data www.ti.com Architecture Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode 17 SPR.
Architecture www.ti.com 2.5.5 Read and Write Operations in Select Strobe Mode Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit in the asynchronous configuration register (ACFG n ) is set to 1.
Internal clock EM_CS[5:2 ] EM_A/EM_BA EM_D EM_OE EM_WE EM_R W Setup Strobe Hold 2 3 2 Address Data www.ti.com Architecture Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode.
Architecture www.ti.com 2.5.5.2 Asynchronous Write Operations (Select Strobe Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.
Internal clock EM_CS[5:2 ] EM_A/EM_BA EM_D EM_OE EM_WE EM_R W Setup Strobe Hold 2 3 2 Address Data www.ti.com Architecture Figure 7. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mod.
Architecture www.ti.com 2.5.6 NAND Flash Mode NAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NAND Flash mode individually by setting the appropriate CS n NAND bit in the NAND Flash control register (NANDFCR).
CLE_EM_A[16] ALE_EM_A[17] EM_CS[n] EM_WE EM_OE EM_D[7:0] EM_W AIT[n] EMIF CLE ALE CE WE OE IO[7:0] R/B NAND flash a) Connection to 8-bit NAND device b) Connection to 16-bit NAND device EM_W AIT[n] EM_D[15:0] EM_OE EM_WE EM_CS[n] ALE_EM_A[17] CLE_EM_A[16] EMIF CE IO[15:0] R/B OE WE NAND flash CLE ALE www.
Architecture www.ti.com 2.5.6.4 NAND Read and Program Operations A NAND Flash access cycle is composed of a command, address, and data phase. The EMIF will not automatically generate these three phases to complete a NAND access with one transfer request.
Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 3 Bit 1 Bit 0 Bit 6 Bit 6 Bit 1 Bit 3 Bit 2 Bit 4 Bit 5 Bit 5 Bit 4 Bit 2 Bit 3 Bit 1 Bit 0 Bit 0 p8o p8o .
EM_D[15:0] EM_RW EM_A[1:0] EM_W AIT EM_OE EM_WE EM_CS EM_BA1 GPIOx AEMIF HD[15:0] HR/W HCNTL[1:0] HRDY HDS1 HCS HHWIL HINT HDS2 HAS HPIENA HBED A HBE1 A HPI16 VCC VCC VSS VSS Architecture www.ti.com 2.5.6.7 NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) indicates the raw status of the EM_WAIT n pin.
www.ti.com Architecture 2.5.8 Extended Wait Mode and the EM_WAIT Pin The Extended Wait mode is a mode in which the external asynchronous device may assert control over the length of the strobe period. The Extended Wait mode can be entered by setting the EW bit in the asynchronous configuration register (ACFG n ).
Architecture www.ti.com 2.5.11 Interrupt Support The EMIF has a single interrupt source ( Table 13 ) mapped to the ARM interrupt controller. For more information on the ARM interrupt controller (AINTC), see the TMS320DM646x DMSoC ARM Subsystem Reference Guide ( SPRUEP9 ).
www.ti.com Architecture 2.5.11.2 Interrupt Multiplexing The EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with another interrupt and is therefore always available.
EM_CS EM_WE EM_OE A[18:0] EM_BA[1] EM_D[15:0] CE WE OE LB UB A[19:1] A[0] DQ[15:0] V S S V S S EMIF TC5516100FT−12 Use Cases www.ti.com 3 Use Cases The EMIF allows a high degree of programmability for shaping asynchronous accesses.
R_SETUP ) R_ST ROBE w ǒ t ACC (m ) ) t SU Ǔ t cyc * 1 R_SETUP ) R_ST ROBE ) R_HOLD w t RC (m ) t cyc * 3 R_HOLD w ǒ t H * t OH (m) Ǔ t cyc * 1 TA w t COD (m) t cyc * 1 www.
t RC (m) Strobe Setup Hold EM_CS EM_A[21:0] EM_BA[1:0] EM_OE EM_D[15:0] t ACC (m) t SU t H t COD (m) t OH (m) Use Cases www.ti.com Figure 12. Timing Waveform of an ASRAM Read For a write access, Table 18 lists the AC timing specifications that must be satisfied.
W_ST ROBE w t W P (m) t cyc * 1 W_SET UP ) W_ST ROB E w max ǒ t AW ( m) t cyc , t DS (m) t cyc Ǔ * 1 W_HOLD w max ǒ t WR (m) t cyc , t DH (m ) t cyc Ǔ * 1 W_SET UP ) W_ST ROB E ) W_HOLD w t W C (m) t cyc * 3 t WC (m) Strobe Setup Hold t WR (m) t WP (m) t A W (m) t DS (m) t DH (m) EM_CS EM_A[21:0] EM_BA[1:0] EM_WE EM_D[15:0] www.
R_SETUP ) R_ST ROBE w ǒ t EM_A ) t A CC (m) ) t SU ) t E M_D Ǔ t cyc * 1 R_SETUP ) R_ST ROBE ) R_HOLD w t RC (m ) t cyc * 3 R_HOLD w ǒ t H * t EM_D * t OH (m) * t EM_A Ǔ t cyc * 1 TA w ǒ t EM_CS ) t COD (m) ) t EM _D Ǔ t cyc * 1 Use Cases www.ti.
1 Setup 2 Strobe 3 Hold 4 EM_CS EM_CS (ASRAM) EM_A[21:0]/ EM_BA[1:0] EM_A[21:0]/ EM_BA[1:0] (ASRAM) EM_OE EM_OE (ASRAM) EM_D[15:0] EM_D[15:0] (ASRAM) t CS t CS t RC (m) t EM_A t EM_A t EM_OE t EM_OE t SU t EM_D t ACC (m) t EM_D t OH (m) t H t COD (m) www.
W_ST ROBE w t W P (m) t cyc * 1 W_SET UP ) W_ST ROB E w max ǒ ǒ t EM_A ) t AW ( m) * t EM_W E Ǔ t cyc , ǒ t EM _D ) t DS (m) * t E M_WE Ǔ t cyc Ǔ * 1 W_HOLD w max ǒ ǒ t EM_WE ) t WR (m ) * t E.
www.ti.com Use Cases 3.1.4 Example Using TC5516100FT-12 This section takes you through the configuration steps required to implement Toshiba’s TC55V1664FT-12 ASRAM with the EMIF.
R_SETUP ) R_ST ROBE w ǒ t EM_A ) t A CC (m) ) t SU ) t E M_D Ǔ t cyc * 1 w ( 0. 27 ) 12 ) 5 ) 0.45 ) 10 * 1 w 0.78 R_SETUP ) R_ST ROBE ) R_HOLD w t RC (m ) t cyc * 3 w ǒ 12 10 Ǔ * 3 w * 1.8 R_HOLD w ǒ t H * t EM_D * t OH (m) * t EM_A Ǔ t cyc * 1 w ( 0 * 0.
www.ti.com Use Cases Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A2CR should be configured as in Table 23 .
Use Cases www.ti.com 3.2.2 Meeting AC Timing Requirements for NAND Flash When configuring the EMIF to interface to NAND Flash, you must consider the AC timing requirements of the NAND Flash as well as the AC timing requirements of the EMIF. These can be found in the data sheet for each respective device.
R_SETUP w t CLR (m ) t cyc * 1 R_STROB E w max ǒ ǒ t REA (m ) ) t SU Ǔ t cyc , t RP (m) t cyc Ǔ * 1 R_SETUP ) R_ST ROBE w ǒ t CEA (m) ) t SU Ǔ t cyc * 1 R_HOLD w ǒ t H * t CHZ (m) Ǔ t cyc * 1 .
W_SET UP w max ǒ t CLS (m ) t cyc , t A LS (m ) t cyc , t CS (m) t cyc Ǔ * 1 W_ST ROBE w t W P (m) t cyc * 1 W_SET UP ) W_ST ROB E w t DS (m) t cyc * 1 W_HOLD w max ǒ t CLH (m) t cyc , t ALH (m) t cyc , t CH (m ) t cyc , t DH (m) t cyc Ǔ * 1 W_SET UP ) W_ST ROB E ) W_HOLD w t W C (m) t cyc * 3 Use Cases www.
t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Setup Strobe Hold t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Setup Strobe Hold www.
t CH (m) t WC (m) t ALH (m) t CLH (m) t WP (m) EM_CS ALE_EM_A[1] CLE_EM_A[2] EM_WE EM_D[7:0] t CS (m) t ALS (m) t CLS (m) t DS (m) t DH (m) Setup Strobe Hold Use Cases www.
www.ti.com Use Cases 3.2.3 Example Using Hynix HY27UA081G1M This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M NAND Flash with the EMIF.
R_SETUP w t CLR (m ) t cyc * 1 w ǒ 10 10 Ǔ * 1 w 0 R_STROB E w max ǒ ǒ t REA (m ) ) t SU Ǔ t cyc , t RP t cyc Ǔ * 1 w ǒ 65 10 Ǔ * 1 w 5.5 R_SETUP ) R_ST ROBE w ǒ t CEA ) t S U Ǔ t cyc * 1 w .
www.ti.com Use Cases Since the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fields are equal to EMIF clock cycles minus 1 cycle, the A1CR should be configured as in Table 30 .
Registers www.ti.com 4 Registers The external memory interface (EMIF) is controlled by programming its internal memory-mapped registers (MMRs). Table 32 lists the memory-mapped registers for the EMIF. See the device-specific data manual for the memory address of these registers.
www.ti.com Registers 4.1 Revision Code and Status Register (RCSR) The revision code and status register (RCSR) is shown in Figure 20 and described in Table 33 .
Registers www.ti.com 4.2 Asynchronous Wait Cycle Configuration Register (AWCCR) The asynchronous wait cycle configuration register (AWCCR) is used to configure the parameters for extended wait cycles. Both the polarity of the EM_WAIT[5:2] pins and the maximum allowable number of extended wait cycles can be configured.
www.ti.com Registers Table 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued) Bit Field Value Description 17-16 CS2_WAIT 0-3h EM_WAIT[5:2] pin map for chip select 2. By default, the EM_WAIT[2] pin is used for chip select 2.
Registers www.ti.com 4.3 Asynchronous n Configuration Registers (A1CR-A4CR) The asynchronous configuration register (ACFG n ) is used to configure the shaping of the address and control signals during an access to asynchronous memory. It is also used to program the width of asynchronous interface and to select from various modes of operation.
www.ti.com Registers 4.4 EMIF Interrupt Raw Register (EIRR) The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-generated interrupts.
Registers www.ti.com 4.5 EMIF Interrupt Mask Register (EIMR) Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) is used to monitor and clear the status of the EMIF’s hardware-generated interrupts.
www.ti.com Registers Table 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued) Bit Field Value Description 0 ATM Asynchronous Timeout Masked.
Registers www.ti.com 4.6 EMIF Interrupt Mask Set Register (EIMSR) The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit is set to 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs.
www.ti.com Registers Table 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued) Bit Field Value Description 0 ATMSET Asynchronous Timeout Mask Set.
Registers www.ti.com 4.7 EMIF Interrupt Mask Clear Register (EIMCR) The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If a bit is read as 1, the corresponding bit in the EMIF interrupt mask register (EIMR) is set and an interrupt is generated when the associated interrupt condition occurs.
www.ti.com Registers Table 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued) Bit Field Value Description 0 ATMCLR Asynchronous Timeout Mask Clear. This bit determines whether or not the asynchronous timeout interrupt is enabled.
Registers www.ti.com 4.8 NAND Flash Control Register (NANDFCR) The NAND Flash control register (NANDFCR) is shown in Figure 27 and described in Table 40 .
www.ti.com Registers 4.9 NAND Flash Status Register (NANDFSR) The NAND Flash status register (NANDFSR) is shown in Figure 28 and described in Table 41 . Figure 28. NAND Flash Status Register (NANDFSR) 31 16 Reserved R-0 15 4 3 0 Reserved WAITST R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 41.
Registers www.ti.com Figure 29. NAND Flash n ECC Register (NANDECC n ) 31 28 27 26 25 24 Reserved P2048O P1024O P512O P256O R-0 R-0 R-0 R-0 R-0 23 22 21 20 19 18 17 16 P128O P64O P32O P16O P8O P4O P2O.
www.ti.com Appendix A Revision History Table 43 lists the changes made since the previous version of this document. Table 43. Document Revision History Reference Additions/Modifications/Deletions Figure 1 Changed figure. Table 1 Changed table. Figure 2 Changed figure.
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