Instruction/ maintenance manual of the product TMS320C6452 DSP Texas Instruments
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TMS320C6452 DSP DDR2 Memory Controller User's Guide Literature Number: SPRUF85 October 2007.
2 SPRUF85 – October 2007 Submit Documentation Feedback.
Contents Preface ............................................................................................................................... 6 1 Introduction .........................................................................................
List of Figures 1 DDR2 Memory Controller Block Diagram ............................................................................... 10 2 DDR2 Memory Controller Signals ................................................................................
List of Tables 1 DDR2 Memory Controller Signal Descriptions ......................................................................... 12 2 DDR2 SDRAM Commands ............................................................................................
Preface SPRUF85 – October 2007 Read This First About This Manual This document describes the operation of the DDR2 Memory Controller in the TMS320C6452. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h.
www.ti.com Related Documents From Texas Instruments SPRUF87 — TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space.
www.ti.com Related Documents From Texas Instruments SPRUF97 — TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal Processor (DSP).
1 Introduction 1.1 Purpose of the Peripheral 1.2 Features 1.3 Functional Block Diagram User's Guide SPRUF85 – October 2007 DSP DDR2 Memory Controller This document describes the DDR2 memory controller in the device. The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices.
www.ti.com L1 S1 M1 D1 Data path A Register file A Register file B D2 Data path B S2 M2 L2 L1 data memory controller Cache control Memory protection Interrupt and exception controller Power control In.
www.ti.com 2 Peripheral Architecture 2.1 Clock Control 2.2 Memory Map 2.3 Signal Descriptions Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh.
www.ti.com DDR_D[31:0] DDR2 memory controller DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_DQS[3:0] DDR_A[13:0] DDR_VREF DDR_DQGA TE[3:0] DDR_DQS[3:0] DDR_ODT[1:0] Peripheral Architecture Figure 2. DDR2 Memory Controller Signals Table 1.
www.ti.com 2.4 Protocol Description(s) Peripheral Architecture The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 . Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row.
www.ti.com 2.4.1 Mode Register Set (MRS and EMRS) COL MRS/EMRS BANK DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.4.2 Refresh Mode Peripheral Architecture DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation.
www.ti.com REFR DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.4.3 Activation (ACTV) ACTV BANK ROW DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] Peripheral Architecture Figure 4.
www.ti.com 2.4.4 Deactivation (DCAB and DEAC) DCAB DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:1 1, 9:0] DDR_A[10] DEAC DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_R.
www.ti.com 2.4.5 READ Command DDR_D[31:0] DDR_DQS[3:0] COL BANK DDR_A[10] CAS Latency D0 D1 D2 D3 D4 D5 D6 D7 DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] Peripheral Architecture Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM.
www.ti.com 2.4.6 Write (WRT) Command DDR_D[31:0] DDR_DQS[3:0] COL BANK DQM7 Sample D0 D1 D2 D3 D4 D5 D6 D7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8 Write Latency DDR_A[10] DDR_CLK DDR_CLK DDR_CS DDR_CKE DDR_RAS DDR_WE DDR_DQM[3:0] DDR_CAS DDR_BA[2:0] DDR_A[13:0] 2.
www.ti.com DDR2 memory controller data bus DDR_D[31:24] (Byte Lane 3) DDR_D[23:16] (Byte Lane 2) DDR_D[15:8] (Byte Lane 1) DDR_D[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device 2.6 Address Mapping Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller.
www.ti.com Peripheral Architecture SDCFG Bit Logical Address IBANK PAGESIZE 31:28 27 26 25 24 23 22:17 16 15 14 13 12 11 10 9:2 0 0 X X X X X nrb=14 (1) ncb=8 1 0 X X X X nrb=14 nbb=1 ncb=8 2 0 X X X .
www.ti.com Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. M Row 0, bank 0 Row 0, bank 1 Row 0, bank 2 Row 0, bank P Row 1, bank 1 Row 1, bank 0 Row 1, bank 2 Row 1, bank P Row N, bank 2 Row N, bank 1 Row N, bank 0 Row N, bank P Peripheral Architecture Figure 11 shows how the DSP memory map is partitioned into columns, rows, and banks.
www.ti.com 0 1 2 3 M Bank 0 Row 0 Row 1 Row 2 Row N C o l l C o l C o l C o Row 0 Row N Row 1 Row 2 C C Bank 1 l l 0 2 1 o o C C l l 3 M o o Row 0 Row N Row 1 Row 2 C C Bank 2 l l 0 2 1 o o l l l l Row N Row 2 Row 0 Row 1 Bank P 0123 M C C l l 3 M o o o C o C o C o C 2.
www.ti.com Command/Data Scheduler Command FIFO W rite FIFO Read FIFO Registers Command to Memory W rite Data to Memory Read Data from Memory Command Data EDMA BUS 2.7.1 Command Ordering and Scheduling, Advanced Concept Peripheral Architecture Figure 15.
www.ti.com 2.7.2 Command Starvation Peripheral Architecture Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering: • Among all pending reads, selects reads to rows already open.
www.ti.com 2.7.3 Possible Race Condition 2.8 Refresh Scheduling Peripheral Architecture A race condition may exist when certain masters write data to the DDR2 memory controller.
www.ti.com 2.9 Self-Refresh Mode 2.10 Reset Considerations Hard resetfrom PLLCTL1 DDR PSC DDR2 memory controller registers State machine VRST VCTL_RST Peripheral Architecture Setting the self refre.
www.ti.com 2.11 DDR2 SDRAM Memory Initialization 2.11.1 DDR2 SDRAM Device Mode Register Configuration Values Peripheral Architecture DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device. These registers control parameters such as burst type, burst length, and CAS latency.
www.ti.com 2.11.2 DDR2 SDRAM Initialization After Reset 2.11.3 DDR2 SDRAM Initialization After Register Configuration 2.12 Interrupt Support 2.13 EDMA Event Support 2.
www.ti.com 3 Using the DDR2 Memory Controller 3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices. The steps required to configure the DDR2 memory controller for external memory access are also described.
www.ti.com CK CK CKE CS WE RAS CAS LDM UDM LDQS UDQS BA[2:0] A[12:0] DQ[15:0] VREF DDR2 memory x16−bit LDQS UDQS DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_DQM0 DDR_CAS DDR_DQM1 DDR_DQS0 DDR_.
www.ti.com DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM0 DDR_DQM1 DDR_DQS0 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_VREF DDR_ODT0 DDR_DQS0 DDR_DQS1 CK CK CKE CS WE RAS CAS LDM.
www.ti.com CK CK CKE CS WE RAS CAS DM DQS BA[2:0] A[13:0] DQ[7:0] VREF DDR2 memory x8−bit DQS RDQS DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_DQM0 DDR_CAS DDR_DQS0 DDR_DQS0 DDR_BA[2:0] DDR_A[.
www.ti.com 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications 3.2.1 Programming the SDRAM Configuration Register (SDCFG) 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC) Using the DDR2 Memory Controller The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses.
www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2) Using the DDR2 Memory Controller Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value t REF Average Periodic Refresh Interval 7.
www.ti.com 3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL) Using the DDR2 Memory Controller Table 15. SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sh.
www.ti.com 4 DDR2 Memory Controller Registers DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller.
www.ti.com 4.1 Module ID and Revision Register (MIDR) 4.2 DDR2 Memory Controller Status Register (DMCSTAT) DDR2 Memory Controller Registers The Module ID and Revision register (MIDR) is shown in Figure 20 and described in Table 18 .
www.ti.com 4.3 SDRAM Configuration Register (SDCFG) DDR2 Memory Controller Registers The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory.
www.ti.com DDR2 Memory Controller Registers Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued) Bit Field Value Description 11-9 CL CAS latency. The value of this field defines the CAS latency, to be used when accessing connected SDRAM devices.
www.ti.com 4.4 SDRAM Refresh Control Register (SDRFC) DDR2 Memory Controller Registers The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state.
www.ti.com 4.5 SDRAM Timing 1 Register (SDTIM1) DDR2 Memory Controller Registers The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR_CLK is equal to the period of the DDR_CLK signal.
www.ti.com DDR2 Memory Controller Registers Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued) Bit Field Value Description 1-0 T_WTR These bits specify the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
www.ti.com 4.6 SDRAM Timing 2 Register (SDTIM2) DDR2 Memory Controller Registers Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory.
www.ti.com 4.7 Burst Priority Register (BPRIO) DDR2 Memory Controller Registers The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller.
www.ti.com 4.8 DDR2 Memory Controller Control Register (DMCCTL) DDR2 Memory Controller Registers The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 27 and described in Table 25 .
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