Instruction/ maintenance manual of the product MSP430x4xx Texas Instruments
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2005 Mixed Signal Products User ’ s G uide SLAU056E.
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Related Documentation From T exas Instruments iii Preface Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices.
Glossary iv Glossary ACLK Auxiliary Clock See Basic Clock Module ADC Analog-to-Digital Converter BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes BSL Bootstrap Loader See www .
Register Bit Conventions v Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and.
vi.
Contents vii Contents 1 Introduction 1-1 1.1 Architecture 1-2 1.2 Flexible Clock System 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Embedded Emulation 1-3 . . . . . . . . . . . . .
Contents viii 3.3.5 Indirect Register Mode 3-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Indirect Autoincrement Mode 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents ix 7 Hardware Multiplier 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Hardware Multiplier Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents x 1 1 Basic Timer1 1 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Basic T imer1 Introduction 1 1-2 . . . . . . . . . . . . . . . . . . . . . . . .
Contents xi 15 USART Peripheral Interface, SPI Mode 15-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 USAR T Introduction: SPI Mode 15-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xii 19 LCD_A Controller 19-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 LCD_A Controller Introduction 19-2 . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xiii 22 SD16_A 22-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 SD16_A Introduction 22-2 22.2 SD16_A Operation 22-4 . . . . . . . . . . . .
1-1 Introduction Introduction This chapter describes the architecture of the MSP430. T opic Page 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flexible Clock System 1-2 . .
Architecture 1-2 Introduction 1.1 Architecture Th e MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB).
Embedded Emulation 1-3 Introduction Figure 1−1. MSP430 Architecture ACLK Bus Conv . Peripheral MAB 16-Bit MDB 16-Bit MCLK SMCLK Clock System Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Watchdog RAM Flash/ RISC CPU 16-Bit JT AG/Debug ACLK SMCLK ROM MDB 8-Bit JT AG 1.
Address Space 1-4 Introduction 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps.
Address Space 1-5 Introduction 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules.
2-1 System Resets, Interrupts, and Operating Modes System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, and operating modes. T opic Page 2.1 System Reset and Initialization 2-2 . . . . . . . .
System Reset and Initialization 2-2 System Resets, Interrupts, and Operating Modes 2.1 System Reset and Initialization Th e system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal.
System Reset and Initialization 2-3 System Resets, Interrupts, and Operating Modes 2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the V CC terminal.
System Reset and Initialization 2-4 System Resets, Interrupts, and Operating Modes 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: - The RST /NMI pin is configured in the reset mode. - I/ O pins are switched to input mode as described in the Digital I/O chapter .
System Reset and Initialization 2-5 System Resets, Interrupts, and Operating Modes 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules i n the connection chain as shown in Figure 2 − 3. The nearer a module is to the CPU/NMIRS, the higher the priority .
System Reset and Initialization 2-6 System Resets, Interrupts, and Operating Modes 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE, OFIE).
System Reset and Initialization 2-7 System Resets, Interrupts, and Operating Modes Figure 2 − 4. Block Diagram of (Non)-Maskable Interrupt Sources Flash Module KEYV System Reset Generator V CC POR PUC WDTQn EQU PUC POR PUC POR NMIRS Clear S WDTIFG IRQ WDTIE Clear IE1.
System Reset and Initialization 2-8 System Resets, Interrupts, and Operating Modes Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator . The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit.
System Reset and Initialization 2-9 System Resets, Interrupts, and Operating Modes Example of an NMI Interrupt Handler Th e NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits.
System Reset and Initialization 2-10 System Resets, Interrupts, and Operating Modes Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual.
System Reset and Initialization 2-1 1 System Resets, Interrupts, and Operating Modes Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2 − 7.
System Reset and Initialization 2-12 System Resets, Interrupts, and Operating Modes 2.2.4 Interrupt V ectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in T able 2 − 1.
Operating Modes 2-13 System Resets, Interrupts, and Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2 − 9.
Operating Modes 2-14 System Resets, Interrupts, and Operating Modes Figure 2 − 9. MSP430x4xx Operating Modes For Basic Clock System Active Mode CPU Is Active Peripheral Modules Are Active LPM0 CPU O.
Operating Modes 2-15 System Resets, Interrupts, and Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes.
Principles for Low - Power Applications 2-16 System Resets, Interrupts, and Operating Modes 2.4 Principles for Low - Power Applications Often, the most important factor for reducing power consumption is using the MSP430 ’ s clock system to maximize the time in LPM3.
3-1 RISC 16-Bit CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. T opic Page 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Introduction 3-2 RISC 16-Bit CPU 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and th e use of high-level languages such as C. The CPU can address the complete address range without paging.
CPU Introduction 3-3 RISC 16-Bit CPU Figure 3−1. CPU Block Diagram 0 15 MDB − Memory Data Bus Memory Address Bus − MAB 16 Zero, Z Carry , C Overflow , V Negative, N 16−bit ALU dst src R8 Gener.
CPU Registers 3-4 RISC 16-Bit CPU 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed.
CPU Registers 3-5 RISC 16-Bit CPU 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
CPU Registers 3-6 RISC 16-Bit CPU 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register , can be used in the register mode only addressed with word instructions. The remain- ing combinations of addressing modes are used to support the constant gen- erator .
CPU Registers 3-7 RISC 16-Bit CPU 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in T able 3 − 2.
CPU Registers 3-8 RISC 16-Bit CPU 3.2.5 General − Purpose Registers R4 - R15 The twelve registers, R4 − R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions as shown in Figure 3 − 7.
Addressing Modes 3-9 RISC 16-Bit CPU 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in T able 3 − 3 describe the contents of the As (source) and Ad (destination) mode bits.
Addressing Modes 3-10 RISC 16-Bit CPU 3.3.1 Register Mode The register mode is described in T able 3 − 4. T able 3 − 4. Register Mode Description Assembler Code Content of ROM MOV R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R1 1.
Addressing Modes 3-1 1 RISC 16-Bit CPU 3.3.2 Indexed Mode The indexed mode is described in T able 3 − 5. T able 3 − 5. Indexed Mode Description Assembler Code Content of ROM MOV 2(R5),6(R6) MOV X(.
Addressing Modes 3-12 RISC 16-Bit CPU 3.3.3 Symbolic Mode The symbolic mode is described in T able 3 − 6. T able 3 − 6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI MOV X(P.
Addressing Modes 3-13 RISC 16-Bit CPU 3.3.4 Absolute Mode The absolute mode is described in T able 3 − 7. T able 3 − 7. Absolute Mode Description Assembler Code Content of ROM MOV &EDE,&TONI MOV X(0),Y(0) X = EDE Y = TONI Length: T wo or three words Operation: Move the contents of the source address EDE to the destination address TONI.
Addressing Modes 3-14 RISC 16-Bit CPU 3.3.5 Indirect Register Mode The indirect register mode is described in T able 3 − 8. T able 3 − 8. Indirect Mode Description Assembler Code Content of ROM MO.
Addressing Modes 3-15 RISC 16-Bit CPU 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in T able 3 − 9. T able 3 − 9.
Addressing Modes 3-16 RISC 16-Bit CPU 3.3.7 Immediate Mode The immediate mode is described in T able 3 − 10. T able 3 − 10. Immediate Mode Description Assembler Code Content of ROM MOV #45h,TONI MOV @PC+,X(PC) 45 X = TONI − PC Length: T wo or three words It is one word less if a constant of CG1 or CG2 can be used.
Instruction Set 3-17 RISC 16-Bit CPU 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions.
Instruction Set 3-18 RISC 16-Bit CPU 3.4.1 Double-Operand (Format I) Instructions Figure 3 − 9 illustrates the double-operand instruction format. Figure 3 − 9. Double Operand Instruction Format B/W D-Reg 15 0 Op-code Ad S-Reg 87 14 13 12 1 1 10 9 6 5 4 3 2 1 As T able 3 − 1 1 lists and describes the double operand instructions.
Instruction Set 3-19 RISC 16-Bit CPU 3.4.2 Single-Operand (Format II) Instructions Figure 3 − 10 illustrates the single-operand instruction format. Figure 3 − 10. Single Operand Instruction Format B/W D/S-Reg 15 0 Op-code 87 14 13 12 1 1 10 9 6 5 4 3 2 1 Ad T able 3 − 12 lists and describes the single operand instructions.
Instruction Set 3-20 RISC 16-Bit CPU 3.4.3 Jumps Figure 3 − 1 1 shows the conditional-jump instruction format. Figure 3 − 1 1. Jump Instruction Format C 10-Bit PC Offset 15 0 Op-code 87 14 13 12 1 1 10 9 6 5 4 3 2 1 T able 3 − 13 lists and describes the jump instructions.
Instruction Set 3-21 RISC 16−Bit CPU ADC[.W] Add carry to destination ADC.B Add carry to destination Syntax ADC dst or ADC.W dst ADC.B dst Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand.
Instruction Set 3-22 RISC 16 − Bit CPU ADD[.W] Add source to destination ADD.B Add source to destination Syntax ADD src,dst or ADD.W src,dst ADD.B src,dst Operation src + dst − > dst Description The source operand is added to the destination operand.
Instruction Set 3-23 RISC 16 − Bit CPU ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC src,dst or ADDC.W src,dst ADDC.B src,dst Operation src + dst + C − > dst Description Th e source operand and the carry bit (C) are added to the destination operand.
Instruction Set 3-24 RISC 16 − Bit CPU AND[.W] Source AND destination AND.B Source AND destination Syntax AND src,dst or AND.W src,dst AND.B src,dst Operation src .AND. dst − > dst Description The source operand and the destination operand are logically ANDed.
Instruction Set 3-25 RISC 16 − Bit CPU BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax BIC src,dst or BIC.W src,dst BIC.B src,dst Operation .NOT .src .AND. dst − > dst Description The inverted source operand and the destination operand are logically ANDed.
Instruction Set 3-26 RISC 16 − Bit CPU BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax BIS src,dst or BIS.W src,dst BIS.B src,dst Operation src .OR. dst − > dst Description The source operand and the destination operand are logically ORed.
Instruction Set 3-27 RISC 16 − Bit CPU BIT[.W] T est bits in destination BIT .B T est bits in destination Syntax BIT src,dst or BIT .W src,dst Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits.
Instruction Set 3-28 RISC 16 − Bit CPU * BR, BRANCH Branch to .......... destination Syntax BR dst Operation dst − > PC Emulation MOV dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used.
Instruction Set 3-29 RISC 16 − Bit CPU CALL Subroutine Syntax CALL dst Operation dst − > t mp dst is evaluated and stored SP − 2 − > SP PC − > @SP PC updated to TOS tmp − > P C dst saved to PC Description A subroutine call is made to an address anywhere in the 64K address space.
Instruction Set 3-30 RISC 16 − Bit CPU * CLR[.W] Clear destination * CLR.B Clear destination Syntax CLR dst or CLR.W dst CLR.B dst Operation 0 − > dst Emulation MOV #0,dst MOV .B #0,dst Description The destination operand is cleared. Status Bits Status bits are not affected.
Instruction Set 3-31 RISC 16 − Bit CPU * CLRC Clear carry bit Syntax CLRC Operation 0 − > C Emulation BIC #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-32 RISC 16 − Bit CPU * CLRN Clear negative bit Syntax CLRN Operation 0 → N or (.NOT .src .AND. dst − > dst) Emulation BIC #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand.
Instruction Set 3-33 RISC 16 − Bit CPU * CLRZ Clear zero bit Syntax CLRZ Operation 0 → Z or (.NOT .src .AND. dst − > dst) Emulation BIC #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination.
Instruction Set 3-34 RISC 16 − Bit CPU CMP[.W] Compare source and destination CMP .B Compare source and destination Syntax CMP src,dst or CMP .W src,dst CMP .B src,dst Operation dst + .NOT .src + 1 or (dst − src) Description The source operand is subtracted from the destination operand.
Instruction Set 3-35 RISC 16 − Bit CPU * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC dst or DADC.W src,dst DADC.B dst Operation dst + C − > dst (decimally) Emulation DADD #0,dst DADD.B #0,dst Description The carry bit (C) is added decimally to the destination.
Instruction Set 3-36 RISC 16 − Bit CPU DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD src,dst or DADD.
Instruction Set 3-37 RISC 16 − Bit CPU * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC dst or DEC.W dst DEC.B dst Operation dst − 1 − > dst Emulation SUB #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one.
Instruction Set 3-38 RISC 16 − Bit CPU * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD dst or DECD.W dst DECD.B dst Operation dst − 2 − > dst Emulation SUB #2,dst Emulation SUB.B #2,dst Description Th e destination operand is decremented by two.
Instruction Set 3-39 RISC 16 − Bit CPU * DINT Disable (general) interrupts Syntax DINT Operation 0 → GIE or (0FFF7h .AND. SR → SR / .NOT .src .AND. dst − > dst) Emulation BIC #8,SR Description All interrupts are disabled. Th e constant 08h is inverted and logically ANDed with the status register (SR).
Instruction Set 3-40 RISC 16 − Bit CPU * EINT Enable (general) interrupts Syntax EINT Operation 1 → GIE or (0008h .OR. SR − > SR / .src .OR. dst − > dst) Emulation BIS #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed.
Instruction Set 3-41 RISC 16 − Bit CPU * INC[.W ] Increment destination * INC.B Increment destination Syntax INC dst or INC.W dst INC.B dst Operation dst + 1 − > dst Emulation ADD #1,dst Description Th e destination operand is incremented by one.
Instruction Set 3-42 RISC 16 − Bit CPU * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD dst or INCD.W dst INCD.B dst Operation dst + 2 − > dst Emulation ADD #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two.
Instruction Set 3-43 RISC 16 − Bit CPU * INV[.W] Invert destination * INV .B Invert destination Syntax INV dst INV .B dst Operation .NOT .dst − > dst Emulation XOR #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted.
Instruction Set 3-44 RISC 16 − Bit CPU JC Jump if carry set JHS Jump if higher or same Syntax JC label JHS label Operation If C = 1: PC + 2 × offset − > PC If C = 0: execute following instruction Description The status register carry bit (C) is tested.
Instruction Set 3-45 RISC 16 − Bit CPU JEQ, JZ Jump if equal, jump if zero Syntax JEQ label, JZ label Operation If Z = 1: PC + 2 × offset − > PC If Z = 0: execute following instruction Description The status register zero bit (Z) is tested.
Instruction Set 3-46 RISC 16 − Bit CPU JGE Jump if greater or equal Syntax JGE label Operation If (N .XOR. V) = 0 then jump to label: PC + 2 × offset − > PC If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested.
Instruction Set 3-47 RISC 16 − Bit CPU JL Jump if less Syntax JL label Operation If (N .XOR. V) = 1 then jump to label: PC + 2 × offset − > PC If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested.
Instruction Set 3-48 RISC 16 − Bit CPU JMP Jump unconditionally Syntax JMP label Operation PC + 2 × offset − > PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter . Status Bits Status bits are not affected.
Instruction Set 3-49 RISC 16 − Bit CPU JN Jump if negative Syntax JN label Operation if N = 1: PC + 2 × offset − > PC if N = 0: execute following instruction Description Th e negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter .
Instruction Set 3-50 RISC 16 − Bit CPU JNC Jump if carry not set JLO Jump if lower Syntax JNC label JLO label Operation if C = 0: PC + 2 × offset − > PC if C = 1: execute following instruction Description The status register carry bit (C) is tested.
Instruction Set 3-51 RISC 16 − Bit CPU JNE Jump if not equal JNZ Jump if not zero Syntax JNE label JNZ label Operation If Z = 0: PC + 2 × offset − > PC If Z = 1: execute following instruction Description The status register zero bit (Z) is tested.
Instruction Set 3-52 RISC 16 − Bit CPU MOV[.W] Move source to destination MOV .B Move source to destination Syntax MOV src,dst or MOV .W src,dst MOV .B src,dst Operation src − > dst Description The source operand is moved to the destination. The source operand is not affected.
Instruction Set 3-53 RISC 16 − Bit CPU * NOP No operation Syntax NOP Operation None Emulation MOV #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times.
Instruction Set 3-54 RISC 16 − Bit CPU * POP[.W] Pop word from stack to destination * POP .B Pop byte from stack to destination Syntax POP dst POP .B dst Operation @SP − > temp SP + 2 − > SP temp − > dst Emulation MOV @SP+,dst or MOV .
Instruction Set 3-55 RISC 16 − Bit CPU PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH src or PUSH.W src PUSH.B src Operation SP − 2 → SP src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS).
Instruction Set 3-56 RISC 16 − Bit CPU * RET Return from subroutine Syntax RET Operation @SP → PC SP + 2 → SP Emulation MOV @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to th e program counter . The program continues at the code address following the subroutine call.
Instruction Set 3-57 RISC 16 − Bit CPU RETI Return from interrupt Syntax RETI Operation TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents.
Instruction Set 3-58 RISC 16 − Bit CPU * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA dst or RLA.W dst RLA.B dst Operation C < − MSB < − MSB − 1 .... LSB+1 < − LSB < − 0 Emulation ADD dst,dst ADD.
Instruction Set 3-59 RISC 16 − Bit CPU * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC dst or RLC.W dst RLC.B dst Operation C < − MSB < − MSB − 1 .... LSB+1 < − LSB < − C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3 − 15.
Instruction Set 3-60 RISC 16 − Bit CPU RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA dst or RRA.W dst RRA.B dst Operation MSB − > MSB, MSB − > MSB − 1, ... LSB+1 − > LSB, LSB − > C Description The destination operand is shifted right one position as shown in Figure 3 − 16.
Instruction Set 3-61 RISC 16 − Bit CPU RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC dst or RRC.W dst RRC dst Operation C − > MSB − > MSB − 1 .... LSB+1 − > LSB − > C Description The destination operand is shifted right one position as shown in Figure 3 − 17.
Instruction Set 3-62 RISC 16 − Bit CPU * SBC[.W] Subtract source and borrow/.NOT . carry from destination * SBC.B Subtract source and borrow/.NOT . carry from destination Syntax SBC dst or SBC.W dst SBC.B dst Operation dst + 0FFFFh + C − > dst dst + 0FFh + C − > dst Emulation SUBC #0,dst SUBC.
Instruction Set 3-63 RISC 16 − Bit CPU * SETC Set carry bit Syntax SETC Operation 1 − > C Emulation BIS #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-64 RISC 16 − Bit CPU * SETN Set negative bit Syntax SETN Operation 1 − > N Emulation BIS #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-65 RISC 16 − Bit CPU * SETZ Set zero bit Syntax SETZ Operation 1 − > Z Emulation BIS #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V : Not affected Mode Bits OSCOFF , CPUOFF , and GIE are not affected.
Instruction Set 3-66 RISC 16 − Bit CPU SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax SUB src,dst or SUB.W src,dst SUB.
Instruction Set 3-67 RISC 16 − Bit CPU SUBC[.W]SBB[.W] Subtract source and borrow/.NOT . carry from destination SUBC.B,SBB.B Subtract source and borrow/.NOT . carry from destination Syntax SUBC src,dst or SUBC.W src,dst or SBB src,dst or SBB.W src,dst SUBC.
Instruction Set 3-68 RISC 16 − Bit CPU SWPB Swap bytes Syntax SWPB dst Operation Bits 15 to 8 < − > bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3 − 18. Status Bits Status bits are not affected.
Instruction Set 3-69 RISC 16 − Bit CPU SXT Extend Sign Syntax SXT dst Operation Bit 7 − > Bit 8 ......... Bit 15 Description Th e sign of the low byte is extended into the high byte as shown in Figure 3 − 19.
Instruction Set 3-70 RISC 16 − Bit CPU * TST[.W] T est destination * TST .B T est destination Syntax TST dst or TST .W dst TST .B dst Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMP #0,dst CMP .B #0,dst Description Th e destination operand is compared with zero.
Instruction Set 3-71 RISC 16 − Bit CPU XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax XOR src,dst or XOR.W src,dst XOR.B src,dst Operation src .XOR. dst − > dst Description Th e source and destination operands are exclusive ORed.
Instruction Set 3-72 RISC 16 − Bit CPU 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK.
Instruction Set 3-73 RISC 16 − Bit CPU Format-I (Double Operand) Instruction Cycles and Lengths T able 3 − 16 lists the length and CPU cycles for all addressing modes of format-I instructions. T able 3 − 16. Format I Instruction Cycles and Lengths Addressing Mode No.
Instruction Set 3-74 RISC 16 − Bit CPU 3.4.5 Instruction Set Description The instruction map is shown in Figure 3 − 20 and the complete instruction set is summarized in T able 3 − 17.
Instruction Set 3-75 RISC 16 − Bit CPU T able 3 − 17. MSP430 Instruction Set Mnemonic Description V N Z C ADC(.B) † dst Add C to destination dst + C → dst * * * * ADD(.B) src,dst Add source to destination src + dst → d s t **** ADDC(.B) src,dst Add source and C to destination src + dst + C → d s t **** AND(.
4-1 FLL+ Clock Module The FLL+ clock module provides the clocks for MSP430x4xx devices. This chapter discusses the FLL+ clock module. The FLL+ clock module is implemented in all MSP430x4xx devices. T opic Page 4.
4-2 FLL+ Clock Module 4.1 FLL+ Clock Module Introduction Th e frequency-locked loop (FLL+) clock module supports low system cost and ultralow-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption.
4-3 FLL+ Clock Module Figure 4−1. MSP430x44x and MSP430x43x Frequency-Locked Loop 10 − bit Frequency Integrator DCO + Modulator DC Generator OSCOFF FNx SCG1 off SCG0 Enable PUC Reset ACLK MCLK XTS.
4-4 FLL+ Clock Module Figure 4 − 2. MSP430x42x and MSP430x41x Frequency-Locked Loop 10 − bit Frequency Integrator DCO + Modulator DC Generator OSCOFF FNx SCG1 off SCG0 Enable PUC Reset ACLK XTS_FL.
FLL+ Clock Module Operation 4-5 FLL+ Clock Module 4.2 FLL+ Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency . When a 32,768-Hz crystal is used for ACLK, MCLK and SMCLK will stabilize to 1.048576 MHz.
FLL+ Clock Module Operation 4-6 FLL+ Clock Module 4.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connects to XIN and XOUT without any external components.
FLL+ Clock Module Operation 4-7 FLL+ Clock Module 4.2.4 Digitally-Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N, the lowest 7 bits of the SCFQCTL register .
FLL+ Clock Module Operation 4-8 FLL+ Clock Module 4.2.6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy , reducing electromagnetic interference (EMI) . The modulator mixes the two adjacent frequencies across 32 DCOCLK clock cycles.
FLL Operation from Low-Power Modes- 4-9 FLL+ Clock Module 4.2.7 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCG0 = 1. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized.
Buffered Clock Output 4-10 FLL+ Clock Module 4.2.10 FLL+ Fail-Safe Operation Th e FLL+ module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 4 − 4.
FLL+ Clock Module Registers 4-1 1 FLL+ Clock Module 4.3 FLL+ Clock Module Registers The FLL+ registers are listed in T able 4 − 2. T able 4 − 2. FLL+ Registers Register Short Form Register T ype A.
FLL+ Clock Module Registers 4-12 FLL+ Clock Module SCFQCTL, System Clock Control Register 76543 210 SCFQ_M N rw − 0 rw − 0 rw − 0 rw − 1 rw − 1 rw − 1 rw − 1 rw − 1 SCFQ_M Bit 7 Modulation. This enables or disables modulation 0 Modulation enabled 1 Modulation disabled N Bits 6-0 Multiplier .
FLL+ Clock Module Registers 4-13 FLL+ Clock Module SCFI1, System Clock Frequency Integrator Register 1 76543 210 DCOx MODx (MSBs) rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 DCOx Bits 7-3 These bits select the DCO tap and are modified automatically by the FLL+.
FLL+ Clock Module Registers 4-14 FLL+ Clock Module FLL_CTL0, FLL+ Control Register 0 76543 210 DCOPLUS XTS_FLL XCAPxPF XT2OF † XT1OF LFOF DCOF rw − 0 rw − 0 rw − 0 rw − 0 r0 r0 r − (1) r − 1 † Not present in MSP430x41x, MSP430x42x devices DCOPLUS Bit 7 DCO output pre-divider .
FLL+ Clock Module Registers 4-15 FLL+ Clock Module FLL_CTL1, FLL+ Control Register 1 76543 210 Unused SMCLK OFF † XT2OFF † SELMx † SELS † FLL_DIVx r0 r0 rw − (1) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) † Not present in MSP430x41x, MSP430x42x devices.
FLL+ Clock Module Registers 4-16 FLL+ Clock Module IE1, Interrupt Enable Register 1 76543 210 OFIE rw − 0 Bits 7-2 These bits may be used by other modules. See device-specific datasheet. OFIE Bit 1 Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.
5-1 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller . T opic Page 5.1 Flash Memory Introduction 5-2 . . . . . . . . . . . . . . . . . .
Flash Memory Introduction 5-2 Flash Memory Controller 5.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations.
Flash Memory Segmentation 5-3 Flash Memory Controller 5.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory , but the segment is the smallest size of flash memory that can be erased.
Flash Memory Operation 5-4 Flash Memory Controller 5.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are of f, and the memory operates identically to ROM.
Flash Memory Operation 5-5 Flash Memory Controller 5.3.2 Erasing Flash Memory Th e erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment.
Flash Memory Operation 5-6 Flash Memory Controller Initiating an Erase from Within Flash Memory An y erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory , all timing is controlled by the flash controller , and the CPU is held while the erase cycle completes.
Flash Memory Operation 5-7 Flash Memory Controller Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again.
Flash Memory Operation 5-8 Flash Memory Controller 5.3.3 Writing Flash Memory The write modes, selected by the WR T and BLKWRT bits, are listed in T able 5 − 1. Interrupts are automatically disabled during a flash write and re-enabled after the write.
Flash Memory Operation 5-9 Flash Memory Controller In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 32 of the 35 f FTG cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates.
Flash Memory Operation 5-10 Flash Memory Controller Initiating a Byte/Word W rite from RAM The flow to initiate a byte/word write from RAM is shown in Figure 5 − 9.
Flash Memory Operation 5-1 1 Flash Memory Controller Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block.
Flash Memory Operation 5-12 Flash Memory Controller Block W rite Flow and Example A block write flow is shown in Figure 5 − 8 and the following example.
Flash Memory Operation 5-13 Flash Memory Controller ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased.
Flash Memory Operation 5-14 Flash Memory Controller 5.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
Flash Memory Operation 5-15 Flash Memory Controller 5.3.5 Stopping a W rite or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller .
Flash Memory Operation 5-16 Flash Memory Controller Programming Flash Memory via JT AG MSP430 devices can be programmed via the JT AG port. The JT AG interface requires four signals (5 signals on 20- and 28-pin devices), ground and optionally V CC and RST /NMI.
Flash Memory Registers 5-17 Flash Memory Controller 5.4 Flash Memory Registers The flash memory registers are listed in T able 5 − 4. T able 5 − 4.
Flash Memory Registers 5-18 Flash Memory Controller FCTL1, Flash Memory Control Register 15 14 13 12 1 1 10 9 8 FRKEY , Read as 096h FWKEY , Must be written as 0A5h 76543 210 BLKWRT WRT Reserved Reserved Reserved MERAS ERASE Reserved rw − 0 rw − 0 r0 r0 r0 rw − 0 rw − 0 r0 FRKEY/ FWKEY Bits 15-8 FCTLx password.
Flash Memory Registers 5-19 Flash Memory Controller FCTL2, Flash Memory Control Register 15 14 13 12 1 1 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 76543 210 FSSELx FNx rw − 0 rw − 1 rw-0 rw-0 rw-0 rw − 0 rw-1 rw − 0 FWKEYx Bits 15-8 FCTLx password.
Flash Memory Registers 5-20 Flash Memory Controller FCTL3, Flash Memory Control Register FCTL3 15 14 13 12 1 1 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 76543 210 Reserved Reserved EMEX LOCK W AIT ACCVIFG KEYV BUSY r0 r0 rw-0 rw-1 r-1 rw − 0 rw-(0) r(w) − 0 FWKEYx Bits 15-8 FCTLx password.
Flash Memory Registers 5-21 Flash Memory Controller IE1, Interrupt Enable Register 1 76543 210 ACCVIE rw − 0 Bits 7-6, 4-0 These bits may be used by other modules. See device-specific datasheet. ACCVIE Bit 5 Flash memory access violation interrupt enable.
6-1 Supply V oltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented in all MSP430x4x devices. T opic Page 6.1 SVS Introduction 6−2 . . . . . .
SVS Introduction 6-2 Supply V oltage Supervisor 6.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the A V CC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
SVS Introduction 6-3 Supply V oltage Supervisor Figure 6−1. SVS Block Diagram + − 1.25V Brownout Reset VCC Set SVSFG t Reset ~ 50us Reset SVSCTL Bits 0001 0010 001 1 1111 1 101 1 100 G D S SVSOUT .
SVS Operation 6-4 Supply V oltage Supervisor 6.2 SVS Operation The SVS detects if the A V CC voltage drops below a selectable level. It can be configured t o provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption.
SVS Operation 6-5 Supply V oltage Supervisor 6.2.3 Changing the VLDx Bits When the VLDx bits are changed, two settling delays are implemented to allows the SVS circuitry to settle. During each delay , the SVS will not set SVSFG. The delays, t d(SVSon) and t settle, are shown in Figure 6 − 2.
SVS Operation 6-6 Supply V oltage Supervisor 6.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when A V CC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 6 − 3 .
SVS Registers 6-7 Supply V oltage Supervisor 6.3 SVS Registers The SVS registers are listed in T able 6 − 1. T able 6 − 1. SVS Registers Register Short Form Register T ype Address Initial State SV.
7-1 Hardware Multiplier Hardware Multiplier This chapter describes the hardware multiplier . The hardware multiplier is implemented in MSP430x44x devices. T opic Page 7.1 Hardware Multiplier Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . .
Hardware Multiplier Introduction 7-2 Hardware Multiplier 7.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Hardware Multiplier Operation 7-3 Hardware Multiplier 7.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply , signed multiply , unsigned multiply accumulate, and signed multiply accumulate operations. The type o f operation is selected by the address the first operand is written to.
Hardware Multiplier Operation 7-4 Hardware Multiplier 7.2.2 Result Registers Th e result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation an d are listed in T able 7 − 2.
Hardware Multiplier Operation 7-5 Hardware Multiplier 7.2.3 Software Examples Examples for all multiplier modes follow . All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file.
Hardware Multiplier Operation 7-6 Hardware Multiplier 7.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one inst.
Hardware Multiplier Registers 7-7 Hardware Multiplier 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in T able 7 − 4.
8-1 The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. The DMA controller is implemented in MSP430FG43x and implements only one DMA channel.
8-2 8.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another , without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM.
8-3 Figure 8−1. DMA Controller Block Diagram DMA Priority And Control ENNMI DT DMA Channel 2 DMASRSBYTE DMA2SZ DMA2DA DMA2SA DMADSTBYTE DMASRCINCRx DMADSTINCRx 2 2 3 DMADTx DMAEN DT DMA Channel 1 DM.
8-4 8.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 8.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable.
8-5 8.2.2 DMA T ransfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in T able 8 − 1. Each channel is individually configurable for its transfer mode.
8-6 Single T ransfer In single transfer mode, each byte/word transfer requires a separate trigger . The single transfer state diagram is shown in Figure 8 − 3.
8-7 Figure 8 − 3. DMA Single T ransfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2.
8-8 Block T ransfers In block transfer mode, a transfer of a complete block of data occurs after one trigger . When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered.
8-9 Figure 8 − 4. DMA Block T ransfer State Diagram Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMAABORT=0 DMAABORT = 1 2 .
8-10 Burst-Block T ransfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity . After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
8-1 1 Figure 8 − 5. DMA Burst-Block T ransfer State Diagram 2 x MCLK Reset Wait for Trigger Idle Hold CPU, Transfer one word/byte Burst State (release CPU for 2xMCLK) [+Trigger AND DMALEVEL = 0 ] OR.
8-12 8.2.3 Initiating DMA T ransfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in T able 8 − 2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur .
8-13 T able 8 − 2. DMA T rigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the T ACCR2 CCIFG flag is set. The T ACCR2 CCIFG flag is automatically reset when the transfer starts.
8-14 8.2.4 Stopping DMA T ransfers There are two ways to stop DMA transfers in progress: - A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. - A burst-block transfer may be stopped by clearing the DMAEN bit.
8-15 8.2.6 DMA T ransfer Cycle T ime The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer . Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer .
8-16 8.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer . NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers.
8-17 8.2.9 Using the I 2 C Module with the DMA Controller The I 2 C module provides two trigger sources for the DMA controller . The I 2 C module can trigger a transfer when new I 2 C data is received and the when the transmit data is needed. The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the I 2 C module.
8-18 8.3 DMA Registers The DMA registers are listed in T able 8 − 4. T able 8 − 4. DMA Registers Register Short Form Register T ype Address Initial State DMA control 0 DMACTL0 Read/write 0122h Res.
8-19 DMACTL0, DMA Control Register 0 15 14 13 12 1 1 10 9 8 Reserved DMA2TSELx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 210 DMA1TSELx DMA0TSELx rw .
8-20 DMACTL1, DMA Control Register 1 15 14 13 12 1 1 10 9 8 0 0000000 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 00000 DMA ONFETCH ROUND ROBIN ENNMI r0 r0 r0 r0 r0 rw − (0) rw − (0) rw − (0) Reserved Bits 15 − 3 Reserved.
8-21 DMAxCTL, DMA Channel x Control Register 15 14 13 12 1 1 10 9 8 Reserved DMADTx DMADSTINCRx DMASRCINCRx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 7654.
8-22 DMA SRCBYTE Bit 6 DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte DMA LEVEL Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive triggers.
8-23 DMAxDA, DMA Destination Address Register 15 14 13 12 1 1 10 9 8 DMAxDAx rw rw rw rw rw rw rw rw 76543 210 DMAxDAx rw rw rw rw rw rw rw rw DMAxDAx Bits 15 − 0 DMA destination address. The destination address register points to the destination address for single transfers or the first address for block transfers.
9-1 Digital I/O Digital I/O This chapter describes the operation of the digital I/O ports. Ports P1-P6 are implemented in all MSP430x4xx devices. T opic Page 9.1 Digital I/O Introduction 9-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital I/O Introduction 9-2 Digital I/O 9.1 Digital I/O Introduction MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to.
Digital I/O Operation 9-3 Digital I/O 9.2 Digital I/O Operation Th e digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections.
Digital I/O Operation 9-4 Digital I/O 9.2.4 Function Select Registers PxSEL Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function − I/O port or peripheral module function.
Digital I/O Operation 9-5 Digital I/O 9.2.5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability , configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector , and all P2 pins source a different single interrupt vector .
Digital I/O Operation 9-6 Digital I/O Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin.
Digital I/O Registers 9-7 Digital I/O 9.3 Digital I/O Registers Seven registers are used to configure P1 and P2. Four registers are used to configure ports P3 - P6.
10-1 Watchdog Timer , Watchdog Timer+ The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer . This chapter describes the watchdog timer .
Watchdog Timer Introduction 10-2 Watchdog Timer , Watchdog Timer+ 10.1 W atchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated.
Watchdog Timer Introduction 10-3 Watchdog Timer , Watchdog Timer+ Figure 10−1. Watchdog T imer Block Diagram WDTQn Y 1 2 3 4 Q6 Q9 Q13 Q15 16 − bit Counter CLK A B 1 1 AE N PUC SMCLK ACLK Clear Pa.
Watchdog Timer Operation 10-4 Watchdog Timer , Watchdog Timer+ 10.2 W atchdog Timer Operation Th e WDT module can be configured as either a watchdog or interval timer with the WDTCTL register . The WDTCTL register also contains control bits to configure the RST /NMI pin.
Watchdog Timer Operation 10-5 Watchdog Timer , Watchdog Timer+ 10.2.4 Watchdog T imer Interrupts The WDT uses two bits in the SFRs for interrupt control. - The WDT interrupt flag, WDTIFG, located in IFG1.0 - The WDT interrupt enable, WDTIE, located in IE1.
Watchdog Timer Operation 10-6 Watchdog Timer , Watchdog Timer+ 10.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user ’ s application and the type of clocking used determine how the WDT should be configured.
Watchdog Timer Registers 10-7 Watchdog Timer , Watchdog Timer+ 10.3 W atchdog Timer Registers The watchdog timer module registers are listed in T able 10 − 1.
Watchdog Timer Registers 10-8 Watchdog Timer , Watchdog Timer+ WDTCTL, W atchdog Timer Register 15 14 13 12 1 1 10 9 8 Read as 069h WDTPW , must be written as 05Ah 76543 210 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw − 0 rw − 0 rw − 0 rw − 0 r0(w) rw − 0 rw − 0 rw − 0 WDTPW Bits 15-8 W atchdog timer password.
Watchdog Timer Registers 10-9 Watchdog Timer , Watchdog Timer+ IE1, Interrupt Enable Register 1 76543 210 NMIIE WDTIE rw − 0 rw − 0 Bits 7-5 These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt.
Watchdog Timer Registers 10-10 Watchdog Timer , Watchdog Timer+ IFG1, Interrupt Flag Register 1 76543 210 NMIIFG WDTIFG rw − (0) rw − (0) Bits 7-5 These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag.
1 1-1 Basic Timer1 The Basic Timer1 module is two independent, cascadable 8-bit timers. This chapter describes the Basic T imer1. Basic Timer1 is implemented in all MSP430x4xx devices. T opic Page 1 1.1 Basic Timer1 Introduction 1 1−2 .
Basic Timer1 Introduction 1 1-2 Basic Timer1 1 1.1 Basic Timer1 Introduction The Basic T imer1 supplies LCD timing and low frequency time intervals. The Basic T imer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function.
Basic Timer1 Introduction 1 1-3 Basic Timer1 Figure 1 1−1. Basic Timer1 Block Diagram BTCNT2 Set_BTIFG BTCNT1 EN1 CLK1 Q4 Q5 Q6 Q7 BTDIV BTHOLD ACLK EN2 CLK2 Q4 Q5 Q6 Q7 Q3 Q2 Q1 Q0 BTSSEL SMCLK BTI.
Basic Timer1 Introduction 1 1-4 Basic Timer1 1 1.2 Basic Timer1 Operation The Basic T imer1 module can be configured as two 8-bit timers or one 16-bit timer with the BTCTL register . The BTCTL register is an 8-bit, read/write register . Any read or write access must use byte instructions.
Basic Timer1 Introduction 1 1-5 Basic Timer1 1 1.2.4 Basic Timer1 Operation: Signal f LCD Th e LCD controller (but not the LCDA controller) uses the f LCD signal from the BTCNT1 t o generate the timing for common and segment lines. ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating f LCD .
Basic Timer1 Introduction 1 1-6 Basic Timer1 1 1.3 Basic Timer1 Registers The watchdog timer module registers are listed in T able 1 1 − 1. T able 1 1 − 1.
Basic Timer1 Introduction 1 1-7 Basic Timer1 BTCTL, Basic Timer1 Control Register 76543 210 BTSSEL BTHOLD BTDIV BTFRFQx BTIPx rw rw rw rw rw rw rw rw BTSSEL Bit 7 BTCNT2 clock select. This bit, together with the BTDIV bit, selects the clock source for BTCNT2.
Basic Timer1 Introduction 1 1-8 Basic Timer1 BTCNT1, Basic Timer1 Counter 1 76543 210 BTCNT1x rw rw rw rw rw rw rw rw BTCNT1x Bits 7 − 0 BTCNT1 register . The BTCNT1 register is the count of BTCNT1. BTCNT2, Basic Timer1 Counter 2 76543 210 BTCNT2x rw rw rw rw rw rw rw rw BTCNT2x Bits 7 − 0 BTCNT2 register .
Basic Timer1 Introduction 1 1-9 Basic Timer1 IE2, Interrupt Enable Register 2 76543 210 BTIE rw − 0 BTIE Bit 7 Basic T imer1 interrupt enable. This bit enables the BTIFG interrupt Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.
12-1 Timer_A T imer_A T imer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes T imer_A. T imer_A3 (three capture/compare registers) is implemented in all MSP430x4xx devices. Timer1_A5 (five capture/compare registers) is also implemented on MSP430x415, MSP430x417, and MSP430xW42x devices.
Timer_A Introduction 12-2 Timer_A 12.1 Timer_A Introduction T imer_A is a 1 6 - bit timer/counter with three or five capture/compare registers. T imer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities.
Timer_A Introduction 12-3 Timer_A Figure 12−1. Timer_A Block Diagram CCR4 Compararator 2 CCI 15 0 CCISx OUTMODx Capture Mode CMx Sync SCS COV logic Output Unit4 D Set Q EQU0 OUT OUT2 Signal Reset GN.
Timer_A Operation 12-4 Timer_A 12.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of T imer_A is discussed in the following sections.
Timer_A Operation 12-5 Timer_A 12.2.2 Starting the Timer The timer may be started, or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by writing 0 to T ACCR0.
Timer_A Operation 12-6 Timer_A Up Mode Th e up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register T ACCR0, which defines the period, as shown in Figure 12 − 2. The number of timer counts in the period is T ACCR0+1.
Timer_A Operation 12-7 Timer_A Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 12 − 4. The capture/compare register T ACCR0 works the same way as the other capture/compare registers.
Timer_A Operation 12-8 Timer_A Use of the Continuous Mode Th e continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the T ACCRx register in the interrupt service routine.
Timer_A Operation 12-9 Timer_A Up/Down Mode The up/down mode is used if the timer period must be dif ferent from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register T ACCR0 and back down to zero, as shown in Figure 12 − 7.
Timer_A Operation 12-10 Timer_A Changing the Period Register T ACCR0 When changing T ACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The new period takes affect after the counter counts down to zero.
Timer_A Operation 12-1 1 Timer_A 12.2.4 Capture/Compare Blocks Three or five identical capture/compare blocks, T ACCRx, are present in T imer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode Th e capture mode is selected when CAP = 1.
Timer_A Operation 12-12 Timer_A Figure 12 − 1 1. Capture Cycle Second Capture T aken COV = 1 Capture T aken No Capture T aken Read T aken Capture Clear Bit COV in Register T ACCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initiated by software.
Timer_A Operation 12-13 Timer_A 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals.
Timer_A Operation 12-14 Timer_A Output Example — Timer in Up Mode The OUTx signal is changed when the timer counts up to the T ACCRx value, and rolls from T ACCR0 to zero, depending on the output mode. An example is shown in Figure 12 − 12 using T ACCR0 and T ACCR1.
Timer_A Operation 12-15 Timer_A Output Example — Timer in Continuous Mode The OUTx signal is changed when the timer reaches the T ACCRx and T ACCR0 values, depending on the output mode. An example is shown in Figure 12 − 13 using T ACCR0 and T ACCR1.
Timer_A Operation 12-16 Timer_A Output Example — Timer in Up/Down Mode The OUTx signal changes when the timer equals T ACCRx in either count direction and when the timer equals T ACCR0, depending on the output mode. An example is shown in Figure 12 − 14 using T ACCR0 and T ACCR2.
Timer_A Operation 12-17 Timer_A 12.2.6 Timer_A Interrupts T wo interrupt vectors are associated with the 16-bit Timer_A module: - T ACCR0 interrupt vector for T ACCR0 CCIFG - T AIV interrupt vector for all other CCIFG flags and T AIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated T ACCRx register .
Timer_A Operation 12-18 Timer_A T AIV Software Example Th e following software example shows the recommended use of T AIV and the handling overhead. The T AIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Timer_A Registers 12-19 Timer_A 12.3 Timer_A Registers The T imer_A registers are listed in T able 12 − 3 and T able 12 − 4. T able 12 − 3. Timer_A3 Registers Register Short Form Register T ype .
Timer_A Registers 12-20 Timer_A T ACTL, T imer_A Control Register 15 14 13 12 1 1 10 9 8 Unused T ASSELx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 2.
Timer_A Registers 12-21 Timer_A T AR, Timer_A Register 15 14 13 12 1 1 10 9 8 T ARx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 210 T ARx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) T ARx Bits 15-0 T imer_A register .
Timer_A Registers 12-22 Timer_A T ACCTLx, Capture/Compare Control Register 15 14 13 12 1 1 10 9 8 CMx CCISx SCS SCCI Unused CAP rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) r − (0) r − (.
Timer_A Registers 12-23 Timer_A CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
13-1 Timer_B T imer_B T imer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes T imer_B. T imer_B3 (three capture/compare registers) is implemented in MSP430x43x devices. T imer_B7 (seven capture/compare registers) is implemented in MSP430x44x.
Timer_B Introduction 13-2 Timer_B 13.1 Timer_B Introduction T imer_B is a 16-bit timer/counter with three or seven capture/compare registers. T imer_B can support multiple capture/compares, PWM outputs, a n d interval timing. T imer_B also has extensive interrupt capabilities.
Timer_B Introduction 13-3 Timer_B Figure 13−1. Timer_B Block Diagram CCR6 Compararator 6 CCI 15 0 OUTMODx Capture Mode CMx Sync COV logic Output Unit6 D Set Q EQU0 OUT OUT6 Signal Reset POR EQU6 Div.
Timer_B Operation 13-4 Timer_B 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of T imer_B is discussed in the following sections.
Timer_B Operation 13-5 Timer_B 13.2.2 Starting the Timer The timer may be started or restarted in the following ways: - The timer counts when MCx > 0 and the clock source is active. - When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0.
Timer_B Operation 13-6 Timer_B Up Mode T h e up mode is used if the timer period must be dif ferent from TBR (max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 13 − 2. The number of timer counts in the period is TBCL0+1.
Timer_B Operation 13-7 Timer_B Continuous Mode In continuous mode the timer repeatedly counts up to TBR (max) and restarts from zero as shown in Figure 13 − 4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 13 − 4.
Timer_B Operation 13-8 Timer_B Use of the Continuous Mode Th e continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
Timer_B Operation 13-9 Timer_B Up/Down Mode Th e up/down mode is used if the timer period must be different from TBR (max) counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 13 − 7.
Timer_B Operation 13-10 Timer_B Changing the V alue of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load mode is immediate , the timer continues its descent until it reaches zero.
Timer_B Operation 13-1 1 Timer_B 13.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in T imer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode Th e capture mode is selected when CAP = 1.
Timer_B Operation 13-12 Timer_B Figure 13 − 1 1. Capture Cycle Second Capture T aken COV = 1 Capture T aken No Capture T aken Read T aken Capture Clear Bit COV in Register TBCCTLx Idle Idle Capture Capture Read and No Capture Capture Capture Read Capture Capture Initiated by Software Captures can be initiated by software.
Timer_B Operation 13-13 Timer_B Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buf fered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates.
Timer_B Operation 13-14 Timer_B 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals.
Timer_B Operation 13-15 Timer_B Output Example—Timer in Up Mode Th e OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 13 − 12 using TBCL0 and TBCL1.
Timer_B Operation 13-16 Timer_B Output Example — Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 13 − 13 using TBCL0 and TBCL1. Figure 13 − 13.
Timer_B Operation 13-17 Timer_B Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 13 − 14 using TBCL0 and TBCL3.
Timer_B Operation 13-18 Timer_B 13.2.6 Timer_B Interrupts T wo interrupt vectors are associated with the 16-bit Timer_B module: - TBCCR0 interrupt vector for TBCCR0 CCIFG - TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register .
Timer_B Operation 13-19 Timer_B TBIV , Interrupt Handler Examples Th e following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction.
Timer_B Registers 13-20 Timer_B 13.3 Timer_B Registers The T imer_B registers are listed in T able 13 − 5. T able 13 − 5. Timer_B Registers Register Short Form Register T ype Address Initial State.
Timer_B Registers 13-21 Timer_B Timer_B Control Register TBCTL 15 14 13 12 1 1 10 9 8 Unused TBCLGRPx CNTLx Unused TBSSELx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) .
Timer_B Registers 13-22 Timer_B Unused Bit 3 Unused TBCLR Bit 2 T imer_B clear . Setting this bit resets TBR, the TBCLK divider , and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 T imer_B interrupt enable.
Timer_B Registers 13-23 Timer_B TBCCTLx, Capture/Compare Control Register 15 14 13 12 1 1 10 9 8 CMx CCISx SCS CLLDx CAP rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) r − (0) rw .
Timer_B Registers 13-24 Timer_B CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
Timer_B Registers 13-25 Timer_B TBIV , T imer_B Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0000000 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 0 TBIVx 0 r0 r0 r0 r0 r − (0) r − (0) r − (0) .
14-1 USART Peripheral Interface, UAR T Mode The universal synchronous/asynchronous receive/transmit (USAR T) peripheral interface supports two serial modes with one hardware module.
USART Introduction: UAR T Mode 14-2 USART Peripheral Interface, UAR T Mode 14.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UAR T mode is selected when the SYNC bit is cleared.
USART Introduction: UAR T Mode 14-3 USART Peripheral Interface, UAR T Mode Figure 14−1. USAR T Block Diagram: UART Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transm.
USART Operation: UAR T Mode 14-4 USART Peripheral Interface, UAR T Mode 14.2 USART Operation: UART Mode In UAR T mode, the USART transmits and receives characters at a bit rate asynchronous to another device. T iming for each character is based on the selected baud rate of the USART .
USART Operation: UAR T Mode 14-5 USART Peripheral Interface, UAR T Mode 14.2.3 Asynchronous Communication Formats When two devices communicate asynchronously , the idle-line format is used for the protocol. When three or more devices communicate, the USAR T supports the idle-line and address-bit multiprocessor communication formats.
USART Operation: UAR T Mode 14-6 USART Peripheral Interface, UAR T Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF , and interrupts are not generated.
USART Operation: UAR T Mode 14-7 USART Peripheral Interface, UAR T Mode Address - Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 14 − 4.
USART Operation: UAR T Mode 14-8 USART Peripheral Interface, UAR T Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored.
USART Operation: UAR T Mode 14-9 USART Peripheral Interface, UAR T Mode 14.2.4 USART Receive Enable Th e receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 14 − 5.
USART Operation: UAR T Mode 14-10 USART Peripheral Interface, UAR T Mode 14.2.5 USART T ransmit Enable When UTXEx is set, the UAR T transmitter is enabled. T ransmission is initiated by writing data to UxTXBUF . The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty , and transmission begins.
USART Operation: UAR T Mode 14-1 1 USART Peripheral Interface, UAR T Mode 14.2.6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 14 − 7.
USART Operation: UAR T Mode 14-12 USART Peripheral Interface, UAR T Mode Baud Rate Bit Timing Th e first stage of the baud rate generator is the 16-bit counter and comparator . At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1.
USART Operation: UAR T Mode 14-13 USART Peripheral Interface, UART Mode T ransmit Bit Timing The timing for each character is the sum of the individual bit timings.
USART Operation: UAR T Mode 14-14 USART Peripheral Interface, UAR T Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error . The second is the error between a start edge occurring and the start edge being accepted by the USART .
USART Operation: UAR T Mode 14-15 USART Peripheral Interface, UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.
USART Operation: UAR T Mode 14-16 USART Peripheral Interface, UAR T Mode T ypical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in T able 14 − 2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK.
USART Operation: UAR T Mode 14-17 USART Peripheral Interface, UART Mode 14.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART T ransmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character .
USART Operation: UAR T Mode 14-18 USART Peripheral Interface, UAR T Mode USART Receive Interrupt Operation Th e URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF . An interrupt request is generated if URXIEx and GIE are also set.
USART Operation: UAR T Mode 14-19 USART Peripheral Interface, UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation.
USART Operation: UAR T Mode 14-20 USART Peripheral Interface, UAR T Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started.
USART Registers: UAR T Mode 14-21 USART Peripheral Interface, UART Mode 14.3 USART Registers: UART Mode T able 14 − 3 lists the registers for all devices implementing a USART module. T able 14 − 4 applies only to devices with a second USART module, USAR T1.
USART Registers: UAR T Mode 14-22 USART Peripheral Interface, UAR T Mode UxCTL, USART Control Register 76543 210 PENA PEV SPB CHAR LISTEN SYNC MM SWRST rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 1 PENA Bit 7 Parity enable 0 Parity disabled.
USART Registers: UAR T Mode 14-23 USART Peripheral Interface, UART Mode UxTCTL, USART T ransmit Control Register 76543 210 Unused CKPL SSELx URXSE TXW AKE Unused TXEPT rw − 0 rw − 0 rw − 0 rw .
USART Registers: UAR T Mode 14-24 USART Peripheral Interface, UAR T Mode UxRCTL, USART Receive Control Register 76543 210 FE PE OE BRK URXEIE URXWIE RXW AKE RXERR rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag.
USART Registers: UAR T Mode 14-25 USART Peripheral Interface, UART Mode UxBR0, USART Baud Rate Control Register 0 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rw rw rw rw rw rw rw rw UxBR1, USART Baud Ra.
USART Registers: UAR T Mode 14-26 USART Peripheral Interface, UAR T Mode UxRXBUF , USART Receive Buffer Register 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rrrrrrrr UxRXBUFx Bits 7 − 0 The receive-data buffer is user accessible and contains the last received character from the receive shift register .
USART Registers: UAR T Mode 14-27 USART Peripheral Interface, UART Mode ME1, Module Enable Register 1 76543 210 UTXE0 URXE0 rw − 0 rw − 0 UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0. 0 Module not enabled 1 Module enabled URXE0 Bit 6 USAR T0 receive enable.
USART Registers: UAR T Mode 14-28 USART Peripheral Interface, UAR T Mode IE1, Interrupt Enable Register 1 76543 210 UTXIE0 URXIE0 rw − 0 rw − 0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 Bit 6 USAR T0 receive interrupt enable.
USART Registers: UAR T Mode 14-29 USART Peripheral Interface, UART Mode IFG1, Interrupt Flag Register 1 76543 210 UTXIFG0 URXIFG0 rw − 1 rw − 0 UTXIFG0 † Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty . 0 No interrupt pending 1 Interrupt pending URXIFG0 † Bit 6 USAR T0 receive interrupt flag.
15-1 USART Peripheral Interface, SPI Mode USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USAR T) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode.
USART Introduction: SPI Mode 15-2 USART Peripheral Interface, SPI Mode 15.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared.
USART Introduction: SPI Mode 15-3 USART Peripheral Interface, SPI Mode Figure 15−1. USAR T Block Diagram: SPI Mode Receiver Shift Register Transmit Shift Register Receiver Buffer UxRXBUF Transmit Bu.
USART Operation: SPI Mode 15-4 USART Peripheral Interface, SPI Mode 15.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master . An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master .
USART Operation: SPI Mode 15-5 USART Peripheral Interface, SPI Mode 15.2.2 Master Mode Figure 15 − 2. USART Master and External Slave Receive Buffer UxRXBUF Receive Shift Register MSB LSB Transmit Buf fer UxTXBUF Transmit Shift Register MSB LSB SPI Receive Buffer Data Shift Register (DSR) MSB LSB SOMI SOMI SIMO SIMO MASTER SLA VE Px.
USART Operation: SPI Mode 15-6 USART Peripheral Interface, SPI Mode 15.2.3 Slave Mode Figure 15 − 3. USART Slave and External Master Receive Buffer UxRXBUF Receive Shift Register LSB MSB Transmit Buf fer UxTXBUF Transmit Shift Register LSB MSB SPI Receive Buffer Data Shift Register DSR LSB MSB SOMI SOMI SIMO SIMO MASTER SLA VE Px.
USART Operation: SPI Mode 15-7 USART Peripheral Interface, SPI Mode 15.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active.
USART Operation: SPI Mode 15-8 USART Peripheral Interface, SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 15 − 6 and Figure 15 − 7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register .
USART Operation: SPI Mode 15-9 USART Peripheral Interface, SPI Mode 15.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USAR T baud rate generator on the UCLK pin as shown in Figure 15 − 8.
USART Operation: SPI Mode 15-10 USART Peripheral Interface, SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART . T iming for each case is shown in Figure 15 − 9.
USART Operation: SPI Mode 15-1 1 USART Peripheral Interface, SPI Mode 15.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI T ransmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character .
USART Operation: SPI Mode 15-12 USART Peripheral Interface, SPI Mode SPI Receive Interrupt Operation Th e URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 15 − 1 1 and Figure 15 − 12. An interrupt request is generated if URXIEx and GIE are also set.
USART Registers: SPI Mode 15-13 USART Peripheral Interface, SPI Mode 15.3 USART Registers: SPI Mode T able 15 − 1 lists the registers for all devices implementing a USART module. T able 15 − 2 applies only to devices with a second USART module, USAR T1.
USART Registers: SPI Mode 15-14 USART Peripheral Interface, SPI Mode UxCTL, USART Control Register 76543 210 Unused Unused I2C † CHAR LISTEN SYNC MM SWRST rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 1 Unused Bits 7 − 6 Unused I2C † Bit 5 I2C mode enable.
USART Registers: SPI Mode 15-15 USART Peripheral Interface, SPI Mode UxTCTL, USART T ransmit Control Register 76543 210 CKPH CKPL SSELx Unused Unused STC TXEPT rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 1 CKPH Bit 7 Clock phase select.
USART Registers: SPI Mode 15-16 USART Peripheral Interface, SPI Mode UxRCTL, USART Receive Control Register 76543 210 FE Unused OE Unused Unused Unused Unused Unused rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 FE Bit 7 Framing error flag.
USART Registers: SPI Mode 15-17 USART Peripheral Interface, SPI Mode UxBR0, USART Baud Rate Control Register 0 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rw rw rw rw rw rw rw rw UxBR1, USART Baud Rate .
USART Registers: SPI Mode 15-18 USART Peripheral Interface, SPI Mode UxRXBUF , USART Receive Buffer Register 76543 210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rrrrrrrr UxRXBUFx Bits 7 − 0 The receive-data buffer is user accessible and contains the last received character from the receive shift register .
USART Registers: SPI Mode 15-19 USART Peripheral Interface, SPI Mode ME1, Module Enable Register 1 76543 210 USPIE0 rw − 0 Bit 7 This bit may be used by other modules. See device-specific datasheet. USPIE0 Bit 6 USAR T0 SPI enable. This bit enables the SPI mode for USART0.
USART Registers: SPI Mode 15-20 USART Peripheral Interface, SPI Mode IE1, Interrupt Enable Register 1 76543 210 UTXIE0 URXIE0 rw − 0 rw − 0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled URXIE0 Bit 6 USAR T0 receive interrupt enable.
USART Registers: SPI Mode 15-21 USART Peripheral Interface, SPI Mode IFG1, Interrupt Flag Register 1 76543 210 UTXIFG0 URXIFG0 rw − 1 rw − 0 UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty . 0 No interrupt pending 1 Interrupt pending URXIFG0 Bit 6 USAR T0 receive interrupt flag.
16-1 OA OA The OA is a general purpose operational amplifier . This chapter describes the OA. Three OA modules are implemented in the MSP430FG43x devices. T opic Page 16.1 OA Introduction 16-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OA Introduction 16-2 OA 16.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analog- to-digital conversion. Features of the OA include: - Single supply , low-current operation - Rail-to-rail output - Software selectable Rail-to-Rail input - Programmable settling time vs.
OA Introduction 16-3 OA Figure 16−1. OA Block Diagram OAPMx OAPx 0 1 1 OAFBRx A12 ext. (OA0) A13 ext. (OA1) A14 ext. (OA2) OAADC0 4R 4R 2R 2R R R R R OAxOUT R BOTT OM R TOP OAx + − OAFCx={2 − 7} OAFBRx > 0 OAADC1 OAFCx=0 OAFCx=1 R BOTT OM OAxT AP OAFCx=6 OAxI0 OA0I1 Int.
OA 16-4 OA 16.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. 16.
OA 16-5 OA 16.2.4 OA Configurations T h e OA can be configured for different amplifier functions with the OAFCx bits. as listed in T able 16 − 1. T able 16 − 1.
OA 16-6 OA Non-Inverting PGA Mode In this mode the output of the OAx is connected to R TOP and R BOTTOM is connected t o A V SS . The OAxT AP signal is connected to the inverting input of th e OAx providing a non-inverting amplifier configuration with a programmable gain of [1+OAxT AP ratio].
OA 16-7 OA Figure 16 − 2 shows an example of a two-opamp differential amplifier using OA 0 and OA1. The control register settings and are shown in T able 16 − 2. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in T able 16 − 3.
OA 16-8 OA Figure 16 − 3. T wo Opamp Differential Amplifier OAx Interconnections OAPx 00 01 10 11 OAPMx 0 1 1 OAFBRx A13 ext. OAADC0 4R 4R 2R 2R R R R R OA1 + − OAADC1 0 1 00 01 10 11 000 001 100 01 1 010 111 11 0 101 000 001 100 01 1 010 111 11 0 101 3 00 01 10 11 A3 int.
OA 16-9 OA Figure 16 − 4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2. The control register settings are shown in T able 16 − 4. Th e gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal.
OA 16-10 OA Figure 16 − 5. Three Opamp Differential Amplifier OAx Interconnections OAPMx OAPx OAFBRx 4R 4R 2R 2R R R R R OA0OUT OA0R BOTTOM OA0 + − OA0T AP 00 01 10 11 0 1 00 01 10 11 000 001 100 01 1 010 111 11 0 101 000 001 100 01 1 010 111 11 0 101 3 OAPMx 0 1 1 OAFBRx A14 ext.
OA Registers 16-1 1 OA 16.3 OA Registers The OA registers are listed in T able 16 − 6. T able 16 − 6. Register Short Form Register T ype Address Initial State OA0 Control Register 0 OA0CTL0 Read/w.
OA Registers 16-12 OA OAxCTL0, Opamp Control Register 0 76543 210 OANx OAPx OAPMx OAADC1 OAADC0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 OANx Bits 7-6 Inverting input select. These bits select the input signal for the OA inverting input.
OA Registers 16-13 OA OAxCTL1, Opamp Control Register 1 76543 210 OAFBRx OAFCx Reserved OARRIP rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 OAFBRx Bits 7-5 OAx feedback resistor select 000 T ap 0 001 T ap 1 010 T ap 2 01 1 T ap 3 100 T ap 4 101 T ap 5 1 10 T ap 6 111 Ta p 7 OAFCx Bits 4-2 OAx function control.
17-1 Comparator_A Comparator_A Comparator_A is an analog voltage comparator . This chapter describes Comparator_A. Comparator_A is implemented in all MSP430x4xx devices. T opic Page 17.1 Comparator_A Introduction 17-2 . . . . . . . . . . . . . . . . .
Comparator_A Introduction 17-2 Comparator_A 17.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals.
Comparator_A Introduction 17-3 Comparator_A Figure 17−1. Comparator_A Block Diagram CAOUT + − CAEX 0.5x 0.25x Set_CAIFG CA1 CCI1B + − 0V G D S P2CA0 P2CA1 CAF CARSEL CAON CAREFx 10 00 01 10 11 00 01 10 11 1 0 1 0 1 0 1 0 1 0 0V 10 V CAREF CA0 0 1 0 1 V CC V CC V CC T au ~ 2.
Comparator_A Operation 17-4 Comparator_A 17.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 17.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals.
Comparator_A Operation 17-5 Comparator_A 17.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter . Any comparator output oscillates if the voltage difference across the input terminals i s small.
Comparator_A Operation 17-6 Comparator_A 17.2.5 Comparator_A, Port Disable Register CAPD Th e comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from V CC to GND.
Comparator_A Operation 17-7 Comparator_A 17.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion.
Comparator_A Operation 17-8 Comparator_A The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 17 − 6. Figure 17 − 6. Timing for T emperature Measurement Systems V C V CC 0.
Comparator_A Registers 17-9 Comparator_A 17.3 Comparator_A Registers The Comparator_A registers are listed in T able 17 − 1. T able 17 − 1. Comparator_A Registers Register Short Form Register T yp.
Comparator_A Registers 17-10 Comparator_A CACTL1, Comparator_A Control Register 1 76543 210 CAEX CARSEL CAREFx CAON CAIES CAIE CAIFG rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) CAEX Bit 7 Comparator_A exchange.
Comparator_A Registers 17-1 1 Comparator_A CACTL2, Comparator_A Control Register 2 76543 210 Unused P2CA1 P2CA0 CAF CAOUT rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) r − (0) Unused Bits 7-4 Unused. P2CA1 Bit 3 Pin to CA1.
18-1 LCD Controller LCD Controller The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes LCD controller . The LCD controller is implemented on all MSP430x4xx devices, except the MSP430x42x0 devices. T opic Page 18.1 LCD Controller Introduction 18−2 .
LCD Controller Introduction 18-2 LCD Controller 18.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically . The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs.
LCD Controller Introduction 18-3 LCD Controller Figure 18−1. LCD Controller Block Diagram Display Memory 20x 8 − bits Segment Output Control Mux Analog V oltage Multiplexer Timing Generator R23 R1.
LCD Controller Operation 18-4 LCD Controller 18.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operation of LCD controller is discussed in the following sections. 18.2.1 LCD Memory Th e LCD memory map is shown in Figure 18 − 2.
LCD Controller Operation 18-5 LCD Controller 18.2.4 LCD V oltage Generation The voltages required for the LCD signals are supplied externally to pins R33, R23, R13, and R03. Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in T able 18 − 1.
LCD Controller Operation 18-6 LCD Controller 18.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 18 − 3 shows some example static waveforms. Figure 18 − 3. Example Static Waveforms f frame COM0 SP1 SP2 Resulting V oltage for Segment a (COM0 − SP1) Segment Is On.
LCD Controller Operation 18-7 LCD Controller Figure 18 − 4 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD Controller Operation 18-8 LCD Controller Static Mode Software Example ; Al l eight segments of a digit are often located in four ; display memory bytes with the static display method. ; a EQU 001h b EQU 010h c EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h ; The register content of Rx should be displayed.
LCD Controller Operation 18-9 LCD Controller 18.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used.
LCD Controller Operation 18-10 LCD Controller Figure 18 − 6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD Controller Operation 18-1 1 LCD Controller 2-Mux Mode Software Example ; Al l eight segments of a digit are often located in two ; display memory bytes with the 2mux display rate ; a EQU 002h b EQU 020h c EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h ; The register content of Rx should be displayed.
LCD Controller Operation 18-12 LCD Controller 18.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 18 − 7 shows some example 3-mux waveforms. Figure 18 − 7.
LCD Controller Operation 18-13 LCD Controller Figure 18 − 8 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD Controller Operation 18-14 LCD Controller 3-Mux Mode Software Example ; Th e 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes.
LCD Controller Operation 18-15 LCD Controller 18.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 18 − 9 shows some example 4-mux waveforms. Figure 18 − 9.
LCD Controller Operation 18-16 LCD Controller Figure 18 − 10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD Controller Operation 18-17 LCD Controller 4-Mux Mode Software Example ; Th e 4mux rate supports eight segments for each digit. ; All eight segments of a digit can often be located in ; one display.
LCD Controller Operation 18-18 LCD Controller 18.3 LCD Controller Registers The LCD Controller registers are listed in T able 18 − 2. T able 18 − 2.
LCD Controller Operation 18-19 LCD Controller LCDCTL, LCD Control Register 76543 210 LCDPx LCDMXx LCDSON Unused LCDON rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 LCDPx Bits 7-5 LCD Port Select. These bits select the pin function to be port I/O or LCD function for groups of segments pins.
19-1 LCD_A Controller LCD_A Controller The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_A controller . The LCD_A controller is implemented on the MSP430x42x0 and MSP430F46xx devices. T opic Page 19.1 LCD Controller Introduction 19 − 2 .
LCD_A Controller Introduction 19-2 LCD_A Controller 19.1 LCD_A Controller Introduction Th e LCD_A controller directly drives LCD displays by creating the ac segment and common voltage signals automatically . The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs.
LCD_A Controller Introduction 19-3 LCD_A Controller Figure 19−1. LCD_A Controller Block Diagram VLCDREFx Display Memory 20x 8 − bits Segment Output Control Mux Analog V oltage Multiplexer Timing G.
LCD_A Controller Operation 19-4 LCD_A Controller 19.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup and operation of the LCD_A controller is discussed in the following sections. 19.2.1 LCD Memory Th e LCD memory map is shown in Figure 19 − 2.
LCD_A Controller Operation 19-5 LCD_A Controller 19.2.3 LCD_A V oltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveform voltage, V 1 , as well as the fractional LCD biasing voltages V2 − V5. V LCD may be sourced from A V CC , an internal charge pump, or externally .
LCD_A Controller Operation 19-6 LCD_A Controller T o source the bias voltages V2 − V4 externally , REXT is set. This also disables the internal bias generation.
LCD_A Controller Operation 19-7 LCD_A Controller Th e internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3 bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In static mode the internal divider is disabled. Some devices share the LCDCAP , R33, and R23 functions.
LCD_A Controller Operation 19-8 LCD_A Controller 19.2.4 LCD Timing Generation Th e LCD_A controller uses the f LCD signal from the integrated ACLK prescaler to generate the timing for common and segment lines. ACLK is assumed to be 32768 Hz for generating f LCD .
LCD_A Controller Operation 19-9 LCD_A Controller 19.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 19 − 4 shows some example static waveforms. Figure 19 − 4. Example Static Waveforms f frame COM0 SP1 SP2 Resulting V oltage for Segment a (COM0 − SP1) Segment Is On.
LCD_A Controller Operation 19-10 LCD_A Controller Figure 19 − 5 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD_A Controller Operation 19-1 1 LCD_A Controller Static Mode Software Example ; Al l eight segments of a digit are often located in four ; display memory bytes with the static display method. ; a EQU 001h b EQU 010h c EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h ; The register content of Rx should be displayed.
LCD_A Controller Operation 19-12 LCD_A Controller 19.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 19 − 6 shows some example 2-mux, 1/2 bias waveforms. Figure 19 − 6.
LCD_A Controller Operation 19-13 LCD_A Controller Figure 19 − 7 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD_A Controller Operation 19-14 LCD_A Controller 2-Mux Mode Software Example ; Al l eight segments of a digit are often located in two ; display memory bytes with the 2mux display rate ; a EQU 002h b EQU 020h c EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h ; The register content of Rx should be displayed.
LCD_A Controller Operation 19-15 LCD_A Controller 19.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 19 − 8 shows some example 3-mux, 1/3 bias waveforms. Figure 19 − 8.
LCD_A Controller Operation 19-16 LCD_A Controller Figure 19 − 9 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD_A Controller Operation 19-17 LCD_A Controller 3-Mux Mode Software Example ; Th e 3mux rate can support nine segments for each ; digit. The nine segments of a digit are located in ; 1 1/2 display memory bytes.
LCD_A Controller Operation 19-18 LCD_A Controller 19.2.9 4-Mux Mode In 3-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 19 − 10 shows some example 4-mux, 1/3 bias waveforms.
LCD_A Controller Operation 19-19 LCD_A Controller Figure 19 − 1 1 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user ’ s application depends on the LCD pin-out and on the MSP430-to-LCD connections.
LCD_A Controller Operation 19-20 LCD_A Controller 4-Mux Mode Software Example ; Th e 4mux rate supports eight segments for each digit. ; All eight segments of a digit can often be located in ; one dis.
LCD_A Controller Operation 19-21 LCD_A Controller 19.3 LCD Controller Registers The LCD Controller registers are listed in T able 19 − 2. T able 19 − 2.
LCD_A Controller Operation 19-22 LCD_A Controller LCDACTL, LCD_A Control Register 76543 210 LCDFREQx LCDMXx LCDSON Unused LCDON rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 LCDFREQx Bits 7-5 LCD Frequency Select. These bits select the ACLK divider for the LCD frequency .
LCD_A Controller Operation 19-23 LCD_A Controller LCDAPCTL0, LCD_A Port Control Register 0 76543 210 LCDS28 LCDS24 LCDS20 LCDS16 LCDS12 LCDS8 LCDS4 LCDS0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 LCDS28 Bit 7 LCD Segment 28 to 31 Enable.
LCD_A Controller Operation 19-24 LCD_A Controller LCDAPCTL1, LCD_A Port Control Register 1 76543 210 Unused LCDS36 LCDS32 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 Unused Bits 7 − 2 Unused LCDS36 Bit 1 LCD Segment 36 to 39 Enable.
LCD_A Controller Operation 19-25 LCD_A Controller LCDA VCTL0, LCD_A V oltage Control Register 0 76543 210 Unused R03EXT REXT VLCDEXT LCDCPEN VLCDREFx LCD2B rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 Unused Bit 7 Unused R03EXT Bit 6 V5 voltage select.
LCD_A Controller Operation 19-26 LCD_A Controller LCDA VCTL1, LCD_A V oltage Control Register 1 76543 210 Unused VLCDx Unused rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 Unused Bits 7 − 5 Unused VLCDx Bits 4 − 1 Charge pump voltage select.
20-1 ADC12 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter . This chapter describes the ADC12. The ADC12 is implemented in the MSP430x43x and MSP430x44x devices. T opic Page 20.1 ADC12 Introduction 20-2 . . . . . . . . .
ADC12 Introduction 20-2 ADC12 20.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buf fer .
ADC12 Introduction 20-3 ADC12 Figure 20−1. ADC12 Block Diagram Sample and Hold Ve REF+ 12 − bit SAR V R − − 16 x 12 Memory Buffer − − 16 x 8 Memory Control − V R+ V REF+ Ve REF − V REF − / ADC12SC TA 1 TB1 TB0 Divider /1 .. /8 ADC12DIVx ADC12CLK ENC MSC SHP SHT0x SAMPCON SHI S/H Convert Sync Sample Timer /4 .
ADC12 Operation 20-4 ADC12 20.2 ADC12 Operation Th e ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 20.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory .
ADC12 Operation 20-5 ADC12 20.2.2 ADC12 Inputs and Multiplexer Th e eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer . The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 20 − 2.
ADC12 Operation 20-6 ADC12 20.2.3 V oltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V . Either of these reference voltages may be used internally and externally on pin V REF+ .
ADC12 Operation 20-7 ADC12 20.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI.
ADC12 Operation 20-8 ADC12 Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer . The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period t sample .
ADC12 Operation 20-9 ADC12 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t sample , as shown below in Figure 20 − 5.
ADC12 Operation 20-10 ADC12 20.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register . The SREFx bits define the voltage reference and the INCHx bits select the input channel.
ADC12 Operation 20-1 1 ADC12 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CST ART ADDx bits. Figure 20 − 6 shows the flow of the Single-Channel, Single-Conversion mode.
ADC12 Operation 20-12 ADC12 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written t o the conversion memories starting with the ADCMEMx defined by the CST ART ADDx bits. The sequence stops after the measurement of the channel with a set EOS bit.
ADC12 Operation 20-13 ADC12 Repeat-Single-Channel Mode A single channel is sampled and converted continuously . The ADC results are written t o the ADC12MEMx defined by the CST ART ADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion.
ADC12 Operation 20-14 ADC12 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly . The ADC results are written to the conversion memories starting with the ADC12MEMx defined b y the CST ART ADDx bits.
ADC12 Operation 20-15 ADC12 Using the Multiple Sample and Convert (MSC) Bit T o configure the converter to perform successive conversions automatically an d as quickly as possible, a multiple sample and convert function is available.
ADC12 Operation 20-16 ADC12 20.2.8 Using the Integrated T emperature Sensor T o use the on-chip temperature sensor , the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
ADC12 Operation 20-17 ADC12 20.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic ef fects, and noise.
ADC12 Operation 20-18 ADC12 20.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: - ADC12IFG0-ADC12IFG15 - ADC12OV , ADC12MEMx overflow - ADC12T OV , ADC12 conversion time overflow Th e ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result.
ADC12 Operation 20-19 ADC12 ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine.
ADC12 Registers 20-20 ADC12 20.3 ADC12 Registers The ADC12 registers are listed in T able 20 − 2 . T able 20 − 2. ADC12 Registers Register Short Form Register T ype Address Initial State ADC12 con.
ADC12 Registers 20-21 ADC12 ADC12CTL0, ADC12 Control Register 0 15 14 13 12 1 1 10 9 8 SHT1x SHT0x rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 210 MSC.
ADC12 Registers 20-22 ADC12 MSC Bit 7 Multiple sample and conversion. V alid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion.
ADC12 Registers 20-23 ADC12 ADC12CTL1, ADC12 Control Register 1 15 14 13 12 1 1 10 9 8 CST ART ADDx SHSx SHP ISSH rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0.
ADC12 Registers 20-24 ADC12 ADC12 SSELx Bits 4-3 ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 1 1 SMCLK CONSEQx Bits 2-1 Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 1 1 Repeat-sequence-of-channels ADC12 BUSY Bit 0 ADC12 busy .
ADC12 Registers 20-25 ADC12 ADC12MCTLx, ADC12 Conversion Memory Control Registers 76543 210 EOS SREFx INCHx rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) Modifiable only when ENC = 0 EOS Bit 7 End of sequence.
ADC12 Registers 20-26 ADC12 ADC12IE, ADC12 Interrupt Enable Register 15 14 13 12 1 1 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE1 1 ADC12IE10 ADC12IE9 ADC12IE8 rw − (0) rw − (0) rw − .
ADC12 Registers 20-27 ADC12 ADC12IV , ADC12 Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0000000 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 ADC12IVx 0 r0 r0 r − (0) r − (0) r − (0) r − (0) r.
21-1 SD16 SD16 The SD16 module is a multichannel 16-bit, sigma-delta analog-to-digital converter . This chapter describes the SD16. The SD16 module is implemented in the MSP430FE42x and MSP430F42x devices. T opic Page 21.1 SD16 Introduction 21-2 . . .
SD16 Introduction 21-2 SD16 21.1 SD16 Introduction The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully dif ferential multiplexed inputs including a built-in temperature sensor .
SD16 Introduction 21-3 SD16 Figure 21−1. SD16 Block Diagram Channel 0 Channel 1 15 0 SD16 Control Block SD16DIVx f M ACLK T ACLK SD16SSELx 00 01 10 11 00 01 10 11 MCLK SMCLK AV CC V REF Divider 1/2/4/8 000 SD16INCHx + − 001 + − 010 + − 01 1 + − 100 + − 101 + − 11 0 + − 111 + − PGA 1.
SD16 Operation 21-4 SD16 21.2 SD16 Operation The SD16 module is configured with user software. The setup and operation of the SD16 is discussed in the following sections. 21.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator .
SD16 Operation 21-5 SD16 21.2.5 Channel Selection Each SD16 channel can convert up to 8 dif ferential pair inputs multiplexed into the PGA. Up to six input pairs (A0-A5) are available externally on the device. Se e the device-specific data sheet for analog input pin information.
SD16 Operation 21-6 SD16 21.2.6 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC 3 comb filter . The transfer function is described in the z-Domain by:.
SD16 Operation 21-7 SD16 Figure 21 − 3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDL Yx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
SD16 Operation 21-8 SD16 Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits. Figure 21 − 4 shows the digital filter output bits and their relation to SD16MEMx for each OSR.
SD16 Operation 21-9 SD16 21.2.7 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversion results for each channel are moved to the corresponding SD16MEMx register with each decimation step of the digital filter .
SD16 Operation 21-10 SD16 21.2.8 Conversion Modes The SD16 module can be configured for four modes of operation, listed in T able 21 − 2. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode.
SD16 Operation 21-1 1 SD16 Figure 21 − 6. Single Channel Operation Channel 0 SD16SNGL = 1 SD16GRP = 0 Time Conversion SD16SC Channel 1 SD16SNGL = 1 SD16GRP = 0 Conversion Channel 2 SD16SNGL = 0 SD16.
SD16 Operation 21-12 SD16 Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set.
SD16 Operation 21-13 SD16 21.2.9 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of f M clock cycles and can range from 0 to 255.
SD16 Operation 21-14 SD16 Figure 21 − 9. Start of Conversion using Preload Delayed Conversion 40 SD16OSRx = 32 Start of Conversion Time Conversion 32 Conversion 32 f M cycles: 1 st Sample Ch1 SD16PR.
SD16 Operation 21-15 SD16 21.2.10 Using the Integrated T emperature Sensor T o use the on-chip temperature sensor , the user selects the analog input channel SD16INCHx = 1 10. Any other configuration is done as if an external channel was selected, including SD16INTDL Yx and SD16GAINx settings.
SD16 Operation 21-16 SD16 21.2.1 1 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set.
SD16 Operation 21-17 SD16 SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
SD16 Registers 21-18 SD16 21.3 SD16 Registers The SD16 registers are listed in T able 21 − 3: T able 21 − 3. SD16 Registers Register Short Form Register T ype Address Initial State SD16 Control SD.
SD16 Registers 21-19 SD16 SD16CTL, SD16 Control Register 15 14 13 12 1 1 10 9 8 Reserved SD16LP r0 r0 r0 r0 r0 r0 r0 rw − 0 76543 210 SD16DIVx SD16SSELx SD16 VMIDON SD16 REFON SD16OVIE Reserved rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 r0 Reserved Bits 15-9 Reserved SD16LP Bit 8 Low power mode.
SD16 Registers 21-20 SD16 SD16CCTLx, SD16 Channel x Control Register 15 14 13 12 1 1 10 9 8 Reserved SD16SNGL SD16OSRx r0 r0 r0 r0 r0 rw − 0 rw − 0 rw − 0 76543 210 SD16 LSBTOG SD16 LSBACC SD16 .
SD16 Registers 21-21 SD16 SD16IFG Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software.
SD16 Registers 21-22 SD16 SD16MEMx, SD16 Channel x Conversion Memory Register 15 14 13 12 1 1 10 9 8 Conversion Results rrrrrrrr 76543 210 Conversion Results rrrrrrrr Conversion Result Bits 15-0 Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit.
SD16 Registers 21-23 SD16 SD16IV , SD16 Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0000000 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 SD16IVx 0 r0 r0 r0 r − 0 r − 0 r − 0 r − 0 r0 SD16IV.
22-1 SD16_A SD16_A The SD16_A module is a single-converter 16-bit, sigma-delta analog-to-digital conversion module with high impedance input buffer . This chapter describes the SD16_A. The SD16_A module is implemented in the MSP430F42x0 devices. T opic Page 22.
SD16_A Introduction 22-2 SD16_A 22.1 SD16_A Introduction The SD16_A module consists of one sigma-delta analog-to-digital converter with an high impedance input buffer and an internal voltage reference. It has up to 8 fully differential multiplexed inputs including a built-in temperature sensor .
SD16_A Introduction 22-3 SD16_A Figure 22−1. SD16_A Block Diagram 15 0 SD16DIVx ACLK T ACLK SD16SSELx 00 01 10 11 00 01 10 11 MCLK SMCLK AV CC V REF Divider 1/2/4/8 A0 000 SD16INCHx + − 001 + − .
SD16_A Operation 22-4 SD16_A 22.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 22.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator .
SD16_A Operation 22-5 SD16_A 22.2.5 Channel Selection The SD16_A can convert up to 8 differential pair inputs multiplexed into the PGA. Up to five input pairs (A0-A4) are available externally on the device. A resistive divider to measure the supply voltage is available using the A5 multiplexer input.
SD16_A Operation 22-6 SD16_A 22.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC 3 comb filter . The transfer function is described in the z-Domain.
SD16_A Operation 22-7 SD16_A Figure 22 − 3 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDL Yx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
SD16_A Operation 22-8 SD16_A Digital Filter Output Th e number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 22 − 4 shows the digital filter output and their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNI setting.
SD16_A Operation 22-9 SD16_A 0 4 8 12 16 20 24 1 53 2 6 97 23 22 21 19 18 17 15 14 13 1 1 10 28 27 26 25 29 0 4 8 12 16 20 24 1 53 2 6 97 23 22 21 19 18 17 15 14 13 1 1 10 28 27 26 25 29 OSR=32, LSBAC.
SD16_A Operation 22-10 SD16_A 22.2.8 Conversion Memory Register: SD16MEM0 The SD16MEM0 register is associated with the SD16_A channel. Conversion results are moved to the SD16MEM0 register with each decimation step of the digital filter . The SD16IFG bit is set when new data is written to SD16MEM0.
SD16_A Operation 22-1 1 SD16_A 22.2.9 Conversion Modes The SD16_A module can be configured for two modes of operation, listed in T able 22 − 3. The SD16SNGL bit selects the conversion mode. T able 22 − 3. Conversion Mode Summary SD16SNGL Mode Operation 1 Single conversion The channel is converted once.
SD16_A Operation 22-12 SD16_A 22.2.10 Using the Integrated T emperature Sensor T o use the on-chip temperature sensor , the user selects the analog input channel SD16INCHx = 1 10. Any other configuration is done as if an external channel was selected, including SD16INTDL Yx and SD16GAINx settings.
SD16_A Operation 22-13 SD16_A 22.2.1 1 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel: - SD16IFG - SD16OVIFG The SD16IFG bit is set when the SD16MEM0 memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set.
SD16_A Registers 22-14 SD16_A 22.3 SD16_A Registers The SD16_A registers are listed in T able 22 − 4: T able 22 − 4. SD16_A Registers Register Short Form Register T ype Address Initial State SD16_.
SD16_A Registers 22-15 SD16_A SD16CTL, SD16_A Control Register 15 14 13 12 1 1 10 9 8 Reserved SD16XDIV SD16LP r0 r0 r0 r0 rw − 0 rw − 0 rw − 0 rw − 0 76543 210 SD16DIVx SD16SSELx SD16 VMIDON .
SD16_A Registers 22-16 SD16_A SD16CCTL0, SD16_A Control Register 0 15 14 13 12 1 1 10 9 8 Reserved SD16BUFx SD16UNI SD16XOSR SD16SNGL SD16OSRx r0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 .
SD16_A Registers 22-17 SD16_A SD16 LSBACC Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the SD16_A conversion result. 0 SD16MEMx contains the most significant 16-bits of the conversion. 1 SD16MEMx contains the least significant 16-bits of the conversion.
SD16_A Registers 22-18 SD16_A SD16INCTL0, SD16_A Input Control Register 76543 210 SD16INTDL Yx SD16GAINx SD16INCHx rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 rw − 0 SD16 INTDL Yx Bits 7-6 Interrupt delay generation after conversion start.
SD16_A Registers 22-19 SD16_A SD16MEM0, SD16_A Conversion Memory Register 15 14 13 12 1 1 10 9 8 Conversion Results r r r r r r r r 76543 210 Conversion Results r r r r r r r r Conversion Result Bits 15-0 Conversion Results. The SD16MEMx register holds the upper or lower 16-bits of the digital filter output, depending on the SD16LSBACC bit.
SD16_A Registers 22-20 SD16_A SD16IV , SD16_A Interrupt V ector Register 15 14 13 12 1 1 10 9 8 0 0000000 r0 r0 r0 r0 r0 r0 r0 r0 76543 210 0 0 0 SD16IVx 0 r0 r0 r0 r − 0 r − 0 r − 0 r − 0 r0 .
23-1 DAC12 DAC12 Th e DAC12 module is a 12-bit, voltage output digital-to-analog converter . This chapter describes the DAC12. T wo DAC12 modules are implemented in the MSP430FG43x devices. Only DAC12_0 is implemented in MSP430x42x0 devices. T opic Page 23.
DAC12 Introduction 23-2 DAC12 23.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured i n 8 - o r 12-bit mode and may be used in conjunction with the DMA controller . When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
DAC12 Introduction 23-3 DAC12 Figure 23−1. DAC12 Block Diagram DAC12_0 DAC12_0OUT 2.5V or 1.5V reference from ADC12 DAC12SREFx V R − V R+ DAC12_0DA T DAC12_0Latch DAC12_1 DAC12LSELx V R − V R+ D.
DAC12 Introduction 23-4 DAC12 Figure 23 − 2. DAC12 Block Diagram For MSPx42x0 Devices DAC12_0 DAC12_0OUT 1.2V reference from SD16 DAC12SREFx V R − V R+ DAC12_0DA T DAC12_0Latch AV SS 00 01 10 11 V.
DAC12 Operation 23-5 DAC12 23.2 DAC12 Operation Th e DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 23.2.1 DAC12 Core The DAC12 can be configured to operate in 8- or 12-bit mode using the DAC12RES bit.
DAC12 Operation 23-6 DAC12 23.2.2 DAC12 Reference On MSP430FG43x devices, the reference for the DAC12 is configured to use either a n external reference voltage or the internal 1.
DAC12 Operation 23-7 DAC12 23.2.4 DAC12_xDA T Data Format The DAC12 supports both straight binary and 2 ’ s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 23 − 3.
DAC12 Operation 23-8 DAC12 23.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the of fset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so.
DAC12 Operation 23-9 DAC12 23.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event.
DAC12 Operation 23-10 DAC12 23.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller . Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt. The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched from the DAC12_xDA T register into the data latch.
DAC12 Registers 23-1 1 DAC12 23.3 DAC12 Registers The DAC12 registers are listed in T able 23 − 2. T able 23 − 2. DAC12 Registers Register Short Form Register T ype Address Initial State DAC12_0 c.
DAC12 Registers 23-12 DAC12 DAC12_xCTL, DAC12 Control Register 15 14 13 12 1 1 10 9 8 DAC12OPS DAC12SREFx DAC12RES DAC12LSELx DAC12 CALON DAC12IR rw − (0) rw − (0) rw − (0) rw − (0) rw − (0).
DAC12 Registers 23-13 DAC12 DAC12 CALON Bit 9 DAC12 calibration on. This bit initiates the DAC12 of fset calibration sequence and is automatically reset when the calibration completes. 0 Calibration is not active 1 Initiate calibration/calibration in progress DAC12IR Bit 8 DAC12 input range.
DAC12 Registers 23-14 DAC12 DAC12_xDA T , DAC12 Data Register 15 14 13 12 1 1 10 9 8 0 0 0 0 DAC12 Data r(0) r(0) r(0) r(0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 210 DAC12 Data rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) Unused Bits 15-12 Unused.
24-1 Scan IF The Scan IF peripheral automatically scans sensors and measures linear or rotational motion. This chapter describes the Scan interface. The Scan IF is implemented in the MSP430FW42x devices. T opic Page 24.1 Scan IF Introduction 24-2 .
Scan IF Introduction 24-2 Scan IF 24.1 Scan IF Introduction The Scan IF module is used to automatically measure linear or rotational motion with the lowest possible power consumption. The Scan IF consists of three blocks: the analog front end (AFE), the processing state machine (PSM), and the timing state machine (TSM).
Scan IF Introduction 24-3 Scan IF Figure 24−1. Scan IF Block Diagram Timing State Machine (TSM) w/ oscillator Processing State Machine (PSM) Analog Input Multiplexer Interrupt Request Rotation Data .
Scan IF Operation 24-4 Scan IF 24.2 Scan IF Operation The Scan IF is configured with user software. The setup and operation of the Scan IF is discussed in the following sections. 24.2.1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement.
Scan IF Operation 24-5 Scan IF Figure 24 − 2. Scan IF Analog Front End Block Diagram SIFTESTD SIFTESTS1(tsm) + − 1 0 SIFCH0 SIFCH1 SIFCH2 00 01 10 11 SIFCH3 1 0 SIFCI SIFCISEL SIFCAON SIFCAX SIFCACI3 10 11 01 00 SIFTCH0x 2 SIFTCH1x SIF2OUT SIF3OUT SIFTCH0OUT SIF1OUT SIF0OUT SIFTCH1OUT SIFCAINV SIFRSON(tsm) 2 Output Stage SIFCHx(tsm) 2 Sync.
Scan IF Operation 24-6 Scan IF Excitation Th e excitation circuitry is used to excite the LC sensors or to power the resistor dividers. The excitation circuitry is shown in Figure 24 − 3 for one LC sensor connected.
Scan IF Operation 24-7 Scan IF Figure 24 − 3. Excitation and Sample-And-Hold Circuitry SIFEX(tsm) SIFVSS 1 1 10 SIFCH0 SIFCOM Sample-and-Hold SIFLCEN(tsm) SIFTEN 1 0 Damping Excitation VSS 1 0 Excit.
Scan IF Operation 24-8 Scan IF Sample-And-Hold The sample-and-hold is used to sample the sensor voltage to be measured. The sample-and-hold circuitry is shown in Figure 24 − 3. When SIFSH = 1 and SIFTEN = 0 the sample-and-hold circuitry is enabled and the excitation circuitry and mid-voltage generator are disabled.
Scan IF Operation 24-9 Scan IF Direct Analog And Digital Inputs By setting the SIFCAX bit, external analog or digital signals can be connected directly to the comparator through the SIFCIx inputs. This allows measurement capabilities for optical encoders and other sensors.
Scan IF Operation 24-10 Scan IF When SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIx channels and the SIFCI input allowing storage of the comparator output for on e input signal into the four output bits SIF0OUT - SIF3OUT . This can be used to observe the envelope function of sensors.
Scan IF Operation 24-1 1 Scan IF Comparator and DAC The analog input signals are converted into digital signals by the comparator and the programmable 10-bit DAC. The comparator compares the selected analog signal to a reference voltage generated by the DAC.
Scan IF Operation 24-12 Scan IF For each input there are two DAC registers to set the reference level as listed in T able 24 − 3. T ogether with the last stored output of the comparator , SIFxOUT , the two levels can be used as an analog hysteresis as shown in Figure 24 − 6.
Scan IF Operation 24-13 Scan IF Internal Signal Connections to Timer1_A5 The outputs of the analog front end are connected to 3 different capture/compare registers of T imer1_A5.
Scan IF Operation 24-14 Scan IF 24.2.2 Scan IF Timing State Machine The TSM is a sequential state machine that cycles through the SIFTSMx registers and controls the analog front end and sensor excitation automatically with no CPU intervention. The states are defined within a 24 x 16-bit memory , SIFTSM0 to SIFTSM23.
Scan IF Operation 24-15 Scan IF Figure 24 − 8. Timing State Machine Block Diagram SIFDIV3Bx State Pointer and Control Start Stop SIFTSM0 SIFTSM23 Set_SIFIFG2 SIFTSMx SIFCH0 SIFCH1 SIFLCOFF SIFEX SIF.
Scan IF Operation 24-16 Scan IF TSM Operation The TSM state machine automatically starts and re-starts periodically based on a divided ACLK start signal selected with the SIFDIV2x bits the SIFDIV3Ax and SIFDIV3Bx bits when SIFTSMRP = 0.
Scan IF Operation 24-17 Scan IF TSM State Clock Source Select Th e TSM clock source is individually configurable for each state. The TSM can be clocked from ACLK or a high frequency clock selected with the SIF ACLK bit. When SIF ACLK = 1, ACLK is used for the state, and when SIF ACLK = 0, the high frequency clock is used.
Scan IF Operation 24-18 Scan IF TSM T est Cycles For calibration purposes, to detect sensor drift, or to measure signals other than the sensor signals, a test cycle may be inserted between TSM cycles by setting the SIFTESTD bit. The time between the TSM cycles is not altered by the test cycle insertion as shown in Figure 24 − 9.
Scan IF Operation 24-19 Scan IF TSM Example Figure 24 − 10 shows an example for a TSM sequence. The TSMx register values for the example are shown in T able 24 − 6. ACLK and SIFCLK are not drawn to scale. The TSM sequence starts with SIFTSM0 and ends with a set SIFSTOP bit in SIFTSM9.
Scan IF Operation 24-20 Scan IF 24.2.3 Scan IF Processing State Machine The PSM is a programmable state machine used to determine rotation and direction with its state table stored within MSP430 memory (flash, ROM, or RAM).
Scan IF Operation 24-21 Scan IF Figure 24 − 1 1. Scan IF Processing State Machine Block Diagram Q0 Q3 Q4 Q5 Q6 Q7 S2 S1 SIFQ6EN SIFQ7EN Q7 . . . Q0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MSP430 Memory Range State .
Scan IF Operation 24-22 Scan IF The current-state and next-state logic are reset while the Scan IF is disabled. On e of the bytes stored at addresses SIFPSMV to SIFPSMV + 3 will be loaded first depending on the S1 and S2 signals when the Scan IF is enabled.
Scan IF Operation 24-23 Scan IF PSM Counters Th e PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updated with Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be read via the SIFCNT register . If the SIFCNTRST bit is set, each read access will reset the counters, otherwise the counters remain unchanged when read.
Scan IF Operation 24-24 Scan IF Simplest State Machine Figure 24 − 12 shows the simplest state machine that can be realized with the PSM. The following code shows the corresponding state table and the PSM initialization.
Scan IF Operation 24-25 Scan IF If the PSM is in state 01 of the simplest state machine and the PSM has loaded the corresponding byte at index 01h of the state table: Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 00000000 For this example, S1 and S2 are set at the end of the next TSM sequence.
Scan IF Operation 24-26 Scan IF 24.2.4 Scan IF Debug Register The Scan IF peripheral has a SIFDEBUG register for debugging and development. Only the lower two bits should be written when writing to the SIFDEBUG register and only MOV instructions should be used write to SIFDEBUG.
Scan IF Operation 24-27 Scan IF 24.2.5 Scan IF Interrupts The Scan IF has one interrupt vector for seven interrupt flags listed in T able 24 − 7. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt.
Scan IF Operation 24-28 Scan IF 24.2.6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a damping material to measure rotation. Rotation is measured with LC sensors by exciting the sensors and observing the resulting oscillation.
Scan IF Operation 24-29 Scan IF 24.2.6.1 LC-Sensor Oscillation T est The oscillation test tests if the amplitude of the oscillation after sensor excitation is above a reference level. The DAC is used to set the reference level for the comparator , and the comparator detects if the LC sensor oscillations are above or below the reference level.
Scan IF Operation 24-30 Scan IF 24.2.6.2 LC-Sensor Envelope T est The envelop test measures the decay time of the oscillations after sensor excitation.
Scan IF Operation 24-31 Scan IF Figure 24 − 17. LC Sensor Connections For The Envelope T est Power Supply T erminals SIFCI0 SIFCI SIFCI1 SIFCI2 SIFCI3 470 nF AV CC DV CC DV SS AV SS SIFVSS 470 nF SI.
Scan IF Operation 24-32 Scan IF 24.2.7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation. The damping material and magnets modify the electrical behavior of the sensor so that rotation and direction can be detected.
Scan IF Operation 24-33 Scan IF 24.2.8 Quadrature Decoding The Scan IF can be used to decode quadrature-encoded signals. Signals that are 90 ° out of phase with each other are said to be in quadrature. T o Create the signals, two sensors are positioned depending on the slotting, or coating of the encoder disk.
Scan IF Operation 24-34 Scan IF Figure 24 − 20. Quadrature Decoding State Diagram 00 10 11 01 00 10 11 01 Correct State T ransitions Erroneous State Transitions +1 − 1 T o transfer the state encoding into counts it is necessary to decide what fraction o f the rotation should be counted and on what state transitions.
Scan IF Registers 24-35 Scan IF 24.3 Scan IF Registers The Scan IF registers are listed in T able 24 − 9. T able 24 − 9. Scan IF Registers Register Short Form Register T ype Address Initial State .
Scan IF Registers 24-36 Scan IF SIFDEBUG, Scan IF Debug Register , Write Mode 15 14 13 12 1 1 10 9 8 Reserved wwwwwwww 76543 210 Reserved SIFDEBUGx wwwwwwww Reserved Bits 15-2 Reserved. Must be written as zero. SIFDEBUGx Bits 1-0 SIFDEBUG register mode.
Scan IF Registers 24-37 Scan IF SIFDEBUG, Scan IF Debug Register , Read Mode After 01h Is Written 15 14 13 12 1 1 10 9 8 0 0 0 Index Of TSM Register r r r r r r r r 76543 210 PSM Bits Q7 − Q0 r r r r r r r r Unused Bits 15-13 Unused. After 01h is written to SIFDEBUG, these bits are always read as zero.
Scan IF Registers 24-38 Scan IF SIFDEBUG, Scan IF Debug Register , Read Mode After 03h Is Written 15 14 13 12 1 1 10 9 8 0 Active DAC Register 0 0 DAC Data rrrrrrrr 76543 210 DAC Data rrrrrrrr Unused Bit 15 Unused. After 03h is written to SIFDEBUG, this bit is always read as zero.
Scan IF Registers 24-39 Scan IF SIFCNT , Scan IF Counter Register 15 14 13 12 1 1 10 9 8 SIFCNT2x r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) 76543 210 SIFCNT1x r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) r − (0) SIFCNT2x Bits 15-8 SIFCNT2.
Scan IF Registers 24-40 Scan IF SIFCTL1, Scan IF Control Register 1 15 14 13 12 1 1 10 9 8 SIFIE6 SIFIE5 SIFIE4 SIFIE3 SIFIE2 SIFIE1 SIFIE0 SIFIFG6 rw − (0) rw − (0) rw − (0) rw − (0) rw − (.
Scan IF Registers 24-41 Scan IF SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by the SIFIFGSETx bits. SIFIFG0 must be reset with software. 0 No interrupt pending 1 Interrupt pending SIFTESTD Bit 1 T est cycle insertion.
Scan IF Registers 24-42 Scan IF SIFCTL2, Scan IF Control Register 2 15 14 13 12 1 1 10 9 8 SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2 rw − (0) rw − (0) rw − (0) rw − (0).
Scan IF Registers 24-43 Scan IF SIFVCC2 Bit 8 Mid-voltage generator 0A V CC /2 generator is off 1A V CC /2 generator is on if SIFSH = 0 SIFSH Bit 7 Sample-and-hold enable 0 Sample-and-hold is disabled.
Scan IF Registers 24-44 Scan IF SIFCTL3, Scan IF Control Register 3 15 14 13 12 1 1 10 9 8 SIFS2x SIFS1x SIFIS2x SIFIS1x rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw.
Scan IF Registers 24-45 Scan IF SIFIFGSETx Bits 6-4 SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set. 000 SIFIFG0 is set when SIF0OUT is set. 001 SIFIFG0 is set when SIF0OUT is reset. 010 SIFIFG0 is set when SIF1OUT is set.
Scan IF Registers 24-46 Scan IF SIFCTL4, Scan IF Control Register 4 15 14 13 12 1 1 10 9 8 SIFCNTRST SIFCNT2EN SIFCNT1 ENM SIFCNT1 ENP SIFQ7EN SIFQ6EN SIFDIV3Bx rw − (0) rw − (0) rw − (0) rw −.
Scan IF Registers 24-47 Scan IF SIFDIV3Bx Bits 9-7 TSM start trigger ACLK divider . These bits together with the SIFDIV3Ax bits select the division rate for the TSM start trigger . SIFDIV3Ax Bits 6-4 TSM start trigger ACLK divider . These bits together with the SIFDIV3Bx bits select the division rate for the TSM start trigger .
Scan IF Registers 24-48 Scan IF SIFCTL5, Scan IF Control Register 5 15 14 13 12 1 1 10 9 8 SIFCNT3x rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) 76543 210 SI.
Scan IF Registers 24-49 Scan IF SIFDACRx, Digital-T o-Analog Converter Registers 15 14 13 12 1 1 10 9 8 0 0 0 0 0 0 DAC Data r0 r0 r0 r0 r0 r0 rw rw 76543 210 DAC Data rw rw rw rw rw rw rw rw Unused Bits 15-10 Unused. These bits are always read as zero, and when written, do not affect the DAC output.
Scan IF Registers 24-50 Scan IF SIFTSMx, Scan IF Timing State Machine Registers 15 14 13 12 1 1 10 9 8 SIFREPEA Tx SIF ACLK SIFST OP SIFDAC rw − (0) rw − (0) rw − (0) rw − (0) rw − (0) rw .
Scan IF Registers 24-51 Scan IF SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock source on for this state when SIF ACLK = 1, even though the high frequency clock is not used for the TSM.
Scan IF Registers 24-52 Scan IF Processing State Machine T able Entry (MSP430 Memory Location) 76543 210 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Bit 7 When Q7 = 1, SIFIFG6 will be set. When SIFQ6EN = 1 and SIFQ7EN = 1 and Q7 = 1, the PSM proceeds to the next state immediately , regardless of the SIFSTOP(tsm) signal and Q7 is used in the next-state calculation.
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If you have not bought Texas Instruments MSP430x4xx yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Texas Instruments MSP430x4xx - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Texas Instruments MSP430x4xx you will learn all the available features of the product, as well as information on its operation. The information that you get Texas Instruments MSP430x4xx will certainly help you make a decision on the purchase.
If you already are a holder of Texas Instruments MSP430x4xx, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Texas Instruments MSP430x4xx.
However, one of the most important roles played by the user manual is to help in solving problems with Texas Instruments MSP430x4xx. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Texas Instruments MSP430x4xx along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
