Instruction/ maintenance manual of the product ARM720T_LH79520 SMC Networks
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Summary Core Reference CR0162 (v2.0) March 10, 2008 This document provides infor mation on Altium Designer's Wishbo ne wra.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Comput er, is a term that is conventionall y us ed to describe a t.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synony mous with a weaker f eature set – a traditional trade-off. Wi th FPGA-based sy stem designs you can have the best of both worlds.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and per ipherals, each of the 32-bi t proc essors supported in Altium Design er has a Wishbone OpenBUS-based FPGA core that ' wraps' around the processor.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH795 20 in both schematic (left) and OpenBus System (right).
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Pin Description The following pin description i s for the proce ssor when used on the schematic. In an OpenB us System, althou gh the s ame signals are present, the abstract nature of the s ystem hides t he pin-level Wishbone interfaces.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Name Type Polarity/Bus size Description Peripheral I/O Interface Signals IO_STB_O O High Strobe signal. When asserted, indicates th e start of a valid W ishbone data transfer cycle IO_CYC_O O High Cycle signal.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Name Type Polarity/Bus size Description PER_RESET I Low Reset signal from the LH79520. ARM7_SYS_RESE T O Low Reset signal to the LH79520 (internall y co nnected from the RST_I line).
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Speed-critical (or latency-sens itive) parts of an application s hou ld also be placed in this memory spac e.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Memory & I/O Management The ARM720T_LH79520 us es 32-bit addres s buses prov iding a 4GBy te linear addr ess space. All memory access is in 32-bit words, which creates a physic al address bus of 30-bits.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_L H79520's addressable External Static Memory. Figure 6. Peripheral devices mapped into bank 5 (cs5) of the ARM720T_LH79520's addressabl e External Static Memory.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor • cs0 (Bank 0) – 4000_0000h to 43FF_ FFFFh • cs1 (Bank 1) – 4400_0000h to 47FF_ FFFFh The bank select signals arrive at the processor's wrapper component in the FPGA on the PER_CS bus.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor The size of the RAM can vary bet ween 1KB and 16MB, dependent on the availabilit y of embed ded block RAM in the target FPGA device used.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor clock signal (CLK_I), an ackno wledge signal fails to appear from the addressed slave peri pher al dev ice, the wait request to the ARM720T is dropped, the processor times o ut normal ly and the current data transfer cycle is forcibly terminated.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits respective l y with zeroes • for a byte load/store, the processor will sign-ext end from bit 8 • for a half-word load/store, the processor will sign-extend from bit 16.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Hardware Description For detailed information about the hardware and function alit y of the ARM720T_LH7952 0 processor, inclu.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Wishbone Communications The following sections detail the standard ha ndshaking that ta kes place when the processor communicat es to a slave peripheral or memory device connected to the relev ant Wishbone interface port.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a Wishbone-compliant memory device or me mor y controller (Wishbone Slave) in accordance with the standard Wishbone dat a transfe r hands haking protocol.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79 520 is placed and wired within an FPGA design depends on th e method used to build that design.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Design Featuring an OpenBus System Figure 11 illustrates identical use of the ARM720T _LH79520 within a design where the main processor system has been defined as an OpenBus System.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Figure 12. Wiring the OpenBus System-based ARM720T_ LH79520 to the physical pins of the FPGA device. For more information on the concepts and workings of the OpenBus System, refer to the article AR0144 Stream lining Processor-based FPGA design w ith the OpenBus System .
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor As the physical ARM720T processor do es not reside within an FPGA, communications bet ween the host computer and the ARM720T are carried out through the Hard D evices JT AG chain.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor • Download of the embedded c ode targeted to the discrete ARM720T device. Click on the LH79520 dev ic e in the Hard Devices chain to access the process flo w re quired to download the embedded soft ware to the processor, as illustrated below.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Figure 16. Starting an embedded code debug session. The debug environment offers the full suite of tools you would ex pect to see in order to effi ciently debug the embedded code.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Figure 17. Workspace panels offering code- specific information and controls Figure 18.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Figure 19. Accessing debug features from the processor's instrument panel The Nexus De b ugger button provides acces s t.
ARM720T_LH79520 – Sh arp LH79520 SoC with ARM720 T 32-bit RISC Processor Instruction Set The ARM7TDMI-S core processor – on which the ARM720T is bas ed – is an implement ation of t he ARM architecture v4T.
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