Instruction/ maintenance manual of the product SI5351A/B/C Silicon Laboratories
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Preliminary Rev. 0.95 8/11 Copyright © 2011 by Silicon Labo ratories Si5351A/B/C This information applies to a product under dev elopment. Its characteristics and specifications are s ubject to change without n otice.
Si5351A/B/C 2 Preliminary Rev. 0.95.
Si5351A/B/C Preliminary Rev. 0.95 3 T ABLE OF C ONTENT S Section Page 1. Electrical Specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Detailed Block Diagrams . . . . . . . . . . .
Si5351A/B/C 4 Preliminary Rev. 0.95 1. Electrical S pecifications T able 1. Recommended Operating Conditions Parameter Symbol T est Condition Min T yp Max Unit Ambient T emperature T A – 4 0 2 58 5° C Core Supply V oltage V DD 3.0 3.3 3.60 V 2.25 2.
Si5351A/B/C Preliminary Rev. 0.95 5 T able 3. AC Characteristics (V DD = 2.5 V ±10%, or 3.3 V ±10%, T A = –40 to 85 °C) Parameter Symbol T est Condition Min T yp Max Unit Power-up T ime T RDY Fro.
Si5351A/B/C 6 Preliminary Rev. 0.95 T able 5. Output Clock Characteristics (V DD = 2.5 V ±10%, or 3.3 V ±10%, T A =– 4 0 t o 8 5° C ) Parameter Symbol T est Condition Min T yp Max Units Frequency Range F CLK 0.
Si5351A/B/C Preliminary Rev. 0.95 7 T able 7. I 2 C Specifica tions (SCL,SDA) 1 Parameter Symbol T es t Co nd ition St and ard Mode 100 kbp s Fast Mode 400 kbps Unit Min Max Min Max LOW Level Input V oltage V ILI2C –0.5 0.3 x V DDI2 C –0.5 0.3 x V DDI2C 2 V HIGH Level Input V oltage V IHI2C 0.
Si5351A/B/C 8 Preliminary Rev. 0.95 T able 9. Absolute Maximum Ratings 1 Parameter Symbol T est Condition V alue Unit DC Supply V o ltage V DD_max –0.5 t o 3.8 V Input V oltage V IN_CLKIN CLKIN, SCL, SDA –0.5 to 3.8 V V IN_VC VC –0.5 to (VDD+0.3) V V IN_XA/B Pins XA, XB –0.
Si5351A/B/C Preliminary Rev. 0.95 9 2. Det ailed Block Diagrams Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices PLL B PLL A SDA SCL OSC XA XB VDDO R0 R1 CLK0 CLK1 R2 CLK2 M ult iS yn.
Si5351A/B/C 10 Preliminary Rev. 0.95 Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices OSC XA XB PLL VCXO R0 R1 CLK0 CLK1 VDDOA R2 R3 CLK2 CLK3 VDDOB R4 R5 CLK4 CLK5 VDDOC R6 R7 CLK6 CL.
Si5351A/B/C Preliminary Rev. 0.95 11 3. Functional Description The Si5351 is a ve rsatile I 2 C progr ammable clock ge nerator that is ide ally suited for repla cing crystals, crystal oscillators, VCXOs, PLLs, and buffers. A block diagram sho wing the general architecture of the Si5351 is shown in Figure 3.
Si5351A/B/C 12 Preliminary Rev. 0.95 3.1.2. Exte rnal Clock I nput (C LKIN) The external clock input is used as a clock reference for the PLLs when gene rating synchronous clock outputs. CLKIN can accept any frequency from 10 to 10 0 MHz. A divider at the input stag e limit s the PLL input frequency to 30 MHz.
Si5351A/B/C Preliminary Rev. 0.95 13 3.4. Spread S pectrum S pread spectrum can be enabl ed on any of the clock output s that use PLL A as its reference.
Si5351A/B/C 14 Preliminary Rev. 0.95 4. I 2 C Interface Many of the functions and features of th e Si5351 are controlled by reading and writing to the RAM sp ace using the I 2 C interface. The following is a list of the common features that ar e controllable through the I 2 C interface.
Si5351A/B/C Preliminary Rev. 0.95 15 Figure 9. I 2 C W rite Operation A read operation is performed in two st ages. A data writ e is used to set the register addre ss, then a data read is performed to retr ieve the data fr om the set address. A read bur st operation is also su pported.
Si5351A/B/C 16 Preliminary Rev. 0.95 5. Configuring the Si5351 The Si5351 is a highly flexible clock generato r which is entirely conf igurable through its I 2 C interface. The device’s default configuration is stored in non-vola tile memory (NVM) as shown in Figure 1 1.
Si5351A/B/C Preliminary Rev. 0.95 17 Figure 12. I 2 C Programming Proce dure Disable Out puts Set CLKx_DI S high; Reg. 3 = 0xFF Powerdown all output drivers Reg.
Si5351A/B/C 18 Preliminary Rev. 0.95 5.2. Si5351 Appl ication Examples The Si5351 is a versatile clock generator which serves a wide variety of applications. The following ex amples show how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
Si5351A/B/C Preliminary Rev . 0. 95 19 5.4. Replacing Cryst als, Cr yst al Oscillators, and VCXOs The Si5351B combines fre e-running clock generation an d a VCXO in a single packag e fo r cost sensi tive video applications. An example is shown in Figure 14.
Si5351A/B/C 20 Preliminary Rev . 0.95 5.6. Replacing a Cr ystal with a Clock The Si5351 can be driven with a clock signal through the XA i nput pin. Figure 16. Si5351 Driven by a Clock Signal 5.7. HCSL Comp atible Outputs The Si5351 can be co nfigured to suppor t HCSL comp atible swing when the VDDO of th e output pair of interest is set to 2.
Si5351A/B/C Preliminary Rev . 0. 95 21 6. Design Considerations The Si5351 is a self-cont ained clock generator that re qui res very few external component s. The following general guidelines are recommended to ensure op timum pe rforman c e. Refer to “AN55 4: Si5350/51 PCB Layout Guide” for additional layout recommendations.
Si5351A/B/C 22 Preliminary Rev . 0.95 6.6. T race Characteristics The Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default). It is recommended to configure t he trace char acteristics as shown in F igu re 18 when an output drive setting of 8 m A is used.
Si5351A/B/C Preliminary Rev . 0. 95 23 7. Register Map Summary The following is a summary of the re gister map used to read st atus, control, and configure th e Si535 1.
Si5351A/B/C 24 Preliminary Rev . 0.95 66 MS3_P3[15:8] 67 MS3_P3[7:0] 68 R3_DIV[2:0] MS3_P1[17:16] 69 MS3_P1[15:8] 70 MS3_P1[7:0] 71 MS3_P3[19:16] MS3_P2[19:16] 72 MS3_P2[15:8] 73 MS3_P2[7:0] 74 MS4_P3.
Si5351A/B/C Preliminary Rev . 0. 95 25 8. Register Descriptions Reset value = 0000 0000 Register 0. Device St atus B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name SYS_INIT LO L_B LOL_A LOS REVID[1:0] Ty p e RRRRRR R Bit Name Function 7S Y S _ I N I T System Initialization St atus.
Si5351A/B/C 26 Preliminary Rev . 0.95 Reset value = 0000 0000 Register 1. Interrupt S tatus S ticky B i t D 7 D 6 D 5 D 4 D 3D 2D 1D 0 Name SYS_INIT_STKY LOL_B_STKY LOL_A_STKY LOS_STKY Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7 SYS_INIT_STKY System Calibration St atus Sticky Bit.
Si5351A/B/C Preliminary Rev . 0. 95 27 Reset value = 0000 0000 Register 2. Interrupt St atus Mask B i t D 7 D 6 D 5 D 4 D 3D 2D 1D 0 Name SYS_INIT_MASK LOL_B_MASK LOL_A_MASK LOS_MASK Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7 SYS_INIT_MASK System Initialization S t atus Mask.
Si5351A/B/C 28 Preliminary Rev . 0.95 Reset value = 0000 0000 Reset value = 0000 0000 Register 3. Output Enable Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK7_OEB CLK6_OEB CLK5_OEB CLK4_OEB CLK3_OEB CLK2_OEB CLK1_OEB CLK0_OEB Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7:0 CLKx_OEB Output Disable for CLKx.
Si5351A/B/C Preliminary Rev . 0. 95 29 Reset value = 0000 0000 Register 15. PLL Input Source B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name PLLB_SRC PLLA_SRC Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Functi on 7:4 Reserved Leave as default. 3 PLLB_SRC Input Source Select for PLLB.
Si5351A/B/C 30 Preliminary Rev . 0.95 Reset value = 0000 0000 Register 16. CLK0 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK0_PDN MS0_INT MS0_SRC CLK0_INV CLK0_SRC[1:0] CLK0_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Funct ion 7 CLK0_PDN Clock 0 Power Down.
Si5351A/B/C Preliminary Rev . 0. 95 31 Reset value = 0000 0000 Register 17. CLK1 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK1_PDN MS1_INT MS1_SRC CLK1_INV CLK1_SRC[1:0] CLK1_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK1_PDN Clock 1 Power Down.
Si5351A/B/C 32 Preliminary Rev . 0.95 Reset value = 0000 0000 Register 18. CLK2 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK2_PDN MS2_INT MS2_SRC CLK2_INV CLK2_SRC[1:0] CLK2_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK2_PDN Clock 2 Power Down.
Si5351A/B/C Preliminary Rev . 0. 95 33 Reset value = 0000 0000 Register 19. CLK3 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK3_PDN MS3_INT MS3_SRC CLK3_INV CLK3_SRC[1:0] CLK3_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7C L K 3 _ P D N Clock 3 Pow e r Do wn .
Si5351A/B/C 34 Preliminary Rev . 0.95 Reset value = 0000 0000 Register 20. CLK4 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK4_PDN MS4_INT MS4_SRC CLK4_INV CLK4_SRC[1:0] CLK4_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK4_PDN Clock 4 Power Down.
Si5351A/B/C Preliminary Rev . 0. 95 35 Reset value = 0000 0000 Register 21. CLK5 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK5_PDN MS5_INT MS5_SRC CLK5_INV CLK5_SRC[1:0] CLK5_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK5_PDN Clock 5 Power Down.
Si5351A/B/C 36 Preliminary Rev . 0.95 Reset value = 0000 0000 Register 22. CLK6 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK6_PDN FBA_INT MS6_SRC CLK6_INV CLK6_SRC[1:0] CLK6_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK6_PDN Clock 7 Power Down.
Si5351A/B/C Preliminary Rev . 0. 95 37 Reset value = 0000 0000 Register 23. CLK7 Control B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK7_PDN FBB_INT MS7_SRC CLK7_INV CLK7_SRC[1:0] CLK7_IDRV[1:0] Ty p e R/W R/W R/W R/W R/W R/W Bit Name Function 7 CLK7_PDN Clock 7 Power Down.
Si5351A/B/C 38 Preliminary Rev . 0.95 Reset value = 0000 0000 Reset value = 0000 0000 Register 24. CLK3–0 Disable St ate B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK3_DIS_ST A TE CLK2_DIS_ST A TE CLK1_DIS_ST A TE CLK0_DIS_ST A TE Ty p e R/W R/W R/W R /W Bit Name Function 7:0 CLKx_DIS_ST A TE Clock x Disable St ate.
Si5351A/B/C Preliminary Rev . 0. 95 39 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 42 . Multisynth0 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS0_P3[15:8 ] Type R/W Bit Name Function 7:0 MS0_P 3[15:8] Multisynth0 Parameter 3.
Si5351A/B/C 40 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 44 . Multisynth0 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R0_DIV[2:0] MS0_P1[17:16] Type R/W R/ W R/W R /W R/W Bit Name Function 7 Unused 6:4 R0_DIV[2:0] R0 Output Divider .
Si5351A/B/C Preliminary Rev . 0. 95 41 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 46 . Multisynth0 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS0_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS0_P1[7:0] Multisynth0 Paramet er 1.
Si5351A/B/C 42 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 49 . Multisynth0 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS0_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS0_P2[7:0] Multisynth0 Paramet er 2.
Si5351A/B/C Preliminary Rev . 0. 95 43 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 52 . Multisynth1 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R1_DIV[2:0] MS1_P1[17:16] Type R/W R/ W R/W R /W R/W Bit Name Function 7 Unused 6:4 R1_DIV[2:0] R1 Output Divider .
Si5351A/B/C 44 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 54 . Multisynth1 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS1_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS1_P1[7:0] Multisynth1 Paramet er 1.
Si5351A/B/C Preliminary Rev . 0. 95 45 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 57 . Multisynth1 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS1_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS1_P2[7:0] Multisynth1 Paramet er 2.
Si5351A/B/C 46 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 60 . Multisynth2 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R2_DIV[2:0] M S2_P1[17:1 6] Ty p e R/W R/W R/W R/W R/W Bit Name Function 7 Unused 6:4 R2_DIV[2:0] R2 Output Divider .
Si5351A/B/C Preliminary Rev . 0. 95 47 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 62 . Multisynth2 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS2_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS2_P1[7:0] Multisynth2 Paramet er 1.
Si5351A/B/C 48 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 65 . Multisynth2 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS2_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS2_P2[7:0] Multisynth2 Paramet er 2.
Si5351A/B/C Preliminary Rev . 0. 95 49 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 68 . Multisynth3 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R3_DIV[2:0] M S3_P1[17:1 6] Ty p e R/W R/W R/W R/W R/W Bit Name Function 7 Unused 6:4 R3_DIV[2:0] R3 Output Divider .
Si5351A/B/C 50 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 70 . Multisynth3 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS3_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS3_P1[7:0] Multisynth3 Paramet er 1.
Si5351A/B/C Preliminary Rev . 0. 95 51 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 73 . Multisynth3 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS3_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS3_P2[7:0] Multisynth3 Paramet er 2.
Si5351A/B/C 52 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 76 . Multisynth4 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R4_DIV[2:0] M S4_P1[17:1 6] Ty p e R/W R/W R/W R/W R/W Bit Name Function 7 Unused 6:4 R4_DIV[2:0] R4 Output Divider .
Si5351A/B/C Preliminary Rev . 0. 95 53 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 78 . Multisynth4 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS4_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS4_P1[7:0] Multisynth4 Paramet er 1.
Si5351A/B/C 54 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 81 . Multisynth4 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS4_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS4_P2[7:0] Multisynth4 Paramet er 2.
Si5351A/B/C Preliminary Rev . 0. 95 55 Reset value = xxxx xxxx Reset value = xxxx xxxx Register 84 . Multisynth5 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R5_DIV[2:0] M S5_P1[17:1 6] Ty p e R/W R/W R/W R/W R/W Bit Name Function 7 Unused 6:4 R5_DIV[2:0] R5 Output Divider .
Si5351A/B/C 56 Preliminary Rev . 0.95 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 86 . Multisynth5 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS5_P1[7:0] Ty p e R/W Bit Name Function 7:0 MS5_P1[7:0] Multisynth5 Paramet er 1.
Si5351A/B/C Preliminary Rev . 0. 95 57 Reset value = xxxx xxxx Reset value = xxxx xxxx Reset value = xxxx xxxx Register 89 . Multisynth5 Parameters B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name MS5_P2[7:0] Ty p e R/W Bit Name Function 7:0 MS5_P2[7:0] Multisynth5 Paramet er 2.
Si5351A/B/C 58 Preliminary Rev . 0.95 Reset value = xxxx xxxx Register 92 . Clock 6 a nd 7 Out put Divider B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name R7_DIV[2:0] R6_DIV[2:0] Ty p e R/W R/W R/W R/W Bit Name Function 7 Reserved Leave as default. 6:4 R7_DIV[2:0] R7 Output Divider .
Si5351A/B/C Preliminary Rev . 0. 95 59 Reset value = 0000 0000 Reset value = 0000 0000 Reset value = 0000 0000 Register 165. CLK0 Initial Phase Offset B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK0_PHOFF[6:0] Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7 Reserved Only write 0 to this bit.
Si5351A/B/C 60 Preliminary Rev . 0.95 Reset value = 0000 0000 Reset value = 0000 0000 Reset value = 0000 0000 Register 168. CLK3 Initial Phase Offset B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name CLK3_PHOFF[6:0] Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7 Reserved Only write 0 to this bit.
Si5351A/B/C Preliminary Rev . 0. 95 61 Reset value = 0000 0000 Reset value = 1 1xx xx xx Register 177. PLL Reset B i t D 7D 6D 5D 4D 3D 2D 1D 0 Name PLLB_RST PLLA_RST Ty p e R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Function 7P L L B _ R S T PLLB_Reset.
Si5351A/B/C 62 Preliminary Rev . 0.95 9. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP) T able 10. Si5351A Pin Descriptions Pin Name Pin Number Pin T ype* Function 20-QFN 24- QSOP XA 1 6 I Input pin for external crystal. XB 2 7 I Input pin for external crystal.
Si5351A/B/C Preliminary Rev . 0. 95 63 10. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP) T able 1 1. Si5351B Pin Descriptions Pin Name Pin Number Pin T ype* Function 20-QFN 24- QSOP XA 1 6 I Inpu.
Si5351A/B/C 64 Preliminary Rev . 0.95 1 1. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP) T able 12. Si5351C Pin Descriptions Pin Name Pin Number Pin T ype* Function 20-QFN 24- QSOP XA 1 6 I Input pin for external crystal. XB 2 7 I Input pin for external crystal.
Si5351A/B/C Preliminary Rev . 0. 95 65 12. Si5351A Pin Descri ptions (10-Pin MSOP) T able 13. Si5351A 10-MSOP Pin Descriptions Pin Name Pin Number Pin T ype* Function 10-MSOP XA 2 I Input pin for external crystal. XB 3 I Input pin for external crystal.
Si5351A/B/C 66 Preliminary Rev . 0.95 13. Ordering Information Figure 19. Device Part Numbers An evaluation kit cont aining ClockBuilder Desktop sof twa re and hardware enable easy evaluatin of the Si5351A/B/C. The ordera ble part numbers for the evaluati on kits are pr ovided in F igure 20.
Si5351A/B/C Preliminary Rev . 0. 95 67 14. Package Out line (24-Pin QSOP) T able 14. 24-QSOP Package Dimensions Dimension Min Nom Max A— — 1 . 7 5 A1 0.10 — 0.2 5 b 0.19 — 0.30 c 0.1 5 — 0.25 D 8 . 5 58 . 6 58 . 7 5 E 6.00 BSC E1 3.81 3.90 3.
Si5351A/B/C 68 Preliminary Rev . 0.95 15. Package Out line (20-Pin QFN) T able 15. Package Dimensions Dimension Min Nom Max A 0 . 8 00 . 8 50 . 9 0 A1 0.00 0.02 0.05 b 0 . 1 80 . 2 50 . 3 0 D 4.00 BSC D2 2.65 2.70 2.75 e 0.50 BSC E 4.00 BSC E2 2.65 2.
Si5351A/B/C Preliminary Rev . 0. 95 69 16. Package Out line (10-Pin MSOP) T able 16. 24-QSOP Pa ckage Dimensions Dimension Min Nom Max A— — 1 . 1 0 A1 0.00 — 0.1 5 A2 0.75 0.85 0.95 b 0.17 — 0.33 c 0.0 8 — 0.23 D 3.00 BSC E 4.90 BSC E1 3.00 BSC e 0.
Si5351A/B/C 70 Preliminary Rev . 0.95 D O CUM EN T C HA NGE L IST Revision 0.1 to Revision 0.9 Updated max output freque ncy . Updated kV values in T able 3 on page 5. Updated "3.4. S pread S pectrum" on page 13. Added "5.
Si5351A/B/C Preliminary Rev . 0. 95 71 N OTES :.
Si5351A/B/C 72 Preliminary Rev . 0.95 C ONT AC T I NF ORMATION Silicon La boratories Inc. 400 West Cesar Chavez Austin, TX 78701 T el: 1+(512) 416-8500 Fax: 1+(512) 416-9669 T oll Free: 1 +(877) 444-3032 Please visit the Silicon Labs T echnical Support web page: https://www .
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If you have not bought Silicon Laboratories SI5351A/B/C yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Silicon Laboratories SI5351A/B/C - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Silicon Laboratories SI5351A/B/C you will learn all the available features of the product, as well as information on its operation. The information that you get Silicon Laboratories SI5351A/B/C will certainly help you make a decision on the purchase.
If you already are a holder of Silicon Laboratories SI5351A/B/C, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Silicon Laboratories SI5351A/B/C.
However, one of the most important roles played by the user manual is to help in solving problems with Silicon Laboratories SI5351A/B/C. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Silicon Laboratories SI5351A/B/C along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
