Instruction/ maintenance manual of the product F8278X Samsung
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S3C8275X/F8275X/C8278X /F8278X/C8274X/F8274X 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.4.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-bit CMOS Microcontroller DOCUMENT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision1.
REVISION HISTORY Revision Date Remark 0 February, 2005 Preliminary spec for internal release only. 1 April, 2005 First edition. Reviewed by Finechips. 1.1 July, 2005 Second edition. Reviewed by Finechips. 1.2 August, 2005 Third edition. Reviewed by Finechips.
REVISION DESCRIPTIONS 1. Electrical Data Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.
Descriptions of Revision 1.4 1. Smart Option Area The Figures are modified about smart option area. Those are “Figure 2-1. Program Memory Address Space” and “Figure 5-3. ROM Vector Address Area”. 2. CHAPTHER 17. Electrical Data It is changed “V DD = 2.
S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X MICROCONTROLLER iii Preface The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X microcontroller for application development.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER v Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Mi crocontro llers ....................................................................................
vi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER Table of Contents (Continued) Chapter 4 Control Registers Overview ....................................................................................................................... .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER vii Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview...............................................................................................
viii S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X MICROCONTROLLER Table of Contents (Continued) Chapter 11 Timer 1 One 16-bit Timer Mode (Tim er 1) ................................................................................................ ......
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER ix Table of Contents (Continued) Chapter 16 Embedded Flash Memory Interface Overview...........................................................................................................
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X MICROCONTROLLER xi List of Figures Figure Title Page Number Number 1-1 Block Diagram ............................................................................................................ 1 -3 1-2 S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X Pin Assignments (64-QFP-1420F ) .
xii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Figures Figure Title Page Number Number 5-1 S3C8-Series In terrupt Ty pes ..................................................................................... 5-2 5-2 S3C8275X/C8278X/C8274X In terrupt Stru cture .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X MICROCONTROLLER xiii List of Figures (Continued) Page Title Page Number Number 9-19 Port 4 High-Byte Cont rol Register (P4CONH) ........................................................... 9-15 9-20 Port 4 Low-Byte Contro l Register (P 4CONL) .
xiv S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X MICROCONTROLLER List of Figures (Concluded) Page Title Page Number Number 17-1 Stop Mode Release Timing When Init iated by an Exter nal Interr upt......................... 17-5 17-2 Stop Mode Release Timing W hen Initiated by a RESET .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xv List of Tables Table Title Page Number Number 1-1 S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X Pin Descr iptions ................. 1-6 2-1 S3C8275X Regist er Type Su mmary ................
xvi S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Tables (Continued) Table Title Page Number Number 17-1 Absolute Ma ximum Rati ngs ........................................................................................ 17-2 17-2 D.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2: Address Spaces Using the Page Pointer for RA M Clear (Page 0, Page 1) ........................................................
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X MICROCONTROLLER xix List of Register Descriptions Register Full Register Name Page Identifier Number BLDCON Battery Level Detect or Control R egister ........................................................
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X MICROCONTROLLER xxi List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with Carry ..................................................................................
xxii S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER List of Instruction Descriptions (Continued) Instruction Full Register Name Page Mnemonic Number LDC/LDE Load Memo ry ....................................................................
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microc ontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes.
PRODUCT OVERVIEW S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 - 2 FEATURES CPU • SAM88RC CPU core Memory • Program Memory(ROM) - 16K × 8 bits program memory(S3C8275X/F8275X) - 8K × 8 bits prog.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM 544/288 Byte Register File 16/8/4-Kbyte ROM 8-Bit Timer/ Counter B I/O Port 0 8-Bit Timer/ Counter A I/O Port 2 TAOUT/ P0. 4 T1CLK/P0.3 TBOUT/ P0. 5 LCD Driver SIO I/O Port 5 I/O Port 6 BUZ/P0.
PRODUCT OVERVIEW S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 - 4 PIN ASSIGNMENT SEG0/P5.7 COM0/P6.0 COM1/P6.1 COM2/P6.2 COM3/P6.3 VLC0 VLC1 VLC2 V DD V SS X OUT X IN TEST XT IN XT OUT nRESET V REG P0.0/INT0 P0.1/INT1 S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X (64-QFP-1420F) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SEG1/P5.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X PRODUCT OVERVIEW 1-5 S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X (64-LQFP-1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG17/P3.
PRODUCT OVERVIEW S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 - 6 PIN DESCRIPTIONS Table 1-1. S3C8275X/F8275X/C8278X/F8278X /C8274X/F8274X Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions P0.0 − P0.2 P0.3 P0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X PRODUCT OVERVIEW 1-7 Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions VLC0 − VLC2 − LCD power supply pins.
PRODUCT OVERVIEW S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 - 8 PIN CIRCUITS P-Channel N-Channel In V DD Figure 1-4. Pin Circuit Type A In V DD Schmitt Trigger Pull-Up Resistor Figure 1-5. Pin Circuit Type B (nRESET) V DD Output Disable Data Pull-up Resistor V DD I/O P-CH N-CH Open Drain Resistor Enable Schmitt Trigger Figure 1-6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X PRODUCT OVERVIEW 1-9 Out COM/SEG V LC0 V LC1 V LC2 Output Disable V SS Figure 1-7. Pin Circuit Type H-4 V DD Open Drain Data Output Disable 1 SEG Output Disable 2 Resistor Enable V DD Circuit Type H-4 P-CH N-CH Pull-Up Resistor I/O Figure 1-8.
PRODUCT OVERVIEW S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 - 10 V DD Data Output Disable 1 COM/SEG Outp ut Disable 2 Resis tor Enable V DD Circuit Type H-4 P-CH N-CH Pull-Up Resistor I/O Figure 1-9.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X PRODUCT OVERVIEW 1-11 V DD Data Output Disable 1 Resistor Enable V DD Circuit Type H- 4 P-CH N-CH Pull-Up Resistor I/O Open-Drain SEG Alternative Function BLDEN BLD Select To B LD Figure 1-10. Pin Circuit Type H-10 (P2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-1 2 ADDRESS SPACES OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two types of address space: • Internal program memory (ROM) • Internal register file A 16-bit address bus supports program memory operations.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-2 PROGRAM MEMORY (ROM) Program memory (ROM) stores progr am codes or table data. The S3C8275X has 16K bytes internal mask- programmable program memory, the S3C8278X has 8K bytes, the S3C8274X has 4K bytes.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-3 SMART OPTION ROM Address: 003EH LSB MSB .7 .6 .5 .4 .3 .2 .1 .0 ISP reset vector change enable/disable bit: 0 = OBP reset vector address 1 = Normal vector (address 0100H) NOTES: 1.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-4 Smart option is the ROM option for start condition of t he chip. The ROM address used by smart option is from 003CH to 003FH. The ISP of smart option (003EH) is available in the S3F8275X only.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-5 REGISTER ARCHITECTURE In the S3C8275X/C8278X/C8274X implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2 .
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-6 System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) Bank 1 System and Peripheral Control Reg.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-7 System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) Bank 1 System and Peripheral Control Reg.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-8 REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addre ssable register pages.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-9 PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1) LD PP,#00H ; Destination ← 0, Source ← 0 SRP #0C0H LD .
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-10 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E 0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-11 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8275X/C8278X/C8274X's two or one 256-by te register pages is called prime register area. Prime registers can be accessed usi ng any of the seven addressing modes (see Chapter 3, "Addressing Modes.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-12 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-13 USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-14 16-By te Contiguous work in g Register block Register File Contains 32 8-Byte Slices 0 0 0 0 0 X X X RP1 1 1 1 1 0 X X X RP0 0H (R0) 7H (R15) F0H (R0) F7H (R7) 8-Byte Slice 8-Byte Slice Figure 2-9.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-15 REGISTER ADDRESSING The S3C8-series register architecture provides an effici ent method of working register addressing that takes full advantage of shorter instruction form ats to reduce execution time.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-16 RP1 RP0 Register Pointers 00H All Addressing Modes Page 0 Indirect Register, Index ed Addressing Mode s Page 0 Register Addressing O nl.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-17 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP 1 automatically select two 8-byte r egister slices.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-18 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-19 Together they create an 8-bit register address Register pointer provides five high-order bits Address OPCODE Selects RP0 or RP1 RP1 RP0 4-bit address provides three low-order bits Figure 2-13.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-20 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to a ccess registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction addr ess must contain the value "1100B.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-21 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2-16.
ADDRESS SPA CES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2-22 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for dat a storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPA CES 2-23 Programming TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operat ions i.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetc hed for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-4 INDIRECT REGISTER ADDRESSING MODE (Continued) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory S.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-5 INDIRECT REGISTER ADDRESSING MODE (Continued) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-6 INDIRECT REGISTER ADDRESSING MODE (Concluded) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program me.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a bas e address during instruction execution in order to calculate the effective operand address (see Figure 3-7).
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-8 INDEXED ADDRESSING MODE (Continued) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB S.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-9 INDEXED ADDRESSING MODE (Concluded) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bi t memory address.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-11 DIRECT ADDRESS MODE (Continued) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3-11.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the in struction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains t he actual address of the next instruction to be executed.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X A DDRESSING MODES 3-13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value.
A DDRESSING MODES S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3-14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the inst ruction used.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-1 4 CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C 8275X/C8278X/C8274X control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-2 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Address R/W Decimal Hex Oscillator control register OSCCON 224 E0H R/W SIO c.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-3 Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Address R/W Decimal Hex LCD control Register LCON 224 E0H R/W Watch timer con.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-4 FLA GS - Sy stem Flags R egister .7 Carry Fl ag (C) .6 Zero Flag (Z) .5 Bit Identifier Reset Value Read/Writ e Bit A ddressing Mode R .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-5 BLDCON — Battery Level Detector Control Register F4H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – 0 0 0 0 0 0 Read/Write – – R/W R R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-6 BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-7 CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – 0 0 – – – Read/Write R/W – – R/W R/W – – – Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-8 CLOCON — Clock Output Control Register E8H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-9 EXTICONH — External Interrupt Control Register (High Byte) F8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-10 EXTICONL — External Interrupt Control Register (Low Byte) F9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-11 EXTIPND — External Interrupt Pending Register F7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-12 FLAGS — System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-13 FMCON — Flash Memory Control Register F0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 – – 0 Read/Write R/W R/W R/W R/W R – – R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-14 FMSECH — Flash Memory Sector Address Register (High Byte) F2H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-15 FMUSR — Flash Memory User Programming Enable Register F1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-16 IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-17 IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-18 IPR — Interrupt Priority Register FFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-19 IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-20 LCON — LCD Control Register E0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 – 0 Read/Write R/W R/W R/W R/W R/W R/W – R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-21 OSCCON — Oscillator Control Register E0H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – – 0 0 – 0 Read/Write R/W – – – R/W R/W – R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-22 P0CONH — Port 0 Control Register (High Byte) E4H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-23 P0CONL — Port 0 Control Register (Low Byte) E5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-24 P0PUR — Port 0 Pull-Up Control Register E6H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-25 P1CONH — Port 1 Control Register (High Byte) E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-26 P1CONL — Port 1 Control Register (Low Byte) E8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-27 P1PUR — Port 1 Pull-up Control Register F9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-28 P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-29 P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-30 P2PUR — Port 2 Pull-up Control Register ECH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-31 P3CONH — Port 3 Control Register (High Byte) EDH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-32 P3CONL — Port 3 Control Register (Low Byte) EEH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-33 P3PUR — Port 3 Pull-up Control Register EFH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-34 P4CONH — Port 4 Control Register (High Byte) E9H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-35 P4CONL — Port 4 Control Register (Low Byte) EAH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-36 P5CONH — Port 5 Control Register (High Byte) EBH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-37 P5CONL — Port 5 Control Register (Low Byte) ECH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-38 P6CON — Port 6 Control Register EDH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-39 PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-40 RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-41 SIOCON — SIO Control Register E1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-42 SPH — Stack Pointer (High Byte) D8H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-43 STPCON — Stop Control Register FBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-44 SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/ W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-45 TACON — Timer 1/A Control Register E6H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4-46 TBCON — Timer B Control Register E7H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER 4-47 WTCON — Watch Timer Control Register E1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors.
INTERRUPT STRUCTURE S3C 8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5-2 INTERRUPT TYPES The three components of the S3C8 in terrupt structure described before ⎯ levels, vectors, and sources ⎯ are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INTERRUPT STRUCTURE 5-3 S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE The S3C8275X/C8278X/C8274X microcontroller supports twelve interrupt sources. All twelve of the interrupt sources have a corresponding interrupt vector address.
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-4 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8275X/C8278X/C 8274X interrupt structure are stored in the vector address area of the internal 16-Kbyte ROM, 0H − 3FFFH, or 8, 4-Kbyte (see Figure 5-3).
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-5 Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority i.
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-6 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) in struction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities.
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways : globally or by specific in terrupt level and source.
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more correspondi ng peripheral control register s that let you control the interrupt generated by the related peripheral (see Table 5-3).
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-9 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5).
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels.
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-11 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt struct ure.
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-12 Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W .7 .6 .5 . 4 .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-13 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure.
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-14 INTERRUPT PENDING FUNCTION TYPES Overvi ew There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and exec uted; the other that must be cleared in the interrupt service routine.
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-15 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1".
INTERRUPT STRUCTURE S3C8275X/F8275X/ C8278X/F8278X/C8274X/F8274X 5-16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H − FFH) contains the addresses of in terrupt service routines that correspond to each level in the interrupt structure.
S3C8275X/F8275X/C8278X/F8278X/ C8274X/F8274X INTERRUPT STRUCTURE 5-17 FAST INTERRUPT PROCESSING (Continued) Two other system registers suppor t fast interrupt processing: • The instruction pointer (.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD d.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that descr ibe the current status of CPU operations. Four of these bits, FLAGS.7 − FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithm etic operation generates a carry-out from or a borrow to the bit 7 position (MSB).
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D D.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0 − 15) rb Bit (b) of working register Rn.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) − 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-11 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) − 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-12 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-13 INSTRUCTION DESCRIPTIONS This section contains detailed information and progr amming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-14 ADC — Add with carry ADC dst,src Operation: dst ← d s t + s r c + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-15 ADD — Add ADD dst,src Operation: dst ← d s t + s r c The source operand is added to the destination oper and and the sum is stored in the destination. The contents of the source are unaffected.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-16 AND — Logical AND AND dst,src Operation: dst ← d s t A N D s r c The source operand is logically ANDed with the destination operand.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-17 BAND — Bit AND BAND dst,s rc.b BAND dst.b,s rc Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit wi thin the destination without affecting any other bits in the destination.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-20 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← d s t ( 0 ) O R s r c ( b ) or dst(b) ← d s t ( b ) O R s r c ( 0 ) The specified bit of the source (or the destinati on) is logically ORed with bit zero (LSB) of the destination (or the source).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← P C + d s t The specified bit within the source operand is test ed.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← P C + d s t The specified bit within the source operand is test ed.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source).
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current contents of the program counter ar e pushed onto the top of t he stack.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0".
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-29 COM — Complement COM dst Operation: dst ← N O T d s t The contents of the destination location are co mplemented (one's complement); all "1s" are changed to "0s", and vice-versa.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subt racted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← P C + R A Ir ← I r + 1 The source operand is compared to (subtracted from ) the destination operand.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,s rc,RA Operation: If dst – src "0", PC ← P C + R A Ir ← I r + 1 The source operand is compared to (subtracted fr om) the destination operand.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-33 DA — Decimal Adjust DA dst Operation: dst ← D A d s t The destination operand is adjusted to form tw o 4-bit BCD digits following an addition or subtraction operation. For additi on (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-34 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the va lue 15 (BCD), working register R1 contains 27.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destinati on operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a singl e 16-bit value that is decremented by one.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← P C + d s t The working register being used as a counter is decremented.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system m ode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assu ming they have highest priority).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← I P + 2 This instruction is useful when implem enting threaded-code languages. The stack value is popped and loaded into the instruction pointer.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while a llowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-44 INC — Increment INC dst Operation: dst ← d s t + 1 The contents of the destinati on operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-45 INCW — Increment Word INCW dst Operation: dst ← d s t + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ I P SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← S P + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← d s t The conditional JUMP instruction tra.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-48 JR — Jump Relative JR cc, dst Operation: If cc is true, PC ← P C + d s t If the condition specified by the condition code (cc) is .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-49 LD — Load LD ds t,src Operation: dst ← src The contents of the source are loaded into the destination.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, regi ster 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-51 LDB — Load Bit LDB dst,s rc.b LDB dst.b,s rc Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the des tination.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-53 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-54 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-55 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← r r + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-56 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,s rc Operation: rr ← r r – 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← r r + 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-58 LDW — Load Word LDW dst,s rc Operation: dst ← src The contents of the source (a word) are loaded in to the destination. The contents of the source are unaffected. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← d s t × src The 8-bit destination operand (even register of t he register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair spec ified by the destination address.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-60 NEXT — Next NEXT Operation: PC ← @ I P IP ← I P + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruct ion pointer is loaded into the program counter.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-62 OR — Logical OR OR dst,src Operation: dst ← d s t O R s r c The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are una ffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-63 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← S P + 1 The contents of the location addressed by the st ack pointer are loaded into the destination. The stack pointer is then incremented by one.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in t he register file. The content s of the register file location addressed by the user stack pointer ar e loaded into the destination.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined st acks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-66 PUSH — Push To Stack PUSH src Operation: SP ← S P – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-67 PUSHUD — Push User Stack (Decrementing) PUSHUD ds t,src Operation: IR ← I R – 1 dst ← src This instruction is used to address user-defined stacks in the register file.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← I R + 1 dst ← src This instruction is used for user-defined stacks in the register file.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero , regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-70 RET — Return RET Operation: PC ← @SP SP ← S P + 2 The RET instruction is normally used to return to the previously executi ng procedure at the end of a procedure entered by a CALL instruction.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated le ft one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-72 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-74 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current val ue of the carry flag, is subtracted from the destination operand and the result is stored in the destination.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the des tination operand and the result is stored in the destination. The contents of the source are una ffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 70 4 3 Flags: C: Undefined.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-84 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the des tination operand for a logic one value.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-85 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value.
INSTRUCTION SET S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 6-86 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt o ccurs, except that DMA transfers can still take place during this wait state. The WFI status c an be released by an internal interrupt, including a fast interrupt.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F 8274X INSTRUCTION SET 6-87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← d s t X O R s r c The source operand is logically exclusive-OR ed with the destination operand and the result is stored in the destination.
S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.
CLOCK CIRCUIT S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 7-2 MAIN OSCILLATOR CIRCUITS X IN X OUT Figure 7-1. Crystal/Ceramic Oscillator (fx) X IN X OUT Figure 7-2. External Oscillator (fx) X IN X OUT R Figure 7-3. RC Oscillator (fx) SUB OSCILLATOR CIRCUITS XT IN XT OUT 32.
S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X CLOCK CIRCUIT 7-3 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: • In stop mode, the main oscillator is halted.
CLOCK CIRCUIT S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 7-4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the set 1, at address D4H.
S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X CLOCK CIRCUIT 7-5 CLOCK OUTPUT CONTROL REGISTER (CLOCON) The clock output control register, CLOCON, is locat ed in set 1 bank 1, at address E8H.
CLOCK CIRCUIT S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 7-6 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in se t 1, bank 0, at address E0H.
S3C8275X/F8275X/C8278X/F8278X/C8274X /F8274X CLOCK CIRCUIT 7-7 SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON.
CLOCK CIRCUIT S3C8275X /F8275X/C8278X/F8278X/C8274X/F8274X 7-8 STOP Control R e gister (STPCON ) FBH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB ST OP cont rol bit s: Other values = Disable STOP instruction 10100101 = Enable STOP instruction NOTE: Before execute the STO P instruction, set this STPCON register as "1010010 1B".
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-1 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at V DD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit wher e it is then synchronized wi th the CPU clock.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-2 HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral cont rol registers, and peripheral data registers following a reset operation.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-3 Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET D.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-4 Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET Register Name Mnemonic Address Bit Values After RESET D.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET and POWER-DOWN 8-5 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscilla tor stops and the supply current is reduced to less than 3 µ A.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-6 IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6F H). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the inter nal clock signal is gated away from the CPU, but all peripherals remain active.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has seven bit-programmable I/O ports, P0 − P6. Port 0 − port 5 are 8-bit ports, port 6 is 4-bit. This gives a total of 52 I/O pins.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register lo cations of all seven S3C8275X/C8278X/C8274X I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-3 PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins . Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in set 1, bank 0. P0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-4 Port 0 Control Register, High Byte (P0CONH) E4H, Set 1, Bank 0 , R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LSB P0.7/BUZ P0CONH bit-pair pin configuration settings: 00 01 10 11 Push-pull output mode Alternative function (BUZ, CLKOUT, TBOUT , TAOUT) P0.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-5 Port 0 Pull-up Control Register (P0PUR) E6H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L S B P0PUR bit configuration s ettings: 0 1 Enabl e pull- up resistor Disable pull-up resistor P0.3 P0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-6 External Interrupt Pending Register (EXT IPND) F7H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB LS B EXT IPND bit configuration settings: 0 1 Interrupt is pending (when read) No interrupt pending (when read), clear pending bit (when write) P0.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-7 PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins . Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 0. P1.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-8 Port 1 Control Register, High Byte (P1CONH) E7H, Set 1, Bank 0 , R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB P1.7/INT7 P1CONH bit-pair pin configuration settings: 00 01 10 11 Push-pull output mode Not available P1.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-9 Port 1 Pull-up Control Register (P1PUR) E9H, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L S B P1PUR bit configuration s ettings: 0 1 Enabl e pull- up resistor Disable pull-up resistor P1.3 P1.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-10 External Interrupt Control Register, Low Byte (EXTICONL) F9H, Set 1, Bank 0, R/W .7 .6 .5 .4 .
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-11 PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins . Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, Bank 0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-12 Port 2 Control Register, Low Byte (P2CONL) EBH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB P2.3/SEG28 P2CONL bit-pair pin configuration settings: 00 01 10 11 Alternative function (SEG28-SEG31/V BLDREF ) P2.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-13 PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins . Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-14 Port 3 Control Register, Low Byte (P3CONL) EEH, Set 1, Bank 0, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB P3.1/SEG22 P3.0/SEG23 P3CONL bit-pair pin configuration settings : 00 01 10 11 Alternative func tion (SEG20-SEG23) Input mode N-channel open-drain output mode Push-pull output mode P3.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-15 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins . Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location F4H in set 1, bank 0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-16 Port 4 Control Register, Lo w Byte (P4CONL) EAH, Set 1, Bank 1 , R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB P4.1/SEG14 P4.0/SEG15 P4CONH bit-pair pin configuration settings: 00 01 10 11 Push-pull output mode Alternative function (SEG12-SEG15) Input with pull-up resistor Input mode P4.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-17 PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins . Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location F5H in set 1, bank 0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9-18 Port 5 Control Register, Low Byte (P5CONL) ECH, Set 1, Bank 1, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB P5.1/SEG6 P5.0/SEG7 P5CONL bit-pair pin configuration settings : 00 01 10 11 Push-pull output mode Alternative function (SEG4-SEG7) Input with pull-up resistor Input mode P5.
S3C8275X/F8275X/C8278X/F8278X/C 8274X/F8274X I/O PORTS 9-19 PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins . Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location F6H in set 1, bank 0. P6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER 10-1 10 BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: • As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. • To signal the end of the required oscillation stabilizati on interval after a reset or a stop mode release.
BASIC TIMER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 10-2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to se lect the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable t he watchdog timer function.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER 10-3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7 − BTCON.4 to any value other than "1010B".
BASIC TIMER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 10-4 NOTE: During a power-on reset operation, the CPU is idle during the require d oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-1 11 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit ti mers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-2 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to • Enable the timer 1 operating (interval timer) • Select t.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-3 NOTE: W hen one 16-bit timer mode (TA CON. 7 <- "1": Timer 1) TACON.6 -.4 M U X 1/8 1/64 1/256 1/512 TACON.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-4 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers . Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-5 TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write addressable using Register addressing mode.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-6 Timer B Control Register (TBC ON) E7H, Set 1, Bank 1, R/W .7 .6 .5 .4 .3 .2 .1 .0 MSB L SB Timer B interrupt enable bit: 0 = Disable interrupt .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 11-7 NOTE: W hen two 8-bit timers mode (TACON.7 <- "0": Timer A) TACON.6-.4 M U X 1/8 1/64 1/256 1/512 TACON.0 TAOU T TAI NT DIV R fxt T1CLK (X IN or XT IN ) fxx BTCON.0 TACON.2 8-Bit Compara tor TADATA B uff er TADA TA R egister LSB MSB LSB MSB Match S ignal TACLR TACON.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11-8 1/8 1/64 1/256 1/512 NOTE: When tw o 8-bit timers mode (TACON.7 <- "0": Timer B ) TBCON.6- .4 M U X TBCON.0 TBINT DIV R fxt (X IN or XT IN ) fxx BTCON.0 TBCON.2 8-Bit Comparator TBDAT A Buff er TBDATA Registe r LSB MSB LSB MSB Match Signal TBC LR TBCON.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH T IMER 12-1 12 WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time meas urement and interval timing for the system clock. To start watch timer operation, set bit 1 of the wa tch timer control register, WTCON.
WATCH TIMER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F8274X 12-2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer functi on.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH T IMER 12-3 WATCH TIMER CI RCUIT DIASGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON. 6 f W /2 15 f W /2 14 f W /2 13 f W /2 7 f W /64 (0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-1 13 LCD CONTROLLER/DRIVER OVERVIEW The S3C8275X/C8278X/C8274X microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 13-2 LCD CIRCUIT DIAGRAM Data BUS Port Latch LCON LCD Disp lay RAM (200H-20FH) SEG/Port Driver LCD Voltage Controller SEG0/P5.7 SEG15/P4.0 SEG16/P3.7 SEG31/P2.0 COM/Port Driver Tim in g Controller COM3/P6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-3 LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit va lue is "0", the display is turned off.
LCD CONTROLLER/DRIVER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 13-4 LCD CONTROL REGISTER (LCON) A LCON is located in set 1, bank 1, at address E0H, and is read/write addressable using Register addressing mode. It has the following control functions.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-5 LCD VOLTAGE DIVIDING RESISTOR NOTES: 1. R = Internal LCD dividing re sistors. The resistor s can be disconnected by LCON .7. 2. R' = Ex ternal LCD dividing resistor s. S3C8275X/C8278X/C8274X LCON.
LCD CONTROLLER/DRIVER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 13-6 COMMON (COM) SIGNALS The common signal output pin selection (COM pin select ion) varies according to the selected duty cycle.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER 13-7 FR Sele ct Non-Sel ect 1 Frame COM V ss SEG V ss COM-SEG V ss V LC1, 2 V LC 0 -V LC 0 -V LC1, 2 V LC1, 2 V LC 0 V LC1, 2 V LC 0 Figure 13-7.
LCD CONTROLLER/DRIVER S3C8275X/F 8275X/C8278X/F 8278X/C8274X/F 8274X 13-8 1 Frame 01 2 31 2 V SS V SS COM0 COM1 COM3 SEG0 COM0 -SEG0 COM0 -SEG1 COM1 -SEG1 COM2 FR 03 V SS V SS V SS V SS V SS V SS V SS V SS SEG1 COM1 -SEG0 SEG1.7 x C3 SEG2.1 x C1 SEG1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIA L I/O INTERFA CE 14-1 14 SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface wi th various types of external device t hat require serial data transfer.
SERIA L I/O INTERFAC E S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 14-2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON , is located at E1H in set 1, bank 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIA L I/O INTERFA CE 14-3 SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface modul e, SIOPS, is located at E3H in set 1, bank 0.
SERIA L I/O INTERFAC E S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 14-4 SERIAL I/O TIMING DIAGRAM (SIO) SO Transmit Complete SIO INT Set SIOCON.3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI SCK Figure 14-4. Serial I/O Timing in Transmit/R eceive Mode (Tx at falling, SIOCON.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BA TTERY LEVEL DETECTOR 15-1 15 BATTERY LEVEL DETECTOR OVERVIEW The S3C8275X/C8278X/C8274X micro-controller has a built-in BLD (Battery Level Detector) circuit which allows detection of power voltage drop or external input level through software.
BA TTERY LEVEL DETECTOR S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 15-2 BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 3 of BLDCON controls to run or disable the operation of Battery Level Detector.
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-1 16 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW This chapter is only for the S3F827 5X. The S3F82 75X has an on-chip full-flash memory interna lly instead of masked ROM.
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-2 USER PROGRAM MODE This mode supports sector erase, byte programming, by te read and one p rote ctio n mode (Ha rd lock protection).
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-3 Flash Memory User Programming Enable Register The FMUSR register i s used for a safety operatio n of the flash memory. This re gister will protect undesired erase or program operation from malfunctioni ng of CPU caused by an electrical noise.
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-4 Flash Memory Sector Address Regis ters There are two sector addres s regist ers for add ressin g a se ctor to be erased.
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-5 ISP TM (ON-BOARD PROGRAMMING) SECTOR ISP TM sectors located in program memory area ca n stor e on board program software (boot p rogram code for upgrading application co de by interfacing with I/O pin).
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-6 Table 16-1. ISP Sector Size Smart Option(003EH) ISP Size Selection Bit Bit 2 Bit 1 Bit 0 Area of ISP Sector ISP Sector Size 1 x x − 0 0 0 0 100H – 1F.
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-7 SECTOR ERASE User can erase a flash memory partially by using sect or erase function only in User Program Mode. The only unit of flash memory to be erased and programmed in User Program Mode is called sector.
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-8 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FM U SR) to "10100101B". 2. Set Flash Memory Sector Address Regi ster (FMSECH/FMSECL). 3. Check user’s ID code (written by user).
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-9 PROGRAMMING A flash memory is programmed in one b yte unit after sect or erase. And for programming safety 's sa ke, must set FMSECH and FMSECL to flash memory sector value. The write operation of programming starts by 'LDC' instructio n.
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-10 PROGRAMMING TIP ⎯ Program • • SB1 LD FMUSR,#0A5H ; User Program mode enab le LD FMSECH,#17H LD FMSECL,#80H ; Set sector address (1780H − 17F.
S3F8275X EMBEDDED FLASH MEMORY INTERF ACE 16-11 READING The read operation of programmi ng sta rts by 'LDC' in structio n. The Reading Procedure in User Progr am Mode 1. Load a flash memory upper add ress into upper register of pair working register.
EMBEDDED FLASH MEMORY INTERF ACE S3F8275X 16-12 HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘011 0’ in FMCON.7 − 4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip e ra se executio n (in the tool program mode).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-1 17 ELECTRICAL DATA OVERVIEW In this chapter, S3C8275X/C8278X/C8274X electrical characteristics are presented in tables and graphs. The information is arranged in the following order: • Absolute maximum ratings • D.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-2 Table 17-1. Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Rating Unit Supply voltage V DD − − 0.3 to + 4.6 V Input voltage V I Ports 0–6 − 0.3 to V DD + 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-3 Table 17-2. D.C. Electrical Characteristics (Continued) (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-4 Table 17-2. D.C. Electrical Characteristics (Concluded) (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.0 V to 3.6 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (1) I DD1 (2) Run mode: V DD = 3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-5 Table 17-3. Data Retention Supply Voltage in Stop Mode (T A = − 25 ° C t o + 8 5 ° C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR − 2.0 − 3.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-6 Execution of STOP Instrction RESET Occurs ~ ~ V DDDR ~ ~ Stop Mode Oscillation Stabilization TIm e Normal Operating Mode Data Retention Mode t WA IT nRESET V DD 0.2 V DD 0.8 V DD NOTE: t WA I T is the same as 16 × 1/BT clock.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-7 Table 17-5. A.C. Electrical Characteristics (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-8 nRESET t RSL 0.2 V DD Figure 17-4. Input Timing for RESET t KH t KL 0.2V DD SCK t KCY 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-9 Table 17-6. Battery Lev el Detector Electrical Characteristics (T A = 25 ° C, V DD = 2.0 V to 3.6 V) Parameter Symbol Conditions Min Typ Max Unit Operating voltage of BLD V DDBLD − 2.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-10 Table 17-8. Main Oscillation Characteristics (T A = − 25 ° C t o + 8 5 ° C) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal X IN C1 X OUT Main oscillation frequency 2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-11 Table 17-10. Main Oscillation Stabilization Time (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.
ELECTRICAL DA TA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17-12 Table 17-11. Sub Oscillation Stabilization Time (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.0 V to 3.6 V) Oscillator Test Condition Min Typ Max Unit Crystal – − − 10 s External clock XT IN input high and low width (t XH , t XL ) 5 − 15 µ s t XTH t XTL V DD -0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA 17-13 2 MHz 6.25 kHz(main)/8.2 kHz(sub) 24 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.05 MHz Instruction Clock 8 MHz 4.2 MHz fx (Main/Sub oscillation frequency) 2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MECHANICA L DATA 18-1 18 MECHANICAL DATA OVERVIEW The S3C8275X/C8278X/C8274X microcontroller is currently available in a 64-pin QFP and LQFP package. 64-QFP-1420F #64 20.00 ± 0.20 23.90 ± 0.30 14.00 ± 0.20 17.
MECHANICA L DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 18-2 0.08 MAX 0.09~0.20 64-LQFP- 1010 #64 NOTE : Dimensions are in millimeters. 10.00 BSC 12.00 BSC 10.00 BSC 12.00 BSC #1 0.50 BSC 0-7 0.45~0.75 0.10 ± 0.05 1.40 ± 0.05 1.60 MAX 0.20 + 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-1 19 S3F8275X/F8278X/F8274X FLASH MCU OVERVIEW The S3F8275X/F8278X/F8274X single-chip CMOS microcontroller is the Flash MCU version of the S3C8275X/C8278X/C8274X microcontroller.
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F 8278X/C8274X/F 8274X 19-2 S3F8275X S3F8278X S3F8274X (64-QFP-1420F) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG14/P4.
S3C8275X/F8275X/C8278X/F8278X/C8274X/ F8274X S3F8275X/F8278X/F8274X FL ASH MCU 19-3 S3F8275X S3F8278X S3F8274X (64-LQFP-1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG17/P3.
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F 8278X/C8274X/F 8274X 19-4 Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function VLC1 SDAT 7 I/O Serial data pin. Output port when reading and input port when writing.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU 19-5 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP (TEST) pin of the S3F8275X/F8278X/F8274X, the Flash ROM programming mode is entered.
S3F8275X/F8278X/F8274X FL ASH MCU S3C8275X/F8275X/C8278X/ F8278X/C8274X/F8274X 19-6 Table 19-4. D.C. Electrical Characteristics (T A = − 25 ° C t o + 8 5 ° C, V DD = 2.0 V to 3.6 V) Parameter Symbol Conditions Min Ty p Max Unit Supply current (1) I DD1 (2) 8.
S3C8275X/F8275X/C8278X/F8278X/C8274X/ F8274X S3F8275X/F8278X/F8274X FL ASH MCU 19-7 2 MHz 6.25 kHz (main)/8.2 kHz(sub) 24 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) 1.05 MHz Instruction Clock 8 MHz 4.2 MHz fx (Main/Sub oscillation frequency) 2.
S3C8275X/F8275X/C8278X/ F8278X/C82 74X/F8274X DEVELOPMENT TOOLS 20-1 20 DEVELOPMENT TOOLS OVERVIEW Samsung provides a powe rful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debuggin g tools, and suppor t software.
DEVELOPMENT TOOLS S3C8275X/F 8275X/C8278X/ F8278X/C8274X/F8274X 20-2 BUS SMDS2+ RS-232C POD Probe Adapter PROM/OT P W riter Unit RAM Break/Display Unit Trac e /Ti me r U ni t SAM8 Base Unit Power Supply Unit IBM-PC AT or Compatible TB8275/8/4 Target Board EVA Chip Target Application System Figure 20-1.
S3C8275X/F8275X/C8278X/ F8278X/C82 74X/F8274X DEVELOPMENT TOOLS 20-3 TB8275/8/4 TARGET BOARD The TB8275/8/4 target board i s used fo r the S3C8 275X/C 8278X/C8274X microcontroller.
DEVELOPMENT TOOLS S3C8275X/F 8275X/C8278X/ F8278X/C8274X/F8274X 20-4 Table 20-1. Power Selection Settings for TB8275/8/ 4 "To User_V cc" Settings Opera ting Mode Comments To User_V CC Off On.
S3C8275X/F8275X/C8278X/ F8278X/C82 74X/F8274X DEVELOPMENT TOOLS 20-5 Table 20-3. Select Smart Option Source Setting for TB82 75/8/4 "Smart Option Source" Settings Opera ting Mode Comments In.
DEVELOPMENT TOOLS S3C8275X/F 8275X/C8278X/ F8278X/C8274X/F8274X 20-6 Table 20-5. Device Selection Setting s for TB8275/8/4 "Device Selection" Settings Opera ting Mode Comments S3F8278/4 S3F8.
S3C8275X/F8275X/C8278X/ F8278X/C82 74X/F8274X DEVELOPMENT TOOLS 20-7 INT7/P1 .7 SEG 30/P 2.1 SEG 28/P 2.3 SEG 26/P 2.5 SEG 24/P 2.7 SEG 22/P 3.1 SEG 20/P 3.3 SEG 18/P 3.5 SEG 16/P 3.7 SEG 14/P 4.1 SEG 12/P 4.3 SEG 10/P 4.5 SEG8/P4.7 SEG6/P5.1 SEG4/P5.
An important point after buying a device Samsung F8278X (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Samsung F8278X yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Samsung F8278X - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Samsung F8278X you will learn all the available features of the product, as well as information on its operation. The information that you get Samsung F8278X will certainly help you make a decision on the purchase.
If you already are a holder of Samsung F8278X, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Samsung F8278X.
However, one of the most important roles played by the user manual is to help in solving problems with Samsung F8278X. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Samsung F8278X along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
