Instruction/ maintenance manual of the product HD74LV2GT14A Renesas
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Rev.2.00, Oct.16. 2003, page 1 of 9 HD74LV2GT14A Triple Inverters with Schmitt-trigger Inputs / CMOS Logic Level Shifter REJ03D0141–0200Z (Previous ADE-205-6 66A (Z )) Rev.2.00 Oct.16.2003 Description The HD74LV2G T14A has t riple inve rters with Sc hmitt-t rigger inputs in an 8 pin packa ge.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 2 of 9 Outline and Article Indication • HD74LV2GT14A Lot No. Y : Year code (the last digit of year) M : Month code W : Week code Y M W T 1 4 Marking Index b.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 3 of 9 Pin Arrangement (Top view) 8V CC 1 71 Y 63 A 52 Y 1A 2 3 Y 3 2A 4 GND Absolute Maximum Ratings Item Symbol Ratings Unit Test Conditions Supply voltage range V CC –0.5 to 7.0 V Input voltage range *1 V I –0.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 4 of 9 Recommended Operating Conditions Item Symbol Min Max Unit Conditions Supply voltage range V CC 3.0 5.5 V Input voltage range V I 05 . 5 V Output voltage range V O 0V CC V —6 V CC = 3.0 to 3.6 V I OL —1 2 V CC = 4.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 5 of 9 Electrical Characteristic • Ta = –40 to 85°C Item Symbol V CC (V) * Min Typ Max Unit Test condition 3.0 — — 1.5 3.6 — — 1.6 4.5 — — 1.9 V T + 5.5 — — 2.1 3.0 0.3 — — 3.6 0.4 — — 4.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 6 of 9 Switching Characteristics • V CC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Test Conditions FROM (Input) TO (Output) — 7.5 12.5 1.0 14.5 C L = 15 pF Propagation delay time t PLH t PHL — 10.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 7 of 9 Test Circuit Pulse generator 50 Ω C L Input Output V CC L Note: C includes probe and jig capacitance.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 8 of 9 Input Output 90% Vref 10% 50% t PHL t PLH V I GND V OH V OL t r t f 90% Vref 10% 50% • Waveforms Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω . 2. The output are measured one at a time with one transition per measurement.
HD74LV2GT14A Rev.2.00, Oct.16. 2003, page 9 of 9 Package Dimensions (0.5) 1.5 ± 0.2 Package Code JEDEC JEITA Mass (reference value) TTP–8DBV 0.010 g 8 − 0.2 + 0.1 − 0.05 0.13 + 0.1 − 0.05 (0.5) 2.0 ± 0.2 (0.5) 0.7 ± 0.1 2.3 ± 0.1 3.
© 2003. Renesas Technolo gy Corp., All ri g hts reserved. Printed in Japan . Colo p hon 1.0 Keep safet y first in y our circuit desi g ns ! 1. Renesas Technolo gy Corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them.
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