Instruction/ maintenance manual of the product CP1E-E@@D@-@ Omron
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INSTRUC TIONS REFERENCE MANUAL C at. No. W4 83 -E1 -03 SYSMAC CP Serie s CP1E-E @@ D @ - @ CP1E-N @@ D @ - @ CP1E-NA @@ D @ - @ CP1E CPU Unit.
OMRO N, 2009 All rights reser ved. No part of th is publication m ay be reproduc ed, stored in a retrieval syste m, or transmitte d, in any form, or by any m eans, mechanic al, electron ic, photoco pying, recordin g, or othe rwise, without th e prior written pe rmission of OMRON.
SYSMAC CP Series CP1E-E @@ D @ - @ CP1E-N @@ D @ - @ CP1E-NA@@D@ - @ CP1E CPU Unit Instructi ons Re ference M anual Revised Decem ber 2 009.
1 CP1E CPU Unit Instructions Reference Manual(W483) Intr oduction Thank y ou f or purchasing a SYSMAC CP-series CP1E Programmable Controller . This manual conta ins info r mation required to use th e CP1E. Read this man ual completely and be sure you understand the contents bef ore attempting to use the CP1E.
2 CP1E CPU Unit Instructions Reference Manual(W483) CP1E CPU Unit Man uals Inf or mation on the CP1E CPU Units is provided in the f ollowing man uals. Ref er to the appropriate man ual f or the inf ormation that is required.
3 CP1E CPU Unit Instructions Reference Manual(W483) The CP1E CPU manuals are organized in the sections listed in the f ollo wing tables. Ref er to t he appro- priate section in the manuals as required. Manual Configuration CP1E CPU Unit Instructions Reference Man ual (Cat.
4 CP1E CPU Unit Instructions Reference Manual(W483) Section 15 Anal og I/O Functi on This section describes the built-in analog function for NA-type CPU Units. Section 16 Buil t-in Functions This section describes PID temperatur e control, cloc k functions, DM backup functions , secur ity functions.
5 CP1E CPU Unit Instructions Reference Manual(W483) Man ual Structure The f ollowing page structure a nd icons are used in this manual. Special information in this manual is classified as f ollows: P .
6 CP1E CPU Unit Instructions Reference Manual(W483) T erminology and Notation Te r m Description E-type CPU Unit A basic model of CPU Unit tha t suppor t basic control appli cations using instr uctions such as basic, mov ement, arithmetic, and comparison instructions.
7 CP1E CPU Unit Instructions Reference Manual(W483) Sections in this Man ual 1 2 3 4 1 2 3 4 Summary of Instructions A Appendices Instructions Instruction Execution Times and Number of Steps Monitorin.
8 CP1E CPU Unit Instructions Re f erence M anual(W483) CONTENTS Intr oduction .......... ................... .................. ................... ................... .......................... 1 CP1E CPU Unit M anuals .................. ............
9 CP1E CPU Unit Instructions Reference Manual(W483) CNTR/CNTRX ..... .............. .............. ................. .............. ................ .............. .............. ........ ............... ...... 2-83 CNR/CNRX ..........................
10 CP1E CPU Unit Instructions Reference Manual(W483) XOR W/XORL ....... .............. .............. ................. .............. .............. ................. .............. ...... .................... 2 -214 COM/COML ... ................. ..
11 CP1E CPU Unit Instructions Reference Manual(W483) Other Instructions ............. ................. ................ ............. ................ ................ ................ .. ........... 2-398 STC/CLC ....... ................. ..........
12 CP1E CPU Unit Instructions Reference Manual(W483) Read and Understand this Manual Please read and understand this manual bef ore using the product. Ple ase consult y our OM RON representativ e if you hav e any questions or comments.
13 CP1E CPU Unit Instructions Reference Manual(W483) Application Considerations SUITABILITY FOR USE OMRON shall not be responsib le f or conformity with any standards, codes, or regulat ions that apply to the combination of pr oducts in the customer’ s application or use of the products.
14 CP1E CPU Unit Instructions Reference Manual(W483) Disclaimers CHANGE IN SPECIFICATIONS Product specifications and accesso ries may be changed at an y time based on improv ements and other reasons. It is our practice to change model nu mbers when pub lished ratings or f eatures are changed, or when significant construction ch anges are made.
15 CP1E CPU Unit Instructions Reference Manual(W483) Safety Precautions The f ollowing notation is used in this man ual to prov ide precautions required to ensure saf e usage of a CP-series PLC. The saf ety pr ecautions that are provided are e xtremely impor tant to safe ty .
16 CP1E CPU Unit Instructions Reference Manual(W483) Be sure to sufficiently confirm the safet y at the destination when y ou transfer the program or I/O memory or perf orm proc edures to change the I/O memory . De vices connec ted to PLC outputs may incor rectly operate regardless of the operat- ing mode of the CPU Unit.
17 CP1E CPU Unit Instructions Reference Manual(W483) Progra m so that the memory area of the start ad dress is not excee ded when using a wo rd add ress or symbol for t he offset.
18 CP1E CPU Unit Instructions Reference Manual(W483) Precautions f or Safe Use Obser v e the f ollowing precauti ons when using a CP-series PLC. Handling • T o initialize the DM Area, back up the initial co ntents f or the DM Area to backup memory using one of the f ollowing methods .
19 CP1E CPU Unit Instructions Reference Manual(W483) Regulations and Standar ds SYSMA C is a registered trademark for Prog rammable Controllers made b y OMRON Corporation. CX-One is a registered tradem ark f or Progr amming Software ma de b y OMRON Corporation.
20 CP1E CPU Unit Instructions Reference Manual(W483) Related Man uals The f ollowing manuals are relat ed to the CP1E. Use them together with this manual.
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1-1 CP1E CPU Unit Instructions Reference Manual(W483) 1 This section pro vides a summar y of instructions used with a CP1E CPU Unit. 1-1 Summary of Instructions .
1 Summar y of Instr uctions 1-2 CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summar y of Instructions There are 200 types of instructions can be used by CP1E. The following table li sts the instruction s by function. Refer to the reference p ages for the detail o f each instruction.
1-3 1 Summar y of Instructions CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summary of Instructions 1 Sequence Output Instructions OUTPUT OUT - Outputs the result (e xecution condition) of the logical processing to the speci- fied bit.
1 Summar y of Instr uctions 1-4 CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructi ons END END 001 Indicates the end of a prog ram. 2-38 NO OPERA TION NOP 000 This instruction has no function. (No processing is perf or med for NOP(000 ).
1-5 1 Summar y of Instructions CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summary of Instructions 1 Comparison Instructions Sy mb ol Co m par i so n = , <> , < , <= , > , >= 300 ∼ 328 Symbol comparison instructions compare two values and create an ON e xecu- tion condition when the compa rison condition is true.
1 Summar y of Instr uctions 1-6 CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructi ons SHIFT REGISTER SFT 010 Operates a shif t register . 2-127 REVERSIBLE SHIFT REGISTER SFTR/ @SFTR 084 Creates a shift re gister that shifts data to either the right or the left.
1-7 1 Summar y of Instructions CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summary of Instructions 1 Symbol Math Instructions SIGNED BINAR Y ADD WITHOUT CARR Y +/ @+ 400 Adds 4-digit (si ngle-word) he xadecimal data and/or constant s.
1 Summar y of Instr uctions 1-8 CP1E CPU Unit Instructions Reference Manual(W483) Conv ersion Instructi ons BCD T O BINARY BIN/ @BIN 023 Conver ts BCD data to binar y d ata. 2-185 DOUBLE BCD T O DOUBLE BINAR Y BINL/ @BINL 058 Conv ert s 8-digit BCD data to 8-digit he xadecimal (32-bit binary) data.
1-9 1 Summar y of Instructions CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summary of Instructions 1 Floating-point Math Instr uc- tions FLOA TING TO 16-BIT FIX/ @FIX 450 Conv er ts a 32-bit floating-poin t value to 16-bi t signed binary data and places the result in the specified result w ord.
1 Summar y of Instr uctions 1-10 CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter and Pulse Output Instructi ons MODE CONTROL INI/ @INI 880 INI(880) is used to start and stop targe.
1-11 1 Summar y of Instructions CP1E CPU Unit Instructions Reference Manual(W483) 1-1 Summary of Instructions 1 Other Instructions SET CARR Y STC/ @STC 040 Sets the Carry F lag (CY).
1 Summar y of Instr uctions 1-12 CP1E CPU Unit Instructions Reference Manual(W483).
2-1 CP1E CPU Unit Instructions Reference Manual(W483) 2 This section describes the functi ons, operands and sample progr ams of the instruc- tions that are suppor ted by a CP1E CPU Unit. Notation and Lay out of Instruction Descriptions . . . . . . . .
2 Instructions 2-2 CP1E CPU Unit Instructions Reference Manual(W483) Notation and La y out of Instruction Descriptions Instructions are described in g roups b y function. Re fe r to Appendix A List of Instructions b y Function Code f or a list of instructions by mnemonic that lists the page nu mber in this section f o r each instru c- tion.
2-3 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Notation and Layout of Instruction Descriptions 2 Constants Constants input f or operands are given as listed belo w .
2 Instructions 2-4 CP1E CPU Unit Instructions Reference Manual(W483) Condition Flags With the CX-Programmer , the condition flags are re gistered in adv ance as glob al symbols with “P_” in front of the symbol na me.
2-5 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 Sequence Input Instructions Differentiated and Immed iate Refreshing Instructions • The LO AD , AN.
2 Instructions 2-6 CP1E CPU Unit Instructions Reference Manual(W483) Operation Timing f or I/O Instructions The f ollowing char t shows the diff er ences in the timing of instr uction operation s for a prog ram config- ured from LD and OUT .
2-7 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 LD/LD NO T LD/LD NO T Applicable Pr ogram Areas Operands Operand Specifications Flag s There are no flags aff e cted by this instruc tion.
2 Instructions 2-8 CP1E CPU Unit Instructions Reference Manual(W483) Hint • LD/LD NO T is used in the follo wing circumstances as an instruction for indicating a logical star t. 1. When directly connectin g to the bus bar . 2. When logic bloc ks are connected by AND LD or OR LD , i.
2-9 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 AND/AND NO T AND/AND NO T Applicable Pr ogram Areas Operands Operand Specifications Flag s There are no flags aff e cted by this instruc tion. Function AND AND is used fo r a nor mally open bit connected in series.
2 Instructions 2-10 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • Diff erentiate up (@) or differentiate do wn (%) can be specified f or AND . If differentiate up (@) is spec- ified, the e xecution condition is turned ON for one cycle only afte r the status of the operand bit goes from OFF to ON.
2-11 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 OR/OR NOT OR/OR NO T Applicable Pr ogram Areas Operands Operand Specifications Flag s There are no flags aff e cted by this instruc tion.
2 Instructions 2-12 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • Diff erentiate up (@) or differentiate do wn (%) can be specified f or OR. If diff erentiate up (@) is speci- fied, the e x ecution condition is tu rn ed ON f or one cycle only after the status of the operand bit goes from OFF to ON.
2-13 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 AND LD/OR LD AND LD/OR LD Applicable Pr ogram Areas Flag s There are no flags aff e cted by this instruc tion. Function Hint Instruction Mnemonic V ariations Function code Function AND LOAD AND LD --- --- T akes a logical AND between logic b locks.
2 Instructions 2-14 CP1E CPU Unit Instructions Reference Manual(W483) Precautions When a logic bl ock is connected b y AND LOAD or OR LO AD instructions, the total number of AND LOAD/OR LO AD instr uctions must match the total number of LOAD/LO AD NO T instructions minus 1.
2-15 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 AND LD/OR LD Sample pr ogram AND LD i • The AND LO AD instruction can be used repea tedly .
2 Instructions 2-16 CP1E CPU Unit Instructions Reference Manual(W483) NO T Applicable Pr ogram Areas Flags There are no flags affected by NO T(520). Function NO T(520) is placed between an e x ecutio n condition and another instruction to inv e r t the e xecution con- dition.
2-17 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Input Instructio ns 2 UP/DOWN UP/DO WN Applicable Pr ogram Areas Flag s There are no flags aff ect ed by UP(521) and DOWN(522).
2 Instructions 2-18 CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output Instructions OUT/OUT NO T Applicable Pr ogram Areas Operands Operand Specifications Flags There are no flags affected b y this instruction.
2-19 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 OUT/OUT NOT Hint • Immediate refreshin g (!) can be specified f or OUT and OUT NO T .
2 Instructions 2-20 CP1E CPU Unit Instructions Reference Manual(W483) TR Function TR bits are used to temporarily retain the ON/OFF status of ex ecution conditions in a program when progra mming in mnemonic code .
2-21 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 KEEP KEEP Applicable Pr ogram Areas Operands Operand Specifications Flag s No flags are aff e cted by KEEP(011). Function Instruction Mnemonic V ariations Function code Function KEEP KEEP !KEEP 011 Operates like a latching rela y .
2 Instructions 2-22 CP1E CPU Unit Instructions Reference Manual(W483) Hint • KEEP(011) has an immediate refreshing v ariation (!KEEP(011)). When a CPU Unit built-in output bit has been specified f or R in a !KEEP(011) instr uction, any changes to R will be refreshed when !KEEP(011) is e x ecuted and reflected immediately in the output bit.
2-23 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 KEEP • If a holding bit is used f or R, the bit status will be retained e v en during a power interruption. KEEP(011) can thus be used to program bits that will maintain status after restar ting the PLC f ollow- ing a pow er interr uption.
2 Instructions 2-24 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram Coding Note KEEP(011) is input in different orders on in ladder and mnemonic form. In ladder form, input the set input, KEEP(011), and then the reset input. In mnemo nic f or m, input the se t input, the reset input, a nd then KEEP(011).
2-25 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 DIFU DIFU Applicable Pr ogram Areas Operands Operand Specifications Flag s No flags are aff ected b y DIFU(013).
2 Instructions 2-26 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • The operation of DI FU(013) depends on the e xec ution condition f or the instr uct ion itself as well as the e x ecution condition for the program section when it is programmed in an inte rloc ked prog ram section, a jumped prog ram section, or a subr outine.
2-27 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 DIFD DIFD Applicable Pr ogram Areas Operands Operand Specifications Flag s No flags are aff ected b y DIFD(014).
2 Instructions 2-28 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • The operation of DIFD(014) will not be consistent if the same function b lock instance is e xecuted more than once in th e same cycle. • An subroutine will not be e xecuted while the input condition f or the subroutine is OFF .
2-29 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 SET/RSET SET/RSET Applicable Pr ogram Areas Operands Operand Specifications Flag s No flags are aff ected by SET and RSET .
2 Instructions 2-30 CP1E CPU Unit Instructions Reference Manual(W483) Hint • Diff erences between OUT/ OUT NO T and SET/RSET The operation of SET diff ers from that of OUT be cause the OUT instruction tur ns the operand bit OFF when its ex ecuti on condition is OFF .
2-31 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 SET A/RST A SET A/RST A Applicable Pr ogram Areas Operands Operand Specifications Flag s Funct.
2 Instructions 2-32 CP1E CPU Unit Instructions Reference Manual(W483) Hint SET A • SET A(530) can be used to tur n ON bits in data areas that are no rmally accessed by words only , such as the DM areas . RST A • RST A(531) can be used to tur n OFF bits in data areas that ar e normally accessed by words only , such as the DM areas.
2-33 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Output I nstructions 2 SETB/RSTB SETB/RSTB Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Instruction Mnemonic V ariations F unction code Function SINGLE BIT SET SETB @SETB, !SETB, !@SETB 532 SETB(532) turns ON the specified bit.
2 Instructions 2-34 CP1E CPU Unit Instructions Reference Manual(W483) Hint • Diff erences between SET/R SET and SETB(532)/RSTB(533) The instructions operate in the sa me w ay when the specified bit is in the CIO , W , H, or A Area. The SETB(532) and RSTB(53 3) instructions can contr ol bits in the DM Ar eas , unlike SET and RSET .
2-35 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 Sequence Contr ol Instructions Overview of Interloc k Instructions Interloc k Instructions The f ollowing instruction combinations can be used to interlock outputs in a program section.
2 Instructions 2-36 CP1E CPU Unit Instructions Reference Manual(W483) Differences between MILH(517) and MILR(518) Diff erentiated instru ctions (DIFU, DIFD , or instructions with a @ or % prefix) operate diff erently in inter- locks cre ated with MI LH(517) and MILR(518).
2-37 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 Differences between Interloc ks and Jumps The f ollowing tab le shows the diff erences between interlocks (c reated with IL(002)/ILC(003), MILH(517)/MILC(5 19), or MILR(518)/MI LC(519)) and jumps crea ted with JMP( 004)/JME(005).
2 Instructions 2-38 CP1E CPU Unit Instructions Reference Manual(W483) END Applicable Pr ogram Areas Flags There are no flags affected b y this instruction. Function END(001) completes the ex ec ution of a program f or t h at cycle. No instructions wr itten after END(001) will be ex ecuted.
2-39 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 NOP NOP Applicable Pr ogram Areas Flag s No flags are aff ected b y NOP(000). Function • No processing is perf or med f or NOP(000) , but this instruction can be used to set aside lines in the program where instructions will be inser ted later .
2 Instructions 2-40 CP1E CPU Unit Instructions Reference Manual(W483) IL/ILC Applicable Pr ogram Areas Flags There are no flags affected b y this instruction. Function When the e x ecution condition f or IL (002) is OFF , the outputs for a ll instructions between IL(002) and ILC(003) are interlocked.
2-41 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 IL/ILC Hint Precautions • The cycle time is not shor tened when a section of the program is inter lock ed because the inter lock ed instructions are ex ecuted internally .
2 Instructions 2-42 CP1E CPU Unit Instructions Reference Manual(W483) Operation of Differentiated Instructions If there is a diff erentia ted instruction (DIFU , DIFD , or instruction prefixed b y.
2-43 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 IL/ILC Sample pr ogram When CIO 0.00 is OFF in the right e xample, all outputs betw een IL(002) and ILC(00 3) are inte rlock ed. When CIO 0.00 is ON in the right e xample, the instructions between IL(0 02) and ILC(003) are e x ecuted nor mally .
2 Instructions 2-44 CP1E CPU Unit Instructions Reference Manual(W483) MILH/MILR/MILC Applicable Pr ogram Areas Operands N: Interloc k Number The interlock n umber must b e between 0 and 15. Ma tch the inte rlock number of the MILH(517) (or MILR(518)) instruction with the same number in t he corresponding MILC (519) instru ction.
2-45 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 MILH/MILR/MILC Function When the e x ecution condition f or MI LH(517) (or MILR(518)) with interlo.
2 Instructions 2-46 CP1E CPU Unit Instructions Reference Manual(W483) • A1 and A2 are interlocked when the Emergency Stop Button is ON . • A2 is interloc ked when Conv eyor R U N is OFF .
2-47 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 MILH/MILR/MILC Differences between MILH(517) and MILR(518) Diff erentiated instructions (DIFU, DIFD , or instructions with a @ or % prefix) oper ate differently in inter- locks created with MI LH(517) and MILR(518).
2 Instructions 2-48 CP1E CPU Unit Instructions Reference Manual(W483) Operation of Differentiated Instructions in an MILR(518) Interloc k If there is a differentiated instruction (DIFU, DI FD , or.
2-49 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 MILH/MILR/MILC Hint • The cycle time is not shor tened wh en a section of the progr am is interlocked b y MILH(517) or MILR(518) because the interlock ed instructions are ex ecuted inter nally .
2 Instructions 2-50 CP1E CPU Unit Instructions Reference Manual(W483) • If there is an ILC(003) instruction between an MILR(518) and MILC(519) pair , the ILC(003) instruction will be ignored and the full progr am section between MILR(518) and MILC(519) will be interlocked.
2-51 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 MILH/MILR/MILC • Progr am operation can be s witched more efficie ntly by using interlocks wit h MILH(517) or MILR(518).
2 Instructions 2-52 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When W0.00 and W0.01 are both ON, the instructions betw een MILH(517) with interlock n umber 0 and MILC(519) with interlock number 0 are e xecuted normally . When W0.
2-53 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 JMP/CJP/JME JMP/CJP/JME Applicable Pr ogram Areas Operands N: J ump Number The jump number must be 0000 to 007F (&0 to &127 decimal). Operand Specifications Flag s JMP/CJP JME There are no flags aff e cted by this instruc tion.
2 Instructions 2-54 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint • Because all of instru ctions between JM P(004)/CJP(510) and JME( 005) are skipped when the ex ecu- tion condition f or JMP(004 ) is OFF , the cycle time is reduced by th e total e x ecution time of the skipped instructions.
2-55 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 JMP/CJP/JME Sample pr ogram • When there are two or more JME(005) instruc- tions with the same jump number , only the instruction with the lower address will be v alid.
2 Instructions 2-56 CP1E CPU Unit Instructions Reference Manual(W483) FOR/NEXT Applicable Pr ogram Areas Operands N: Number of loops The number of loop s must be 0000 to FFFF (0 to 65,535 decimal).
2-57 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 FOR/NEXT Hint There are two w ays to repeat a program section until a giv en e xecution con dition is input. • FOR-NEXT Loop with BREAK Star t a FOR-NEXT loop with a maximum of N repetitions.
2 Instructions 2-58 CP1E CPU Unit Instructions Reference Manual(W483) • A jump instruction such as JMP(004) may be e x ecuted within a FOR-NEXT loop , but do not jump bey ond the FOR-NEXT loop .
2-59 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Sequence Control Instructions 2 BREAK BREAK Applicable Pr ogram Areas Flag s Function Precautions • A BREAK(514) instr uction cancels only one loop , so sev eral BREAK(514) instructions (the number of le vels nested) are required to escape from nested loops.
2 Instructions 2-60 CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions Refresh Methods f or Timer/Counter PV Overview There are two PV refr esh methods f or instr uction s related to timer/coun ters, “BCD” and “BINAR Y”.
2-61 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 Operating Mode Item TIM/TI MX (550) TIMH(015)/ TIMHX(551) TMHH(540)/ TMHHX(552) TTIM(087)/ TT.
2 Instructions 2-62 CP1E CPU Unit Instructions Reference Manual(W483) Example Timer and Counter Applications Example 1: Long-term Timers The f ollowing progr am e xamples show three w a ys to create long-ter m timers wit h standard TIM and CNT instructions.
2-63 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 Example 2: T wo-stage Counter When an SV higher than 999 9 is required, tw o counters can be combined as sho wn in the f ollowing e xample. In this case , two CNT instructions are combined to mak e a BCD counter with an SV of 20,000.
2 Instructions 2-64 CP1E CPU Unit Instructions Reference Manual(W483) Example 4: One-shot Bit A TIM timer can be combined with OUT or OUT NO T to control how long a particular bit is ON or OFF . In this example , CIO 2.04 will be ON for 1.5 seconds (the SV of T0001) after CIO 0.
2-65 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 2) Clock Pulse The desired ex ecution condition can be combined wit h a clock pulse to mi mic the cloc k pulse (0.1 s, 0.2 s, or 1.0 s). Timer reset method There are two methods f or resetting a timer ins truction.
2 Instructions 2-66 CP1E CPU Unit Instructions Reference Manual(W483) TIM/TIMX Applicable Pr ogram Areas Operands N: Timer Number The timer numb er must be betw een 0000 and 0255 (decimal). S: Set V alue (100-ms Units) TIM (BCD): #0 000 to #9999. TIMX (Binary): &0 to &65535 (d ecimal) or #0000 to #FFFF (he x).
2-67 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TIM/TIMX Function Hint • A TIM/TIMX(550) instruction’ s PV and Completion Flag can be refreshed in the follo wing wa ys depending on the timer number that is used.
2 Instructions 2-68 CP1E CPU Unit Instructions Reference Manual(W483) *1 If the IOM Hold Bit (A500.12) has been tur ned ON, the statu s of timer Comple tion Flags and PVs will b e maintained when the operating mode is changed. *2 The PV will be set to the SV when TIM/TIMX(550) is e x ecuted.
2-69 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TIMH/TIMHX TIMH/TIMHX Applicable Pr ogram Areas Operands N: Timer Number The timer number must be between 00 00 and 0255 (decimal).
2 Instructions 2-70 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint A TIMH(015)/TIMHX(551) instruction’ s PV and Completion Flag can be refreshed in the f ollowing wa ys depending on the timer n umber that is used. Precautions • Timer numbers are share d with other timer instructions.
2-71 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TIMH/TIMHX *1 If the IOM Hold Bit (A500.12) has be en turned ON, the status o f timer Completion Flags and PVs wil l be maintained when the operating mode is changed.
2 Instructions 2-72 CP1E CPU Unit Instructions Reference Manual(W483) TMHH/TMHHX Applicable Pr ogram Areas Operands N: Timer Number The timer must be betw een 0000 and 0015 decimal.
2-73 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TMHH/TMHHX • The setting range f or the set v alue (SV) is 0 to 9.999 s f o r TMHH(540) and 0 to 65.535 f or TMHHX(552). • The timer accuracy is -0.
2 Instructions 2-74 CP1E CPU Unit Instructions Reference Manual(W483) TTIM/TTIMX Applicable Pr ogram Areas Operands N: Timer Number The timer numb er must be betwee n 0000 to 0255 (decimal).
2-75 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TTIM/TTIMX Function Hint • T ypical timers such as TIM/TIMX(5 50) are decrementing co unters and the PV sho ws the time remain- ing until the timer times out.
2 Instructions 2-76 CP1E CPU Unit Instructions Reference Manual(W483) • When a TTIM(087)/TTIMX(555) timer is fo rced set, its Completion Flag will be turned ON and its PV will be reset to 0. When a TTIM(087)/TTIMX(555) timer is f orced reset, its Completion Flag will be turned OFF and its PV will be reset to 0.
2-77 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TIML/TIMLX TIML/TIMLX Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function LONG TIMER TIML --- 542 TIML(542)/TIMLX(553) operates a decrementing timer with units of 0.
2 Instructions 2-78 CP1E CPU Unit Instructions Reference Manual(W483) Function • TIML(542)/TIMLX(553 ) can time up to 115 da ys f or TIML(542 ) and 4,971 da ys f or TIMLX(553). • The timer accuracy is 0 to 0.01 s. Precautions • Unlike most timers, TIML(542)/ TIMLX(55 3) does not use a timer numb er .
2-79 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 TIML/TIMLX Sample pr ogram When timer input CIO 0.00 is ON in the f ollowing e xample, the timer PV (in D201 and D200) will be set to the SV (in D101 and D100) and the PV will begin counting do wn.
2 Instructions 2-80 CP1E CPU Unit Instructions Reference Manual(W483) CNT/CNTX Applicable Pr ogram Areas Operands N: Counter Number The counter number must be bet w een 0000 and 0255 (decimal).
2-81 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 CNT/CNTX Function • The setting range 0 to 9,999 f or CNT and 0 to 65,535 f or CNTX(546). Hint Precautions • Counter numbers are shared b y the CNT , CNTX(546), CNTR(0 12) and CNTRX(548) instructions.
2 Instructions 2-82 CP1E CPU Unit Instructions Reference Manual(W483) • When a CNT/CNTX(546) counter is f o rced set, its Completion Flag will be turned ON and its PV will be reset to 0000. When a CNT/CNTX(546) counter is f orced reset, its Completion Flag will be turned OFF and its PV will be set to the SV .
2-83 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 CNTR/CNTRX CNTR/CNTRX Applicable Pr ogram Areas Operands N: Counter Number The counter numb er must be betw een 0000 and 0255(decima l).
2 Instructions 2-84 CP1E CPU Unit Instructions Reference Manual(W483) Function Precautions • Counter numbers ar e shared b y the CNT , CNTX(5 46), CNTR(012) and CNTRX(548) instructions.
2-85 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 CNTR/CNTRX The add and subtract count inp uts increase/decrea se the count once when the signal rises (OFF to ON). When bo th inputs turn ON at the same time , neither increases/decreases the count.
2 Instructions 2-86 CP1E CPU Unit Instructions Reference Manual(W483) CNR/CNRX Applicable Pr ogram Areas Operands N1: First Number in Range N1 must be a timer number betwe en T000 and T255 or a coun ter number be tween C000 and C255 .
2-87 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Timer and Counter Instructions 2 CNR/CNRX Precautions • The timer/cou nter that is reset is as follo ws. • The CNR(545)/CNRX( 547) instructions do no t reset TIML(542) and TIMLX(553), beca use these tim- ers do not use timer numbers.
2 Instructions 2-88 CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instructions =, <>, <, <=, >, >= Applicable Pr ogram Areas Operands Operand Specifications Flags .
2-89 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 =, <>, <, <=, >, >= Function i Options The input comparison instr uctions can com pare signed or un signed data and they can compare one- word or doub le values .
2 Instructions 2-90 CP1E CPU Unit Instructions Reference Manual(W483) Unsigned input comparison instr uctions (i.e., instructions without the S option) can handle unsigned binar y or BCD data. Sig ned input comparison instr u ctions (i.e., instructions with the S option) handle signed binary data.
2-91 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 =DT , <>DT , <DT , <=DT , >DT , >=DT =DT, <>DT, <DT, <=DT, >DT, >=DT Applicable Pr ogram Areas Operands C: Control W or d Bits 00 to 05 of C specify whether or not the time data will be masked f or the compar ison.
2 Instructions 2-92 CP1E CPU Unit Instructions Reference Manual(W483) i Operand Specifications Flags Area W ord addresses Indirect DM addresses Constants CF Pulse bits TR bits CIO WR HR AR T C DM .
2-93 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 =DT , <>DT , <DT , <=DT , >DT , >=DT Function The time comparison instr uction compar.
2 Instructions 2-94 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • Time comparison instru ctions cannot be used as right-hand instr uctions, i.e ., another instruction must be used betw een them and the right b us bar . • E-type CP1E CPU Unit (CP1E-E - ) does not hav e the clock function.
2-95 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 CMP/CMPL CMP/CMPL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnem.
2 Instructions 2-96 CP1E CPU Unit Instructions Reference Manual(W483) The follo wing table sho ws the status of the Arithmetic Flags after execution of CMP(020). * A status of “---” indicates th at the Flag may be ON or OFF . The follo wi ng table shows the status of the Arithmetic Flags after ex ecution of CMPL(060) .
2-97 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 CMP/CMPL Precautions • Using CMP(020)Results in the Program When CMP(020)/CMPL( 060) is ex ecuted, the result is reflected in the Arithmetic Flags.
2 Instructions 2-98 CP1E CPU Unit Instructions Reference Manual(W483) CPS/CPSL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Funct.
2-99 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 CPS/CPSL The follo wing table sho ws the status of the Arit hmetic Flags after ex ecution of CPS(114). * A status of “---” indicates that the Flag ma y be ON or OFF .
2 Instructions 2-100 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • When CPS(114)/CPSL(1 15) is e x ecuted, t he result is reflected in the Ar ithmetic Flags . Control the desired output or right- hand instr uction with a bran ch from the same input condition that controls CPS(114)/CPSL(115), as shown in the f ollowing diagram.
2-101 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 TCMP TCMP Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V .
2 Instructions 2-102 CP1E CPU Unit Instructions Reference Manual(W483) Function i TCMP(085) compare s the source data (S) to each of the 16 words T through T+15 and turns ON the corre- sponding bit in word R when the data are equal. Bit n of R is tur ned ON if the content of T+n is equal to S and it is tur ned OFF if they are not equal.
2-103 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 BCMP BCMP Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V .
2 Instructions 2-104 CP1E CPU Unit Instructions Reference Manual(W483) Function BCMP(068) compares the source data (S) to the 16 ranges defi ned b y pairs of low er and upper limit values in B through B+31. The first word in each pair (B+2n) pr ovides the lower limit and the second word (B+2n+1) provides the upp er limit of r ange n (n = 0 to 15).
2-105 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 ZCP/ZCPL ZCP/ZCPL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mne.
2 Instructions 2-106 CP1E CPU Unit Instructions Reference Manual(W483) Function ZCP ZCP(088) compa res the 16-bit signed bin ar y data in CD with the range de fined by LL and UL and out- puts the result to the Greater Than, Equals, and Less Than Flags in the A uxiliar y Area.
2-107 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Comparison Instru ctions 2 ZCP/ZCPL • Do not progra m another instruction between ZCP(088)/ZCPL(11 6) and the instruction controlled b y the Arithmetic Flag because the othe r instr uction might change the status of the Arithmetic Flag.
2 Instructions 2-108 CP1E CPU Unit Instructions Reference Manual(W483) Data Mo vement Instructions MO V/MO VL/MVN Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function MO VE MO V @MOV , !MOV , !@MO V 021 T ransf ers a word of data to the specified word.
2-109 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 MO V/MOVL/MVN Function Precautions MO V(021) has an immediate refr eshing v ariation (!MO V( 021)). A CPU Unit Built -in input bits can be specified f or S and external output bits can be specified for D .
2 Instructions 2-110 CP1E CPU Unit Instructions Reference Manual(W483) When CIO 0.00 is ON in the follo wing example , th e content of D101 and D1 00 are copied to D201 a nd D200. When CIO 0.00 is ON in the f ollowing e xample, the status of the bits in CIO 100 is inv er ted and the result is copied to D100.
2-111 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 MO VB MO VB Applicable Pr ogram Areas Operands C: Control W or d Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function MO VE BIT M O VB @MO VB 082 T ransfers the specified bit.
2 Instructions 2-112 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint The same word can be specified for both S and D to copy a bit within a w ord. Precautions The other bits in the destinat ion word are lef t unchanged. Sample pr ogram When CIO 0.
2-113 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 MO VD MO VD Applicable Pr ogram Areas Operands S: Source W or d D: Destination W ord C: Control W or.
2 Instructions 2-114 CP1E CPU Unit Instructions Reference Manual(W483) Flags Function Precautions If the number of digits being read or written exceeds the leftmost digit of S or D , MO VD(083) will wrap to the rightmost digit of the same w ord. Sample pr ogram When CIO 0.
2-115 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 XFRB XFRB Applicable Pr ogram Areas Operands C: Control W or d D: First destination W ord Note The source words and the destination words must be in the same data area respectively .
2 Instructions 2-116 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint • Up to 255 bits of data can be tr ansf erred per e x ecution of XFRB(062).
2-117 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 XFER XFER Applicable Pr ogram Areas Operands N: Number of W ords Specifies the number of wo rds to be tr ansf erred. The possible ra nge f or N is 0000 to FFFF (0 to 65,535 decimal).
2 Instructions 2-118 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint Precautions • Be sure that the sour ce words (S to S+N-1) and destination words (D to D+N-1) do not exceed the end of the data area. • Some time will be required to complete XFER(070) when a large number of words is being trans- f erred.
2-119 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 BSET BSET Applicable Pr ogram Areas Operands St: Star ting W ord Specifies the first word in the destination range . E: End W ord Specifies the last word in the destination range .
2 Instructions 2-120 CP1E CPU Unit Instructions Reference Manual(W483) Function Precautions • Some time will be required to complete BSET(071) when a large number of words is being set.
2-121 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 XCHG XCHG Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Instruction Mnemonic V ariations Function code Function D A T A EXCHANGE XCHG @XCHG 073 Exchanges the contents of the two specified wor ds.
2 Instructions 2-122 CP1E CPU Unit Instructions Reference Manual(W483) Hint Sample pr ogram T o exchange 3 or more words , use XFER(070) to tran sfer the w ords to a third s et of words (a b uff er) as shown in this diag ram. When CIO 0.00 is ON in this example, the con- tent of D100 is exchan ged with the content of D200.
2-123 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 DIST DIST Applicable Pr ogram Areas Operands Bs: Destination Base Address Of: Offset The offset can be an y value fr om 0000 to FFFF (0 to 65,535 decimal) .
2 Instructions 2-124 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint The same DIST(080) instruction can be used to distribute the source w ord to v ar ious words in the data area by cha nging the v alue of Of . Precautions Be sure that the offset does not e xceed the end of the data area, i.
2-125 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Movement Instructions 2 COLL COLL Applicable Pr ogram Areas Operands Bs: Sour ce Base Address Of: Offset The offset can be any v alu e from 0000 to FFFF (0 to 65,535 decimal).
2 Instructions 2-126 CP1E CPU Unit Instructions Reference Manual(W483) Function Hint The same COLL(081) instru ction can be used to collect data from v arious source words in the data area by cha nging the v alue of Of . Precautions Be sure that the offset does not e xceed the end of the data area, i.
2-127 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 SFT Data Shift Instructions SFT Applicable Pr ogram Areas Operands Operand Specifications Flag s Fu.
2 Instructions 2-128 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • Do not use more than one SFT(010) instructions with ov erlapping shift words. The results will not be dependab le. • St and E must be in the same data area. • The bit data shifted out of th e shift register is discarded.
2-129 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 SFTR SFTR Applicable Pr ogram Areas Operands C: Control W or d Note St and E must be in the same data area.
2 Instructions 2-130 CP1E CPU Unit Instructions Reference Manual(W483) Function Note • The above shift operations are applicable when the reset bit (bit 15 o f C) is set to OFF . • When reset (bit 15 of C) tur ns ON all bits in the shift register, from St to E will be reset (i.
2-131 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 WSFT WSFT Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Precautions • St and E must be in the same data area. • When large amounts of data are shifted, the inst ruction ex ecution time is quit e long.
2 Instructions 2-132 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When CIO 0.00 is ON, data from CIO 100 through CIO 102 will be shifted one wo rd toward E. The con- tents of W0 will be stored in CIO 100 and the contents of CIO 102 will be lost.
2-133 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 ASL ASL Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Sample pr ogram Instruction Mnemonic V ariations Function code Function ARITHMETIC SHIFT LEFT ASL @ASL 025 Shifts the contents of Wd one bit to the left.
2 Instructions 2-134 CP1E CPU Unit Instructions Reference Manual(W483) ASR Applicable Pr ogram Areas Operands Operand Specifications Flags Function Sample pr ogram Instruction Mnemonic V ariations Function code Function ARITHMETIC SHIFT RIGHT ASR @ASL 026 Shifts the contents of Wd one bit to the right.
2-135 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 ROL RO L Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Hint It is possi.
2 Instructions 2-136 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When CIO 0.00 is ON, word CIO 100 and the Carr y Flag (CY) will shift one bit to the left. The contents of CIO 100.15 will be shifted to the Carry Flag (CY) and the Carr y Flag con- tents will be shifted to CIO 100.
2-137 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 ROR RO R Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Hint It is possi.
2 Instructions 2-138 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When CIO 0.00 is ON, word CIO 100 and the Carr y Flag (CY) will shift one bit to the r ight. The contents of CIO 100.00 will be shifted to the Carr y Flag (CY) and the Carr y Flag contents will be shifted to CIO 100.
2-139 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 SLD/SRD SLD/SRD Applicable Pr ogram Areas Operands Operand Specifications Flag s Function SLD SLD(074) shifts data be tween St and E by one digit (4 bi ts) to the lef t.
2 Instructions 2-140 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram SLD When CIO 0.00 is ON, word s CIO 100 through CIO 102 will shift by one digit (4 bits) to the left. A z ero will be placed in bits 0 to 3 of word CIO 100 and the contents of bits 12 to 15 of CIO 102 will be lost.
2-141 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 NASL/NSLL NASL/NSLL Applicable Pr ogram Areas Operands C: C o n t rol wo rd Operand Specifications .
2 Instructions 2-142 CP1E CPU Unit Instructions Reference Manual(W483) Flags Function NASL NASL(580) shifts D (the shift word) by the specified number of binary bits (specifi ed in C) to the left (from the rightmost bit to the leftmost bit).
2-143 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 NASL/NSLL Sample pr ogram When CIO 0.00 is ON, The contents of CIO 100 is shifted 10 bits to the left (fro m the rightmost bit to the leftmost bit). The number of bits to shift is specified in bits 0 to 7 of word W0 (contr ol data).
2 Instructions 2-144 CP1E CPU Unit Instructions Reference Manual(W483) NASR/NSRL Applicable Pr ogram Areas Operands C : C o nt ro l wo rd Operand Specifications Instruction Mnemonic V ariations Function code Function SHIFT N-BITS RIGHT NASR @NASR 581 Shifts the specified 16 bits of word data to the r ight by the specified number of bits.
2-145 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Shift Instructions 2 NASR/NSRL Flag s Function NASR NASR(581) shifts D (the shift word) by the specified num ber of binary bits (spe cified in C) to the r ight (from the rightmost bit to the leftmost bit).
2 Instructions 2-146 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram • When CIO 0.00 is ON, CIO 100 will be shifted 10 bits to the right (from the leftmost bit to the right- most bit). The number of bits to shift is specified in bits 0 to 7 of W0.
2-147 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 + +/+ +L Increment/Decrement Instructions + +/+ +L Applicable Pr ogram Areas Operands Oper.
2 Instructions 2-148 CP1E CPU Unit Instructions Reference Manual(W483) Function Sample pr ogram Operation of + +(590)/+ +L(591) In the follo wing example, the content of D100 will be incremented b y 1 ev er y cycle as long as CIO 0.00 is ON. In the follo wing example, the content of D100 will be incremented b y 1 ev er y cycle as long as CIO 0.
2-149 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 + +/+ +L Operation of @+ +(590)/@+ +L(591) The up-diff erentiated variation is used in the f ollowing example , so the content of D100 will be incre- mented b y 1 only when CIO 0.
2 Instructions 2-150 CP1E CPU Unit Instructions Reference Manual(W483) -- / -- L Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function DECREMENT BINAR Y - - @- - 592 Decrements the 4-digit h e xadecimal content of the specified word by 1.
2-151 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 - -/- -L Function Sample pr ogram Operation of - -(592)/- -L(593) The up-diff erentiated variation is used in the f ollowing e xample, so the content of D100 will be decre- mented b y 1 only when CIO 0.
2 Instructions 2-152 CP1E CPU Unit Instructions Reference Manual(W483) Operation of @- -(592)/@- -L(593) In the follo w ing e xample, the content of D100 will be dec remented by 1 e very cycle as long as CIO 0.
2-153 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 + +B/+ +BL + +B/+ +BL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function INCREMENT BCD + +B @+ +B 594 Increments the 4-digit BCD content of the speci- fied word by 1.
2 Instructions 2-154 CP1E CPU Unit Instructions Reference Manual(W483) Function Sample pr ogram Operation of + +B(594)/+ +BL(595) In the f ollowing e xample, the BCD content of D100 will be incremented b y 1 e v er y cycle as long as CIO 0.00 is ON.
2-155 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 + +B/+ +BL Operation of @+ +B(594)/@+ +BL(595) The up-diff erentiated variation is used in the f ollowing example , so the content of D100 will be incre- mented b y 1 only when CIO 0.
2 Instructions 2-156 CP1E CPU Unit Instructions Reference Manual(W483) - -B/- -BL Applicable Pr ogram Areas Operands Operand Specifications Flags Function Instruction Mnemonic V ariations Functio n code Function DECREMENT BCD - -B @- -B 596 Decrements the 4-digit BC D content of the speci- fied word by 1.
2-157 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Increment/Decrement Instructions 2 - -B/- -BL Sample pr ogram Operation of - -B(596)/- -BL(597) In the f ollowing e xample, the BCD content of D100 will be decremented by 1 e very cyc le as long as CIO 0.
2 Instructions 2-158 CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions +/+L Applicable Pr ogram Areas Operands Operand Specifications Instruction Mnemonic V ariations Functio n code Function SIGNED BINAR Y ADD WITHOUT CARR Y + @+ 400 Adds 4-digit (single-word) hexadecimal data and/or constants.
2-159 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 +/+L Flag s Function + +(400) adds the binar y values in A u and Ad and outputs the result to R. +L +L(401) adds the binar y values in A u and Au+1 and Ad and Ad+1 and outputs the result to R.
2 Instructions 2-160 CP1E CPU Unit Instructions Reference Manual(W483) +C/+CL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function SIGNED BINAR Y ADD WITH CARR Y +C @+C 402 Adds 4-digit (single-word) he xadecimal data and/or constants with the Carr y Flag (CY).
2-161 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 +C/+CL Function +C +C(402) adds the binary values in A u, Ad, and CY and outputs the result to R. +CL +CL(403) adds the binar y values in A u and Au+1, Ad and Ad+1, and CY and outputs the result to R.
2 Instructions 2-162 CP1E CPU Unit Instructions Reference Manual(W483) +B/+BL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function BCD ADD WITHOUT CARR Y +B @+B 404 Adds 4-digit (single-word) BCD data and/or con- stants.
2-163 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 +B/+BL Function +B +B(404) adds the BCD values in A u and Ad and outputs the result to R. +BL +BL(405) adds the BCD v alues in A u and Au+1 and Ad and Ad +1 and outputs th e result to R, R+1.
2 Instructions 2-164 CP1E CPU Unit Instructions Reference Manual(W483) +BC/+BCL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function BCD ADD WITH CARR Y +BC @+BC 406 Adds 4-digit (single-word) BCD data and/or con- stants with the Carr y Fla g (CY).
2-165 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 +BC/+BCL Function +BC +BC(406) adds BCD v alue s in Au, Ad, and CY and outputs the result to R. +BCL +BCL(407) adds the BCD value s in A u and Au+1, Ad and Ad+1, and CY and out puts the result to R, R+1.
2 Instructions 2-166 CP1E CPU Unit Instructions Reference Manual(W483) –/–L Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function SIGNED BINAR Y SUBTRA CT WITHOUT CARR Y – @– 410 Subtracts 4-digit (single-word) hexadecimal data and/or constants.
2-167 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 –/–L Function – –(400) subtracts the binar y v alues in Su from Mi and outputs the result to R. Wh en the result is nega- tive , it is output to R as a 2’ s complement.
2 Instructions 2-168 CP1E CPU Unit Instructions Reference Manual(W483) Hint • 2’ s Complement A 2’ s complement is the value obtaine d b y subtracting each binary digit from 1 and adding one to the result.
2-169 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 –/–L Subtraction at (1) Subtraction at (2) Final Subtraction Result Sample pr ogram If the result .
2 Instructions 2-170 CP1E CPU Unit Instructions Reference Manual(W483) –C/–CL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Fu.
2-171 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 –C/–CL Function –C –C(412) subtracts the bi nary values in Su and CY from Mi, and outputs the resu lt to R. When the result is negative , it is output to R as a 2’ s complement.
2 Instructions 2-172 CP1E CPU Unit Instructions Reference Manual(W483) –B/–BL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function BCD SUBTRACT WITHOUT CARR Y –B @–B 414 Subtracts 4-digit (single-word) BCD data and/or constants.
2-173 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 –B/–BL Function –B –B(414) subtracts the BCD v alues in Su from Mi and outputs th e result to R. If the result of the subtrac- tion is negative , the result is ou tput as a 10’ s complement.
2 Instructions 2-174 CP1E CPU Unit Instructions Reference Manual(W483) Subtraction at (1) Subtraction at (2) Final Subtraction Result Sample pr ogram If the result of the subtraction is a negative n umber (M i<Su or Mi+1, Mi <Su+1, Su ), the result is output as a 10’ s complement.
2-175 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 –BC/–BCL –BC/–BCL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruc.
2 Instructions 2-176 CP1E CPU Unit Instructions Reference Manual(W483) Function –BC –BC(416) subtracts BCD v a lues in Su and CY from Mi and outputs th e result to R.
2-177 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 */*L */*L Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function SIGNED BINAR Y MUL TIPL Y * @* 420 Multiplies 4-digit signed he xadecimal data and/or constants.
2 Instructions 2-178 CP1E CPU Unit Instructions Reference Manual(W483) Function * *(420) multiplies the sign ed binary values in Md an d Mr and outputs th e result to R, R+1. *L *L(421) multiplies the signed bi nary values in Md and Md+1 and Mr an d Mr+1 and output s the result to R, R+1, R+2, and R+3.
2-179 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 *B/*BL *B/*BL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function BCD MUL TIPL Y *B @*B 424 Multiplies 4-digit (single-word) BCD data and/or constants.
2 Instructions 2-180 CP1E CPU Unit Instructions Reference Manual(W483) Function *B *B(424) multiplies the BCD content of Md and Mr and outputs the result to R, R+1. *BL *BL(425) multiplies BCD v alues in Md and Md+1 and Mr and Mr+1 and outp uts the result to R, R+1, R+2, and R+3.
2-181 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 /, /L /, /L Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function SIGNED BINAR Y DIVIDE / @/ 4 30 Divides 4-digit (single-word) signed he xadecimal data and/or constants.
2 Instructions 2-182 CP1E CPU Unit Instructions Reference Manual(W483) Function / /(430) divides the signed bi nary (16 bit) values in Dd b y those in Dr and outputs the re sult to R, R+1. The quotient is placed in R and the remainder in R+1. Note Division of he xadecimal #8000 by #FFFF is undefined.
2-183 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Symbol Math Instructions 2 /B, /BL /B, /BL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function BCD DIVIDE /B @/B 434 Divides 4-digit (single-word) BCD data and/or con- stants.
2 Instructions 2-184 CP1E CPU Unit Instructions Reference Manual(W483) Function /B /B(434) divides the BCD content of Dd by those of Dr and outputs the quotient to R and the remainder to R+1. /BL /BL(435) divides BCD v alues in Dd and Dd+1 by those in Dr and Dr+1 and output s the quotient to R, R+1 and the remainder to R+2 , R+3.
2-185 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 BIN/BINL Con ver sion Instructions BIN/BINL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mnemonic V ariations Function code Function BCD T O BINAR Y BIN @BIN 023 Conv er ts BCD data to binar y data.
2 Instructions 2-186 CP1E CPU Unit Instructions Reference Manual(W483) Function Sample pr ogram When CIO 0.00 is ON in the follo wing e xample, the 8-digit BCD v alue in CIO 0010 and CIO 0011 is con- verted to hexadecimal a nd stored in D200 and D201.
2-187 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 BCD/BCDL BCD/BCDL Applicable Pr ogram Areas Operands S: Source W or d (BCD)/First Sour ce W ord (BCDL) • BCD S must be between 0000 and 270F he xadecimal (0000 and 9999 decimal).
2 Instructions 2-188 CP1E CPU Unit Instructions Reference Manual(W483) Function Sample pr ogram When CIO 0.00 is ON in the f ollowing example , t he hexade cimal va lue in CIO 11 and CIO 10 is con- verted to a BCD value an d stored in D100 and D101. BCD BCD(024) conv er ts the binar y data in S to BCD data and writes the result to R.
2-189 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 NEG NEG Applicable Pr ogram Areas Operands Operand Specifications Flag s Function Hint • This operation (re versing the status of the bi ts and adding 1) is equiv alent to subtracting the content of S/S+1 and S fro m 0000/0000 0000.
2 Instructions 2-190 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When CIO 0.00 is ON in the f ollo wing e xample, NEG(160) ca lculates the 2’ s compleme nt of the content of D100 and writes the result to D200. 1 D100 2 34 ED CB = -) E D200 D CC 00 00 ED CC NEG D100 D200 0.
2-191 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 MLPX MLPX Applicable Pr ogram Areas Operands 4-to-16 bit decoder C: Control W or d Instruction Mne.
2 Instructions 2-192 CP1E CPU Unit Instructions Reference Manual(W483) 8-to-256 bit con version C : C o nt ro l W ord Operand Specifications Flags Function MLPX(076) can perf or m 4-to-16 bit or 8-to-256 bit con versions .
2-193 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 MLPX Hint Precaution 4-to-16 bit con version When two or more digits are being conv er ted, MLPX(076) will read the digits in S from r ight to left and will wrap around to the rightmost digit after the leftmost digit, if necessar y .
2 Instructions 2-194 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram 4-to-16 bit Con version When CIO 0.00 is ON in the f o llowing e xample, MLPX(076) will con vert 3 digits in S beginning with digit 1 (the second digit), as indicated by C (#0021).
2-195 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 MLPX Example of multi-digit decoding • Example of 4-to -16 bit decoding • Example of 8-to-2 56.
2 Instructions 2-196 CP1E CPU Unit Instructions Reference Manual(W483) DMPX Applicable Pr ogram Areas Operands 16-to-4 bit con version C : C o nt ro l W ord Instruction Mnemonic V ariations Functi.
2-197 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 DMPX 256-to-8 bit con version C: C o n t rol wo rd Operand Specifications Flag s Function DMPX(077) can perf or m 16-to-4 bit or 256-to-8 bit conv er sions.
2 Instructions 2-198 CP1E CPU Unit Instructions Reference Manual(W483) 256-to-8 bit Con version When the f our th (leftmo st) digit of C is 1, DMPX( 077) finds the locat ions of the leftmost (highest bit address) or rightmost (lo west bit address) ON bits in one or tw o 16-word ranges of source w ords.
2-199 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 DMPX Sample pr ogram 16-to-4 bit Con version When CIO 0.
2 Instructions 2-200 CP1E CPU Unit Instructions Reference Manual(W483) 256-to-8 bit Con version If the conv ersion data contains 000 0 hex, b u t other data is to be encoded, separate the con version b y using more than one DMPX(07 7) instructions.
2-201 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 ASC ASC Applicable Pr ogram Areas Operands DI: Digit Designator The digit designator specifies various parameters f or the conv ersion, as shown in the f ollowing dia- gram.
2 Instructions 2-202 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Flags Function Hint • The parity bit is appen ded to the data to enable detection of errors when the da ta is tr ansmitted.
2-203 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 ASC Sample pr ogram When CIO 0.00 is ON in the follo wing example, ASC(086) con ver ts three he xadeci.
2 Instructions 2-204 CP1E CPU Unit Instructions Reference Manual(W483) Pa r i t y It is possible to specify the parity of the ASCII data fo r use in error control during data transmissions. The leftmost bit of each ASCII character will be automatically adjusted for e v en, odd, or no par ity .
2-205 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 HEX HEX Applicable Pr ogram Areas Operands DI: Digit Designator The digit designator specifies various parameters f or the conv ersion, as shown in the f ollowing dia- gram.
2 Instructions 2-206 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Flags Function Hint • The parity bit is appen ded to the data to enable detection of errors when the da ta is tr ansmitted.
2-207 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 HEX Sample pr ogram When CIO 0.00 is ON in the f ollowing e xample, HEX(162) conv er ts the ASCII data in D100 and D101 according to the settings of the digit designator .
2 Instructions 2-208 CP1E CPU Unit Instructions Reference Manual(W483) Output example * Parity bit - changes according to the par ity specificati on.
2-209 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions 2 HEX Example of con ver ting multiple b ytes of ASCII code to he x Di: #0112 Di: #0030 Di: #0131 Di.
2 Instructions 2-210 CP1E CPU Unit Instructions Reference Manual(W483) Logic Instructions AND W/ANDL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function LOGICAL AND AND W @ANDW 034 T ak es the logical AND of corresponding bits in sin- gle words of word data and/or constants.
2-211 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Logic Instructions 2 AND W/ANDL Function Sample pr ogram When the e x ecution condit ion CIO 0.00 is ON, the logical AND is tak en of corresponding bits in CIO 11, CIO 10 and CIO 21, CIO 20 and the results will be output to corresponding bits in D201 and D200.
2 Instructions 2-212 CP1E CPU Unit Instructions Reference Manual(W483) OR W/OR WL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function LOGICAL OR ORW @ORW 035 T ak es the logical OR of corresponding bits in sin- gle words of word data and/or constants.
2-213 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Logic Instructions 2 ORW/OR WL Function Sample pr ogram When the e x ecution co ndition CIO 0.00 is ON, the logical OR is ta ken of corresponding bits in CIO 21, CIO 20 and CIO 31, CIO 30 and the results will be output to corresponding bits in D501 and D500.
2 Instructions 2-214 CP1E CPU Unit Instructions Reference Manual(W483) XOR W/XORL Applicable Pr ogram Areas Operands Operand Specifications Flags Instruction Mnemonic V ariations Functio n code Function EXCLUSIVE OR XORW @XORW 036 T akes the logical e xclusive OR of corresponding bits in single words of word data and/or constants.
2-215 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Logic Instructions 2 XORW/XORL Function Sample pr ogram When the e x ecution condition CIO 0.00 is ON, the logical exclusiv e OR is taken of corresponding bits in CIO 151, CIO 150 and D1001, D1000 and the results will be output to corresponding bits in D1201 and D1200.
2 Instructions 2-216 CP1E CPU Unit Instructions Reference Manual(W483) COM/COML Applicable Pr ogram Areas Operands Operand Specifications Flags Function COM COM(029) re v erses the stat us of e very specified bit in Wd.
2-217 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Logic Instructions 2 COM/COML Sample pr ogram When CIO 0.00 is ON in the follo wing e xample, the status of each bit D100 will be rev ersed. When CIO 0.00 is ON in the follo wing example , the status of each bit in D100 and D101 will be rev ers ed.
2 Instructions 2-218 CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions APR Applicable Pr ogram Areas Operands Sine Function Cosine Function Instruction Mnemonic V ariations Functio n code Function ARITHMETIC PROCESS APR @APR 069 Calculates the sine, cosine, or a linear ex trapola- tion of the source data.
2-219 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions 2 APR Linear Extrapolation Function • Linear Extrapolation (C = Da ta area addre ss) APR(069) linear extr apolation is specified when C is a word address.
2 Instructions 2-220 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Area W ord ad dresses Indirect DM addresses Constants CF Pulse bits TR bits CIO WR HR AR T C DM @DM *D.
2-221 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions 2 APR Flag s Function Operation of the Linear Extrapolation Function APR(069) processes th e input data specified in S with the f o llowing equation and th e line-segment data (X n , Y n ) specified in the table beginning at C+1.
2 Instructions 2-222 CP1E CPU Unit Instructions Reference Manual(W483) 16-bit Unsigned BCD Data The input data a nd/or the output data can be 16-bit unsigned BCD data. Also, the lin- ear e xtrapolation function ca n be set to operate on the v alue specified in S directly or on X m -S .
2-223 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions 2 APR Sample pr ogram Sine Function (C: #0000) The f ollowing e xample shows APR(069) used to calculate the sine of 30 ° .
2 Instructions 2-224 CP1E CPU Unit Instructions Reference Manual(W483) This e xample shows ho w to construct a linear extrapol ation with 12 coordinates . The bloc k of data is continuous, as it m ust be, from D0 to D26 (C to C + (2 × 12 + 2)). The input data is taken from CIO 10, and the result is output to C IO 11.
2-225 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions 2 APR • Using 32-bit Sign ed Binar y Data In this e x ample , APR(069) is used to con vert the fluid height i n a tank to flui d volume based on the shape of the holding tank.
2 Instructions 2-226 CP1E CPU Unit Instructions Reference Manual(W483) • Using Floating-point Data In this exa mple, APR(069) is used to con vert the flui d height in a tank to fl uid v olume based on the shape of the holding tank.
2-227 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Special Math Instructions 2 BCNT BCNT Applicable Pr ogram Areas Operands N: Number of words The number of words m ust be 0001 to FFFF (1 to 65,535 words).
2 Instructions 2-228 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • Some time will be required to complete BCNT(067) if a large n umber of words is specified.
2-229 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 Floating-point Math Instructions The Floating-point Math Instr uctio ns conv er t data and perf or m flo ating-point ar ithmetic operations. Data Format Floating-point data expresses re al numbers using a sign, e xponent, and mant issa.
2 Instructions 2-230 CP1E CPU Unit Instructions Reference Manual(W483) Writing Floating-point Data When floating-point is spe cified f or the data f or mat in the I/O memor y edit displa y in the .
2-231 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 (2) Non-normalized Numbers Non-nor malized numbers e xpress real numbers with very small absolute values. The sign bit will be 0 f or a positiv e number and 1 f or a negativ e number .
2 Instructions 2-232 CP1E CPU Unit Instructions Reference Manual(W483) (3) Precautions in Handling Special V alues The f ollowing precautions apply to handling zero , infinity , and NaN. • The sum of positiv e zero and ne gativ e zero is positiv e zero .
2-233 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FIX/FIXL FIX/FIXL Applicable Pr ogram Areas Operands Operand Specifications Flag s Instru.
2 Instructions 2-234 CP1E CPU Unit Instructions Reference Manual(W483) Function FIX FIX(450) con v er ts the integer por tion of the 32-bit floating-poin t number in S+1 and S (IEEE7 54-f ormat) to 16-bit signed binar y data and places the result in R .
2-235 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FL T/FL TL FL T/FL TL Applicable Pr ogram Areas Operands Operand Specifications Flag s In.
2 Instructions 2-236 CP1E CPU Unit Instructions Reference Manual(W483) Function FL T FL T(452) converts the 16-bit signed binar y v alue in S to 32-bit floating-point data (IEEE754-format) and places the result in R+1 and R. A single 0 is added after the decimal point in the floatin g-point result.
2-237 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 +F , –F , *F , /F +F , –F , *F , /F Applicable Pr ogram Areas Operands Operand Specif.
2 Instructions 2-238 CP1E CPU Unit Instructions Reference Manual(W483) Flags Function The data specified in A u/Mi/Md/Dd and the data sp ecified in AD/Su/Mr/ Dr are added (+F), subtracted (-F), multiplied (*F), or divided (/F) as single-precision floating-point data (32 bits: IEEE754) and output to R+1, R.
2-239 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 +F , –F , *F , /F *F /F • If the absolute value of the result is greater than th e maximum value that can be e xpressed as float- ing-point data, the Overflo w Flag will tur n ON and the result will be output as ±∞ .
2 Instructions 2-240 CP1E CPU Unit Instructions Reference Manual(W483) FLO A TING-POINT MUL TIPL Y (*F) Note 1 The results could be zero (including underflo ws), a numeral, + ∞ , or – ∞ . ER The Error Flag will be tur ned ON and the instr uction will not be ex ecuted.
2-241 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 =F , <>F , <F , <=F , >F , >=F =F , <>F , <F , <=F , >F , &g.
2 Instructions 2-242 CP1E CPU Unit Instructions Reference Manual(W483) Function Options With the three input types and six symbols, there are 18 different possib le combinations.
2-243 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 =F , <>F , <F , <=F , >F , >=F Precautions • Input comparison instr uctions cannot be used as ri ght-hand instr uctions, i.e .
2 Instructions 2-244 CP1E CPU Unit Instructions Reference Manual(W483) FSTR Applicable Pr ogram Areas Operands C: First Contr ol W ord Operand Specifications Flags Instruction Mnemonic V ariations.
2-245 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FSTR Function FSTR(448) e xpresses the 32- bit floating-point nu mber in S+1 and S (IEEE754-f.
2 Instructions 2-246 CP1E CPU Unit Instructions Reference Manual(W483) Storage of ASCII T ext After the floating-point nu mber is con v er ted to ASCII text, the ASCII characters are stored in the desti- nation words beginning with D , as shown in the follo wing dia grams .
2-247 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FSTR • Limits on the Number of Digits in the Integer P ar t 1) Decimal Notation (C = 0 hex).
2 Instructions 2-248 CP1E CPU Unit Instructions Reference Manual(W483) Con ver ting to ASCII T e xt in Scientific Notation When CIO 0.00 is ON in the follo wing e xample, FSTR(448) con v er ts the floating-point data in D1 and D0 to scientific-notat ion ASCII te xt and writes the ASCII te xt to t he destination words beginning with D100.
2-249 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FV AL FV AL Applicable Pr ogram Areas Operands Operand Specifications Flag s Function FV .
2 Instructions 2-250 CP1E CPU Unit Instructions Reference Manual(W483) • Scientific Notation Real numbers e xpressed as an in teger par t, fractional pa r t, and exponent par t. Example: 1.2456E-2 (1.2 456 × 10 - 2 ) The data f or mat (decimal or scientific notation) is detected automatically .
2-251 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Floating-po int Math Instructions 2 FV AL Storage of ASCII T ext The f ollowing diagrams show ho w the ASCII text nu mber is conv er ted to floating-point data. Different conv ersion methods are used f or numbers stored with decimal notation and scientific notation.
2 Instructions 2-252 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram Con ver ting ASCII T ext in Decimal Notation to Floating-point Data When CIO 0.
2-253 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) T able Data Processing Instructions 2 SW AP T able Data Pr ocessing Instructions SW AP Applicable Pr ogram Areas Operands N: Number of w ords N specifies the number of w ord s in the range and must be 0001 to FFFF he xadecimal (or &1 to &65,535).
2 Instructions 2-254 CP1E CPU Unit Instructions Reference Manual(W483) Function SW AP (637) s witches the position of the two bytes in all of the wo rds in the range of mem- or y from R1 to R1+N-1. Hint • This instruction can be used to rev erse the or der of ASCII-code charac ters in each word.
2-255 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) T able Data Processing Instructions 2 FCS FCS Applicable Pr ogram Areas Operands Operand Specifications Flag s Instruction Mn.
2 Instructions 2-256 CP1E CPU Unit Instructions Reference Manual(W483) Function FCS(180) calculat es the FCS v alue f or W units of data beginning with the data in R1, con verts the v alue to ASCII code, and outputs the result to D (f or bytes) or D+1 and D (f or words).
2-257 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T Data Contr ol Instructions PID A T Applicable Pr ogram Areas Operands C: First P arameter W o.
2 Instructions 2-258 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Flags Function When the e x ecution condit ion is ON, PID A T(191) carries out target value filtered PID co ntrol with two degrees of freedom according to the parameters designated b y C (set value , PID constant, etc.
2-259 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T The f ollowing flo wchar t show s the autot uning procedure: Note 1 If autotuning is interrup.
2 Instructions 2-260 CP1E CPU Unit Instructions Reference Manual(W483) Hint • PID A T(191) is ex ecuted as if the ex ecution co ndition was a ST OP-R UN signal. PID calculations are e xecuted when the e xecution condit ion remains ON for the ne xt cycle after C+11 to C+40 are initial- ized.
2-261 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T Bloc k Diagram f or T arget V alue PID with T w o Degrees of Freedom When ov ershooting is prev ented with simple PID control, stabilization of disturbances is slo wed (1).
2 Instructions 2-262 CP1E CPU Unit Instructions Reference Manual(W483) Note 1 When the unit is designate d as 1, the range is from 1 to 8,191 times the per iod.
2-263 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T Sampling P eriod and Cycle Time The sampling period can be designated in units of 10 ms (0.
2 Instructions 2-264 CP1E CPU Unit Instructions Reference Manual(W483) PID contr ol Proportional Action (P) Propor tional action is an op eration in which a proportional band is es tablished with re spect to the set value (SV), and within that band the manipulat ed variab le (MV) is made pr opor tional to the de viation.
2-265 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T Deriv ative Action (D) Propor tional action and integral ac tion both mak e corrections with respect to the co ntrol results, so there is ine vitably a respon se dela y .
2 Instructions 2-266 CP1E CPU Unit Instructions Reference Manual(W483) Direction of Action When using PID control, select either of the f ollo wing two control directions . In either direction, the MV increases as the diff erence between the SV and th e PV increases.
2-267 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 PID A T Sample pr ogram Interrupting PID Contr ol to P erform A utotuning • At the rising edge of CIO 0.00 (OFF to ON), the wor k area in D211 to D240 is initialized according to the para meters (sho wn below) set in D200 to D208.
2 Instructions 2-268 CP1E CPU Unit Instructions Reference Manual(W483) Starting PID A T(191) with A utotuning Interrupting A utotuning Bef ore Completion A utotuning can be interrupted by turning bit 15 of D209 (C+9) from ON to OFF .
2-269 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 TPO TPO Applicable Pr ogram Areas Operands S: Input W ord Specifies the input word cont aining the input duty r atio or manipulated v ariable. • Input duty ratio: 000 0 to 2710 he x (0.
2 Instructions 2-270 CP1E CPU Unit Instructions Reference Manual(W483) R: Pulse Output Bit Specifies the destination output bit for the pulse output. Nor mally , specify an output bit allocated t o a T r ansistor Output Unit and connect a solid state rela y to the T ransistor Output Unit.
2-271 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 TPO In this case, set the same v a lue f o r the PID Control instruction’ s outp ut range and the TPO(685) instruc- tion’ s manipulated variab le range.
2 Instructions 2-272 CP1E CPU Unit Instructions Reference Manual(W483) • The parameters (in C to C+3) are read in real time each ti me that the instru ction is e x ecuted. When changing the par ameters , change all of them at the same time so that diff erent sets of par ameters are not mixed.
2-273 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 TPO • Input time setting = 2 (Use highe r valu e.) • Input time setting = 3 ( Continuous adjustme.
2 Instructions 2-274 CP1E CPU Unit Instructions Reference Manual(W483) Precautions When using TPO(685) in combination with PID A T(191) in a cyclic task and also using an interrupt ta s k, temporarily disable interrupts by e x ecuting DI(693) (DISABLE INTERRUPTS) ahead PID A T(191) and TPO(685).
2-275 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 TPO Using TPO(685) Alone When CIO 0.00 is ON, TPO(685) tak es the duty ratio in D10, con v er ts the duty ratio to a tim e-propor- tional output, and outputs the pulses to bit 00 of CIO 100.
2 Instructions 2-276 CP1E CPU Unit Instructions Reference Manual(W483) SCL Applicable Pr ogram Areas Operands P1: First P arameter W ord Operand Specifications Instruction Mnemonic V ariations Functio n code Function SCALING SCL @SCL 194 Converts unsigned b inary d ata into unsigned BCD data according to the specified linear function.
2-277 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 SCL Flag s Function SCL(194) is used to conv er t the unsigned binar y data contained in the source word S into unsigned BCD data and place the result in the result w ord R according to the linear function defined by points (As, Ar) and (Bs , Br).
2 Instructions 2-278 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram In the f ollowing e xample, it is assume that an analog signal from 1 to 5 V is conv er ted and input to D0 as 0000 to 0F A0 hexadecimal. SCL(1 94) is used to conv er t (scale) th e v alue in CIO 200 to a v alue between 0 and 300 BCD .
2-279 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 SCL In this e xample, v alues from 0000 to 00C8 he xadecimal will be con verted to negative v alues . SCL(194), how ev er , can output only unsigned BCD values from 0000 to 9999, so 0000 BCD will be output when- e ve r the contents of D0.
2 Instructions 2-280 CP1E CPU Unit Instructions Reference Manual(W483) SCL2 Applicable Pr ogram Areas Operands P1: First P arameter W ord Operand Specifications Instruction Mnemonic V ariations Functio n code Function SCALING 2 SCL2 @SCL2 486 Conv er ts signed binar y data into signed BCD data according to the specified linear function.
2-281 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 SCL2 Flag s Function SCL2(486) is used to conv er t the signed binary dat a contained in the sour ce .
2 Instructions 2-282 CP1E CPU Unit Instructions Reference Manual(W483) Hint • SCL2(486) can be used to scale the results of an alog signal conv ersion values from Analog Input Units according to user -defined scale para meters .
2-283 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 SCL2 Scaling 1 to 5-V Analog Input to –200 to 200 In the f ollowing e xample, it is assume that an analog signal from 1 to 5 V is con verted and input to CIO 3 as 0000 to 1770 he xadecimal.
2 Instructions 2-284 CP1E CPU Unit Instructions Reference Manual(W483) SCL3 Applicable Pr ogram Areas Operands P1: First P arameter W ord Instruction Mnemonic V ariations Functio n code Function SCALING 3 SCL3 @SCL3 487 Conv er ts signed BCD data into signed binar y data according to the specified linear function.
2-285 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 SCL3 Operand Specifications Flag s Function SCL3(487) is used to con v er t the signe d BCD data .
2 Instructions 2-286 CP1E CPU Unit Instructions Reference Manual(W483) Hint SCL3(487) is used to con v er t data using a user-defined scale to signed binary f or Analog Output Units . F or e xample, SCL3( 487) can con ve r t 0 to 200 ° C to 0000 to 1770 (he x) and output an analog outpu t signal 1 to 5 V from the Analog Output Unit.
2-287 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 A VG AV G Applicable Pr ogram Areas Operands N: Number of Cycles The number of cycles must be between 0001 and 0040 he xadecimal (0 to 64 cycles). R: Result First W ord and R+1: Fir st W ork Area W or d Note R to R+N+1 must be in the same area.
2 Instructions 2-288 CP1E CPU Unit Instructions Reference Manual(W483) Function Precautions The processing inf or mation (R+1) is cleared to 0000 each time the e x ecution condition changes from OFF to ON. But the processing inf or mation (R+1) will not be cleared to 0000 the first time the program is e xecuted at the star t of operation.
2-289 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Data Control Instructions 2 A VG • In the f ollowing e xample, the content of CIO 40 is set to #0000 a nd then incremented by 1 each cycle . • F or the first two cycles, A V G(195) move s the content of CIO 4 0 to D1002 and D1003.
2 Instructions 2-290 CP1E CPU Unit Instructions Reference Manual(W483) Subr outines Instructions SBS Applicable Pr ogram Areas Operands N: Subr outine number Specifies the subroutine number betw een 0 and 127 decimal.
2-291 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Subroutines Instructions 2 SBS Function SBS(091) calls the subroutine with the specified subroutin e number . The subrou- tine is the progra m section between SBN(092) and RET(09 3).
2 Instructions 2-292 CP1E CPU Unit Instructions Reference Manual(W483) Precautions • The subroutine n umber must be uni que f or each subroutine . Y ou cannot use the same numb er f or more than one sub- routine. • Each subroutine must hav e a unique subroutine number .
2-293 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Subroutines Instructions 2 SBS Sample pr ogram Sequential (Non-nested) Subr outines When CIO 0.00 is ON in the f o llowing e xample, subroutine 1 is e xecuted and progr am e x ecution retur ns to the ne xt instruction after SBS(091) 1.
2 Instructions 2-294 CP1E CPU Unit Instructions Reference Manual(W483) Nested Subroutines When CIO 0.00 is ON in the f ollo wing e xample, subroutine 1 is e xecuted . If CIO 0.01 is ON, subroutine 2 is e x ecuted from within su broutine 1 and program e xecution returns to the next instruction after SBS(091) 2 when subrou tine 2 is completed.
2-295 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Subroutines Instructions 2 SBN/RET SBN/RET Applicable Pr ogram Areas SBN RET Operands SBN N: Subroutine number Specifies the subroutin e number between 0 and 127 decimal.
2 Instructions 2-296 CP1E CPU Unit Instructions Reference Manual(W483) Flags SBN/RET There are no flags affected b y this instruction. Function SBN RET When progr am ex ecution reaches RET( 093), it is automatically retur ned to the ne xt instruction after the SBS(091) instruction that called the subroutine.
2-297 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Subroutines Instructions 2 SBN/RET • The step instructions, STEP(008 ) and SNXT(009) cannot be used in subroutines. • Place the subroutines after the main progr am and just befo re the END(001) instruction in the program f or each task.
2 Instructions 2-298 CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Contr ol Instructions CP1E CPU Units suppor t the f ollowing interrupts. Outline of Interrupt Contr ol Instructions SET INTERR UPT MASK: MSKS(690) Both I/O interrupt tasks and sche duled interrupt tasks are masked (disab led) when the PLC enters R UN mode.
2-299 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Control Instructions 2 Related Memory Area W ords Name Address Operation Maximum Interrupt T ask Processing Time A440 The maximum processing time f or an interrupt task is stored in binary data in 0.
2 Instructions 2-300 CP1E CPU Unit Instructions Reference Manual(W483) MSKS Applicable Pr ogram Areas Operands (1) I/O Interrupt T ask Note When the up/down diff erentiation setting is changed, all detected interr upt inputs will be clea red.
2-301 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Control Instructions 2 MSKS Operand Specifications Flag s Function When the program e xecution starts, the interr u.
2 Instructions 2-302 CP1E CPU Unit Instructions Reference Manual(W483) Precaution • Be sure that the time interval is longer than the time require d to e x ecute the scheduled interrupt task.
2-303 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Control Instructions 2 CLI CLI Applicable Pr ogram Areas Operands (1) Clearing/Retaining an I/O Inte rrupt T ask’ s R.
2 Instructions 2-304 CP1E CPU Unit Instructions Reference Manual(W483) (3) Clearing/Retaining High-spee d Counter Inter rupts Operand Specifications Flags Function Depending on the v alue of N, CL.
2-305 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Control Instructions 2 CLI (2) N = 4: Setting the Time to the First Scheduled Interrupt T ask When N is 4, the content of C specifies the time inter v al to the fir st scheduled interrupt task.
2 Instructions 2-306 CP1E CPU Unit Instructions Reference Manual(W483) DI Applicable Pr ogram Areas Flags Function DI(693) is e xecuted from the main program to temp or arily disable all interrupt tasks (I/O interrupts, scheduled interrupts). Precautions All interrupt tasks will remain disabled until EI(694) is e x ecuted.
2-307 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Interrupt Control Instructions 2 EI EI Applicable Pr ogram Areas Flag s Function • EI(694) is e xecuted from the main progr am to tempo rarily enabl e all interrupt tasks that were disabled by DI(693).
2 Instructions 2-308 CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructions INI Applicable Pr ogram Areas Operands P: P or t Specifier Instruction Mne- monic Va.
2-309 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 INI C: Control Data NV : First W ord with Ne w PV Operand Specifications Flag s Function INI(880) perf or ms the operation spe cified in C f or the por t sp ecified in P .
2 Instructions 2-310 CP1E CPU Unit Instructions Reference Manual(W483) Changing a PV (C = 0002 hex) Stopping Pulse Output (P = 0000, 0001 or 1000 hex and C = 0003 he x) If C is 0003 hex, INI(8 80) immediately stops pulse output f or the specified por t.
2-311 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PR V PR V Applicable Pr ogram Areas Operands P: P or t Specifier C: Control Data .
2 Instructions 2-312 CP1E CPU Unit Instructions Reference Manual(W483) D: First Destination W ord Operand Specifications Flags Function PR V(881) reads the data specified in C for the por t specified in P . The possible combinations of data and por ts are shown in the f ollowing tab le.
2-313 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PR V Reading a PV (C = 0000 hex) Reading Status (C = 0001 hex) P ort and mode Operation Setting range Pulse output (P = 0000 or 0001 he x) The present value of the pulse output is stored in D and D+1.
2 Instructions 2-314 CP1E CPU Unit Instructions Reference Manual(W483) Reading Pulse Output or High-speed Counter Frequency (C = 00 @ 3 he x) If C is 00 @ 3 he x, PR V(881) reads the frequency being output from pulse output 0 or 1 or the frequency being input to high-speed counter 0 and stor es it in D and D+1.
2-315 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 CTBL CTBL Applicable Pr ogram Areas Operands P: P or t specifier C: Control data .
2 Instructions 2-316 CP1E CPU Unit Instructions Reference Manual(W483) TB: First comparison tab le wor d • TB is the first w ord of the comparison table.
2-317 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 CTBL Flag s Function CTBL(882) registers a comp arison table and star ts comparison for the port specified in P and the method specified in C.
2 Instructions 2-318 CP1E CPU Unit Instructions Reference Manual(W483) Range Comparison The corresponding interrupt task is called an d ex ecuted when the PV enters a set range. • The same interrupt task numb er can be specified f or more than one target v alue.
2-319 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 SPED SPED Applicable Pr ogram Areas Operands P: P or t specifier Operand Spec.
2 Instructions 2-320 CP1E CPU Unit Instructions Reference Manual(W483) Flags Function In independent mode, pulse output will stop automatically when the number of pulses set with PULS(886) in adv ance hav e been output. In contin uous mode, pulse output will continue until stopped from the program.
2-321 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 SPED Independent Mode P ositioning When independent mode operation is started, pulse output will be continued until the specified number of pulses has been output.
2 Instructions 2-322 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram When CIO 0.00 tur ns ON in the follo wing programmi ng e xample, PULS(886) sets the number of output pulses f or pulse output 0. An absolute value of 5,000 pulses is set.
2-323 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PULS PULS Applicable Pr ogram Areas Operands P: P or t specifier T : Pulse type N.
2 Instructions 2-324 CP1E CPU Unit Instructions Reference Manual(W483) Flags Function PULS(886) sets the pulse ty pe and number of pulses specified in T and N for the por t specified in P . Actual output of the pulses is star ted later in the program using SPED(885) or A CC(888) in independent mode.
2-325 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PLS2 PLS2 Applicable Pr ogram Areas Operands P: P or t Specifier M: Output Mode I.
2 Instructions 2-326 CP1E CPU Unit Instructions Reference Manual(W483) S: First W ord of Settings T ab le The actual number of mov ement pulses that will be output are as f ollows: • F or relativ e pulse output, the number of mov ement pulses = the set number of pulses.
2-327 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PLS2 Function PLS2(887) star ts pulse output on the por t specified in P using the mode specifi ed in M at the star t fre- quency specified in F (1 in diagr a m).
2 Instructions 2-328 CP1E CPU Unit Instructions Reference Manual(W483) Independent Mode P ositioning Note Pulse output will stop immediately if the CPU Unit is changed to PROGRAM mode.
2-329 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PLS2 Note T r iangular Control If the specified number of pulses is less than the.
2 Instructions 2-330 CP1E CPU Unit Instructions Reference Manual(W483) Switching fr om Continuous Mode Speed Contr ol to Independent Mode P ositioning Sample pr ogram When CIO 0.00 tur ns ON in the f ollowing prog ramming e xample, PLS2(887) starts pu lse output from pulse output 0 with an absolu te pulse specification of 100,000 pulses.
2-331 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 ACC AC C Applicable Pr ogram Areas Operands P: P or t Specifier M: Output Mode Note Use the same pulse output method when using both pulse outp uts 0 and 1.
2 Instructions 2-332 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Flags Function A CC(888) star ts pulse output on the por t sp ecified in P using the m ode specified in M using the target frequency and acceleration/de celer ation rate specified in S .
2-333 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 ACC Continuous Mode Speed Contr ol Pulse output will continue until it is stopped from the program. Note Pulse output will stop immediately if the CPU Unit is changed to PROGRAM mode .
2 Instructions 2-334 CP1E CPU Unit Instructions Reference Manual(W483) Independent Mode P ositioning When independent mode operation is star ted, pulse output will be continued until the specified number of pulses has been output.
2-335 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 ACC Note T r iangular Control If the specified number of pulses is less than the .
2 Instructions 2-336 CP1E CPU Unit Instructions Reference Manual(W483) ORG Applicable Pr ogram Areas Operands P: P or t Specifier C: Control Data Operand Specifications Instruction Mnemonic V ariations Functio n code Function ORIGIN SEARCH ORG @OR G 889 ORG(889) performs an origin search or or igin return op eration.
2-337 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 ORG Flag s Function ORG(889) performs an origin sear ch or origin retur n op eration for the por t specified in P using the method specified in C .
2 Instructions 2-338 CP1E CPU Unit Instructions Reference Manual(W483) When the origin search operation has been completed, the Error Counter Reset Output will be turned ON. The abov e operation, howe ver , depends on the operatin g mode , origin detectio n method, and other paramete rs.
2-339 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) High-speed Counter/Pulse Output Instructio ns 2 PWM PWM Applicable Pr ogram Areas Operands P: P or t Specifier F: Frequency F specifies the freque ncy of the PWM output between 2.0 and 6,553.
2 Instructions 2-340 CP1E CPU Unit Instructions Reference Manual(W483) Operand Specifications Flags Function PWM(891) outputs the frequency spec ified in F at the dut y f actor specified in D from the por t specified in P . PWM (891) can be e xecuted du ring duty-fa ctor PWM output to cha nge the duty f actor without stop- ping PWM output.
2-341 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 Step Instructions In CP1E series PLCs, STEP(008)/SNXT( 009) can be used together to create step programs. Note W or k bits are used as the control bits for A, B , C and D .
2 Instructions 2-342 CP1E CPU Unit Instructions Reference Manual(W483) SNXT/STEP Applicable Pr ogram Areas Operands Operand Specifications Flags Function SNXT(009) SNXT(009) is used in the f ollowing three wa ys: 1.T o star t step pr ogramming e xecution.
2-343 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 SNXT/STEP Proceeding to the Ne xt Step When SNXT(009) occurs in the middle of the step program area, it is used to proceed to the ne xt step .
2 Instructions 2-344 CP1E CPU Unit Instructions Reference Manual(W483) Hint Related Bits Precaution • The control bit, B, m ust be in the W ork Area for STEP(008)/SNXT(009). • A control bit f o r STEP(00 8)/SNXT(009) cannot be use an ywhere else in the ladd er diagram.
2-345 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 SNXT/STEP • STEP(008) an d SNXT(009) cannot be used inside of subr outines, inte rrupt programs , or b lock pro- grams . • Be sure that two steps are not e x ecuted during the same cycle.
2 Instructions 2-346 CP1E CPU Unit Instructions Reference Manual(W483) (1) Sequential Cont rol Step (A) W0.00 Step (B) W0.01 Step (C) W0.02 End 0.01 (Step (A) star ting condition) 0.02 (Step (A) → Step (B) transition condition) 0.03 (Step (B) → Step (C) transition condition) 0.
2-347 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 SNXT/STEP (2) Branching Contr ol Additional Inf ormation: • In the abov e example, where SNXT (009) is ex ecuted fo r W0.02, the branching mo ves onto the ne xt steps e ven though the same control bit is used twice .
2 Instructions 2-348 CP1E CPU Unit Instructions Reference Manual(W483) (3) Parallel Contr o l Step (A) W0.00 Step (B) W0.01 Step (C) W0.02 End 0.05 (Step (C) reset conditions) Step (D) W0.02 Step (E) W0.04 0.04 (When both Step (B) and Step (D) are complete, mov es to Step (E) 0.
2-349 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 SNXT/STEP Application Examples (1) Sequential Execution SW 1 SW 2 SW 3 SW 4 Solenoid 1 Robot hand Solenoid 2 .
2 Instructions 2-350 CP1E CPU Unit Instructions Reference Manual(W483) (2) Branching Execution SW A1 SW A2 SW C1 SW C2 SW D SW B2 SW B1 Process C Process B Process A Guide W eight scale Conv ey er B Conv ey er A Printer 0.01(SW A1) 0.02(SW B1) 0.03(SW A2) 0.
2-351 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Step Instructions 2 SNXT/STEP (3) P arallel Ex ecution SW1 SW2 SW3 SW4 SW6 SW5 SW7 Process C Process A Process D Process B Process E Conv ey er A Conv ey er C Conve yer D Conv ey er B Conv ey er E 0.
2 Instructions 2-352 CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions IORF Applicable Pr ogram Areas Operands St: Starting W ord CIO 001 to CIO 099, C IO 101 to CIO 199 (C.
2-353 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 IORF Units Refreshed b y IORF(097) Note CP1E CPU Unit built-in I/O area cannot be refreshed with IORF(097). CP1E CPU Unit built-in I/O area can be refre shed with immediate refreshi ng specifications (!).
2 Instructions 2-354 CP1E CPU Unit Instructions Reference Manual(W483) SDEC Applicable Pr ogram Areas Operands Di: Digit designator Operand Specifications Flags Instruction Mnemonic V ariations Fu.
2-355 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 SDEC Function Precaution • If more than one digit is specified f o r conv ersi on in Di, digits are conv er ted in order tow ard the most- significant digit.
2 Instructions 2-356 CP1E CPU Unit Instructions Reference Manual(W483) 7-segment Data The f ollowing table sho ws the data co nv ersions from a he xade cimal digit (4 bits) to 7-segment code (8 bits).
2-357 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 DSW DSW Applicable Pr ogram Areas Operands I: Input W ord (Data Line D0 to D3 Inputs) Specify the input word a llocated to the Input Unit and connect the digital s witch’ s D0 to D3 data lines to the Input Unit as shown in the follo wing diagr am.
2 Instructions 2-358 CP1E CPU Unit Instructions Reference Manual(W483) D: First Result W ord Specifies the leading word address where the e xter nal digital switch’ s set values will be stored. C1: Number of Digits Specifies the number of digits that will be read from the e xter nal digital switch.
2-359 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 DSW External Connections Connect the digital s witch or thumbwheel switch to In put Unit contacts 0 to 7 and Output Unit contacts 0 to 4, as shown i n the f ollowing diagr am.
2 Instructions 2-360 CP1E CPU Unit Instructions Reference Manual(W483) Precaution • Do not read or write the system word (C2) from an y other instruction.
2-361 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 MTR MTR Applicable Pr ogram Areas Operands I: Input W ord Specify the input word allocated to the Input Unit and co nnect the 8 input signal lines to the Input Unit as shown in the f ollowing diag ram.
2 Instructions 2-362 CP1E CPU Unit Instructions Reference Manual(W483) D: First Register W ord Specifies the leading word address of the 4 words that co ntain the data from the 8 × 8 matrix. C: System W ord Specifies a work word used by the instruction.
2-363 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 MTR Flag s Function MTR(213) outputs the selection signals to bits 00 to 07 of O , reads the data in or der from bits 00 to 07 of I, and stores the 64 bits of data in th e 4 wo rds D thro ugh D+3.
2 Instructions 2-364 CP1E CPU Unit Instructions Reference Manual(W483) Precaution • Do not read or write the system word (C) from any other instruction. MTR (213) will not operate cor- rectly if the system word is accessed by anothe r instruction. The system word is not initialized b y MTR(213) in the first cycle when program e xecutio n star ts.
2-365 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 7SEG 7SEG Applicable Pr ogram Areas Operands S: Source W or d Specify the first source word containing the data that will be conv er ted to 7-segment display data.
2 Instructions 2-366 CP1E CPU Unit Instructions Reference Manual(W483) • Conv er ting 8 digits C: Control Data The value of C indicates the n umber of digits of source data and the logic f or the Input and Output Units, as sho wn in the f ollowing tab le.
2-367 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Basic I/O Unit Instructions 2 7SEG External Connections Connect the 7-segment displa y to the Output Unit as shown in the f ollowing diag ram. This e xample shows an 8-digit displa y .
2 Instructions 2-368 CP1E CPU Unit Instructions Reference Manual(W483) Precaution • Do not read or write the system word (D) from any other instruction.
2-369 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 TXD Serial Comm unication Instructions TXD Applicable Pr ogram Areas Operands C: Control w or.
2 Instructions 2-370 CP1E CPU Unit Instructions Reference Manual(W483) Flags Related A uxiliar y Area W ords and Bits CPU Unit’ s Bu ilt-in RS-232C P or t Serial Option Board P or t Related .
2-371 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 TXD • Up to 259 bytes can be sent, including the send data (N = 256 b ytes max.), the star t code, and the end code . • Specify the size of the send data, not including the star t code and end code, in N.
2 Instructions 2-372 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram Sending Data to a Code Reader This e xample shows ho w to send data to the V530-R150 V3 2D Code Reader as an example of commu- nicating with an e x ternal device.
2-373 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 TXD Pr ogramming Example If CIO 0.01 turns ON while the RS-232C P or t Send Ready F lag (A392.
2 Instructions 2-374 CP1E CPU Unit Instructions Reference Manual(W483) RXD Applicable Pr ogram Areas Operands C: Control W ord Operand Specifications Flags Instruction Mnemonic V ariations Functio.
2-375 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 RXD Related A uxiliar y Area W ords and Bits A uxiliary Area Flags for CPU Unit’ s RS-2.
2 Instructions 2-376 CP1E CPU Unit Instructions Reference Manual(W483) Function • RXD(235) reads data that has been receiv ed in no-pro tocol mode at the CPU Unit’ s built-in RS-232C por t or the Serial O ption Board por t (the por t is specified wit h bits 8 to 11 of C) and stores N bytes of data in words D to D+(N ÷ 2)-1.
2-377 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 RXD Start Code/End Code Se ttings and Receive Data Hint • When RXD(235) is used to read data that was receiv ed at one of the Serial Option Board’ s por ts , the por t’ s reception buff er is cleared after RXD(23 5) is ex ecuted.
2 Instructions 2-378 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram Receiving data This e xample shows how to receiv e data from th e V530-R150V3 2D Code Read er as an example of communicating with an e xter nal de vice.
2-379 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Serial Communication Instructions 2 RXD Pr ogramming Example If CIO 0.02 turns ON while the RS-2 32C P or t Send Ready Flag (A392.
2 Instructions 2-380 CP1E CPU Unit Instructions Reference Manual(W483) Cloc k Instructions CADD/CSUB Applicable Pr ogram Areas Operands Instruction Mnemonic V ariations Functio n code Function CALEND AR ADD CADD @CADD 730 Adds time to the calendar data in the specified words.
2-381 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Clock Instructions 2 CADD/CSUB CADD C through C+2: Calendar Data T and T+1: Time Data R through R+2: Result Data 15 8 0 7 C 1.
2 Instructions 2-382 CP1E CPU Unit Instructions Reference Manual(W483) CSUB C through C+2: Calendar Data T and T+1: Time Data R through R+2: Result Data 15 8 0 7 C 15 8 0 7 C+1 15 8 0 7 C+2 Minute.
2-383 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Clock Instructions 2 CADD/CSUB Operand Specifications Flag s Function CADD CADD(730) adds the calenda r data (words C through C+2) to the time data (w ords T and T+1) and outputs the resultin g calendar data to R through R+2.
2 Instructions 2-384 CP1E CPU Unit Instructions Reference Manual(W483) Sample pr ogram CADD When CIO 0.00 tur ns ON in the f ollowing e xample, the calendar data in D1 00 through D102 (y ear , mon.
2-385 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Clock Instructions 2 D A TE DA T E Applicable Pr ogram Areas Operands S through S+3: Ne w Clock Setting Note S through S+3 must be in the same data area.
2 Instructions 2-386 CP1E CPU Unit Instructions Reference Manual(W483) Related A uxiliar y Area W ords and Bits Function D A TE(735) changes th e inter nal clock setting according to the clock data in the four source words. The new inter- nal clock setting is immediately reflected in the Calendar/Cloc k Area (A351 to A354).
2-387 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F AL F ailure Diagnosis Instructions FA L Applicable Pr ogram Areas Operands Generating or C.
2 Instructions 2-388 CP1E CPU Unit Instructions Reference Manual(W483) Flags Related A uxiliar y Area W ords and Bits A uxiliary Area W ords/Flags f o r User-defined Err ors Only A uxiliary Ar.
2-389 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F AL Function Generating Non-fatal User -defined Error s The f ollowing tab le shows the error codes and F AL Er ror Flags f or F AL(006).
2 Instructions 2-390 CP1E CPU Unit Instructions Reference Manual(W483) 1. The specified error code will be written to A400. 2. The error code and the time that the error occurred will be written to the Error Log Area (A100 through A199) . 3. The appropriate Auxiliary Area Flags are set based on the error code and error details.
2-391 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F AL Note Even if PLC Setup w ord 129 bit 15 is set to 1 (Do not record F AL Errors in Error Log.
2 Instructions 2-392 CP1E CPU Unit Instructions Reference Manual(W483) Clearing a P articular Non-fatal Error When CIO 0.01 is ON in the f ollowing example , F AL(006) will clear the non-f atal error with F AL number 31, turn OFF the corres ponding Executed F AL Number Flag (A361.
2-393 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F ALS FA L S Applicable Pr ogram Areas Operands Generating User-defined F atal Error s Note The v alue of operand N must be different from the content of A529 (the system-generated F AL/F ALS number).
2 Instructions 2-394 CP1E CPU Unit Instructions Reference Manual(W483) Related A uxiliar y Area W ords and Bits A uxiliary Area W ords/Flags f o r User-defined Err ors Only A uxiliary Area W o.
2-395 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F ALS 4 When a user-defined fatal error is registe red, the I/O memor y and output status from output u nits will be as indicated below .
2 Instructions 2-396 CP1E CPU Unit Instructions Reference Manual(W483) The f ollowing table sho ws how to specify er ror codes and error details in S and S+1.
2-397 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Failure Diagnosis Instructions 2 F ALS Sample pr ogram Generating a User -defined Error When CIO 0.00 is ON in the follo wing ex ample, F ALS(007) will generate a fatal error with F AL number 31 and e xecute the f ollowing processes.
2 Instructions 2-398 CP1E CPU Unit Instructions Reference Manual(W483) Other Instructions STC/CLC Applicable Pr ogram Areas Flags Function STC When the e x ecution condition is ON, STC(040) turns ON the Carry Flag (CY).
2-399 2 Instructions CP1E CPU Unit Instructions Reference Manual(W483) Other Instructions 2 WDT WDT Applicable Pr ogram Areas Operands T : Timer setting Specifies the watchdog timer setting between 0000 and 0064 he xadecimal or between &0000 and &0100 decimal.
2 Instructions 2-400 CP1E CPU Unit Instructions Reference Manual(W483) PLC Setup settings Note • The default value f or the maximum cycle time is 1,00 0 ms, although it can be set anywhere from 10 to 1,000 ms in 10-ms units. • WDT(094) can be used more than once in a cycle.
3-1 CP1E CPU Unit Instructions Reference Manual(W483) 3 This section provides the e x ecution times for all instructions used with a CP1E CPU Unit. 3-1 CP1E CPU Unit Instruction Execution Times and Number of Steps .
3 Instruction Exec ut ion Times and Number of Steps 3-2 CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Ex ecution Times and Number of Steps The f ollowing tab le lists the e xecution times f or all instruct ions that are suppor ted by the CPU Units.
3-3 3 Instruction Execution Times and Number of Steps CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Execution Times and Number of 3 Sequence Input Instructions Instru ction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Condit ions LOAD LD --- 1 1.
3 Instruction Exec ut ion Times and Number of Steps 3-4 CP1E CPU Unit Instructions Reference Manual(W483) Sequence Contr ol Instructions Instruction Mnemonic FUN No. Length (steps ) ON execution time ( µ s) Condition s END END 001 1 4.6 --- NO OPERA TION NOP 000 1 1.
3-5 3 Instruction Execution Times and Number of Steps CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Execution Times and Number of 3 Comparison Instructions Instru ction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Conditions Input Comparison Instructions (unsigned) LD ,AND ,OR+= 300 4 9.
3 Instruction Exec ut ion Times and Number of Steps 3-6 CP1E CPU Unit Instructions Reference Manual(W483) Data Mo vement Instructions Instruction Mnemonic FUN No. Length (steps) ON executi on time ( µ s) Conditions MO VE MOV 021 3 8.0 --- !MO V 021 7 57.
3-7 3 Instruction Execution Times and Number of Steps CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Execution Times and Number of 3 Increment/Decrement Instructions Instru ction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Condit ions INCREMENT BINAR Y ++ 590 2 12.
3 Instruction Exec ut ion Times and Number of Steps 3-8 CP1E CPU Unit Instructions Reference Manual(W483) Con version Instructions Instruction Mnemonic FUN No. Length (steps ) ON executi on time ( µ s) Condit ions BCD T O BINAR Y BIN 023 3 15.1 - -- DOUBLE BCD T O DOUBLE BINAR Y BINL 058 3 16.
3-9 3 Instruction Execution Times and Number of Steps CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Execution Times and Number of 3 Floating-point Math Instructions Instru ction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Conditions FLOA TING T O 16-BIT FIX 450 3 15.
3 Instruction Exec ut ion Times and Number of Steps 3-10 CP1E CPU Unit Instructions Reference Manual(W483) Subr outine Instructions Instruction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Conditions SUBROUTINE CALL SBS 091 2 6.6 --- SUBROUTINE E NTR Y SBN 092 2 2.
3-11 3 Instruction Execution Times and Number of Steps CP1E CPU Unit Instructions Reference Manual(W483) 3-1 CP1E CPU Unit Instruction Execution Times and Number of 3 ACCELE RA TION CONTROL ACC 888 4 75.6 Continuou s mode 82.8 Independent mode ORIGIN SEAR CH ORG 889 3 52.
3 Instruction Exec ut ion Times and Number of Steps 3-12 CP1E CPU Unit Instructions Reference Manual(W483) F ailure Diagnosis Instructions Instruction Mnemonic FUN No. Length (steps) ON execution time ( µ s) Conditions F AILURE ALARM F AL 006 3 55.6 Recording errors 79.
4-1 CP1E CPU Unit Instructions Reference Manual(W483) 4 This section describes how to mo nitor and calculate the cycle time of a CP1E CPU Unit that can be used in the pr ograms . 4-1 Monitoring the C ycle Time . . . . . . . . . . . . . . . . . . . . .
4 Monitoring and Computing the Cycle Time 4-2 CP1E CPU Unit Instructions Reference Manual(W483) 4-1 Monitoring the Cyc le Time The av erage, maximum, and minim um cycle times ca n be monit ored when the CX-Programmer is con- nected online to a CPU Unit.
4-3 4 Monitoring and Computing the Cycle Time CP1E CPU Unit Instructions Reference Manual(W483) 4-2 Computing th e Cycle Time 4 4-2-1 CPU Unit Operation Flowchar t 4-2 Computing the Cyc le Time The CPU Unit processes data in repeating cycles from the ov erseeing processing up to peripheral ser vicing as shown in the f ollowing diagra m.
4 Monitoring and Computing the Cycle Time 4-4 CP1E CPU Unit Instructions Reference Manual(W483) The cycle time depends on the follo wing conditions. • T ype and number of instr uctions in the us er .
4-5 4 Monitoring and Computing the Cycle Time CP1E CPU Unit Instructions Reference Manual(W483) 4-2 Computing th e Cycle Time 4 4-2-3 I/O Refresh Times for PLC Units (5) P eripheral Servicing I/O .
4 Monitoring and Computing the Cycle Time 4-6 CP1E CPU Unit Instructions Reference Manual(W483) The f ollowing e xample shows th e method used to calculate the cycle time when Expansion I/O Units are connected to a CP1E CPU Unit.
A-1 pp CP1E CPU Unit Instructions Reference Manual(W483) App Alphabetical List of Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . .
Appendices A-2 CP1E CPU Unit Instructions Reference Manual(W483) Alphabetical List of Instructions b y Mnemonic A Mne- monic Instru ction FUN No. Upward differen- tiatio n Downward differentia- tion I.
A-3 Appendices CP1E CPU Unit Instructions Reference Manual(W483) Alphabetical List of Instructions by Mnemonic App B C AND>= SL AND DBL SIGNED GREA TER THAN OR EQU AL 328 --- --- --- 2-88 AND> D.
Appendices A-4 CP1E CPU Unit Instructions Reference Manual(W483) D E F H I J K L Mne- monic Instru ction FUN No. Upward differen- tiation Downward differ enti a- tion Immediate refreshing specifica- t.
A-5 Appendices CP1E CPU Unit Instructions Reference Manual(W483) Alphabetical List of Instructions by Mnemonic App LD NO T LOAD NO T --- --- --- !LD NOT 2-7 LD< LOAD LESS THAN 310 --- --- --- 2-88 .
Appendices A-6 CP1E CPU Unit Instructions Reference Manual(W483) M N O Mne- monic Instru ction FUN No. Upward differen- tiation Downward differ enti a- tion Immediate refreshing specifica- tion Pag e .
A-7 Appendices CP1E CPU Unit Instructions Reference Manual(W483) Alphabetical List of Instructions by Mnemonic App P R OR= OR EQU AL 300 --- --- - -- 2-88 OR=DT OR DA TE EQU AL 341 --- --- --- 2-91 OR.
Appendices A-8 CP1E CPU Unit Instructions Reference Manual(W483) S T U W X Mne- monic Instru ction FUN No. Upward differen- tiation Downward differ enti a- tion Immediate refreshing specifica- tion Pa.
A-9 Appendices CP1E CPU Unit Instructions Reference Manual(W483) Alphabetical List of Instructions by Mnemonic App Z Symbol Mne- monic Instruction FUN No.
Appendices A-10 CP1E CPU Unit Instructions Reference Manual(W483) ASCII Code T ab le *BL DOUBLE BCD MUL TI- PL Y 425 @ *B L --- --- 2-179 *F FLOA TING- POINT MUL TIPL Y 456 @ *F --- --- 2-237 *L DOUBL.
Revision-1 Re vision Histor y A manual r e vision code a ppears a s a suffix t o the c atalog number o n the fron t cover of the manual. Revi sion code Date Rev ised content 01 March 2009 Original p roducti on 02 June 200 9 Errors we re corrected. 03 Ja nuary 2010 In formatio n added on E10/14, N 14/60 and NA20 CPU Units.
Revision-2.
Authorized Distrib utor: In the interest of product improvement, specifications are subject to change without notice. Cat. No. W483-E1-03 0110 © OMRON Corporation 2009 All Rights Reserved. OMRON Corporation Industrial Automation Company OMRON ELECTRONICS LLC One Commerce Drive Schaumburg, IL 60173-5302 U.
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