Instruction/ maintenance manual of the product DS33Z41 Maxim
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1 of 167 REV: 122006 Note: Some revisions of this device may incor porate deviations from published specifications known as erra ta. Multiple revisions of any device may be simultaneously available through various sales channel s. For information about device errata, click here: www.
DS33Z41 Quad IMUX Ethernet Mapper 2 of 167 TABLE OF CONTENTS 1 DESCRIPTION .................................................................................................................... 7 2 FEATURE HIGH LIGHTS ...................................
DS33Z41 Quad IMUX Ethernet Mapper 3 of 167 8.14 E THERNET MAC.......................................................................................................................... 46 8.14.1 MII Mode ................................................
DS33Z41 Quad IMUX Ethernet Mapper 4 of 167 12.2.2 BYPASS ......................................................................................................................... ...................163 12.2.3 EXTEST ...................................
DS33Z41 Quad IMUX Ethernet Mapper 5 of 167 LIST OF FIGURES Figure 3-1. Quad T1/E 1 SCT to DS33Z41 .......................................................................................... .................... 11 Figure 6-1. Detail ed Block Di agram..
DS33Z41 Quad IMUX Ethernet Mapper 6 of 167 LIST OF TABLES Table 2-1. T1 Related Teleco mmunications Spec ifications ........................................................................ ............ 10 Table 7-1. Detailed Pin Descriptions .........
DS33Z41 Quad IMUX Ethernet Mapper 7 of 167 1 DESCRIPTION The DS33Z41 provides in terconnection and ma pping functionality between Et hernet Packet Systems and WA N Time-Division Multiplexed (TDM) syst ems such as T1/E1/J1, HDSL, and T3/E3.
DS33Z41 Quad IMUX Ethernet Mapper 8 of 167 2 FEATURE HIGHLIGHTS 2.1 General • 169-pin, 14mm x 14mm CSBGA package • 1.8V supply with 3.3V tolerant inputs and outputs • IEEE 1149.
DS33Z41 Quad IMUX Ethernet Mapper 9 of 167 2.6 SDRAM Interface • Interface for 128Mb, 32-bit-wide SDRAM • SDRAM Interface speed up to 100MHz • Auto Refresh Timing • Automatic Precharge • Master clock provided to the SDRAM • No external components requi re d for SDRAM connectivity 2.
DS33Z41 Quad IMUX Ethernet Mapper 10 of 167 2.10 Specifications compliance The DS33Z41 meets relevant telecom munications specificat ions. The following table provides the specificat ions and relevant sections that are applicable to the DS33Z41. Table 2-1.
DS33Z41 Quad IMUX Ethernet Mapper 11 of 167 3 APPLICATIONS • Bonded Transparent LAN Service • LAN Extension • Ethernet Delivery Over T1/E1/J1, T3/E 3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS 33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an exam ple of a complete LAN to WAN design.
DS33Z41 Quad IMUX Ethernet Mapper 12 of 167 4 ACRONYMS AND GLOSSARY • BERT—Bit Error Rate Tester • DCE—Data Communication Interface • DTE—Data Terminating Interface • FCS—Frame Check S.
DS33Z41 Quad IMUX Ethernet Mapper 13 of 167 5 MAJOR OPERATING MODES Operation of the DS33Z41 operation requ ires a host microprocessor for init ialization and maintenance of the link aggregation functions. Microproce ssor cont rol is possible through the 8-bit pa rallel control port.
DS33Z41 Quad IMUX Ethernet Mapper 14 of 167 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are inout pin s in JTAG mode. This feat ure increases the effectiveness of board leve l ATPG patterns.
DS33Z41 Quad IMUX Ethernet Mapper 15 of 167 NAME PIN TYPE FUNCTION TX_CLK A8 IO Transmit Clock (MII). Timing reference for TX_EN and TXD[3:0]. The TX_CLK frequency is 25MHz fo r 100Mbps operatio n and 2.5MHz for 10Mbps operation. In DTE mode, this is a clock input provided by the PHY.
DS33Z41 Quad IMUX Ethernet Mapper 16 of 167 NAME PIN TYPE FUNCTION COL_DET B13 I Collision Detect (MII). Asserted by the MAC PHY to indicate that a collision is occurring. In DCE Mode this signal should be conne cted to ground. This signal is only valid in half duplex mode, and is ignored in full duplex mode MDC C12 O Management Data Clock (MII).
DS33Z41 Quad IMUX Ethernet Mapper 17 of 167 NAME PIN TYPE FUNCTION RD / DS E1 I Read Data Strobe (Intel Mode). The DS33Z41 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. Data Strobe (Motorola Mode).
DS33Z41 Quad IMUX Ethernet Mapper 18 of 167 NAME PIN TYPE FUNCTION SDRAM CONTROLLER SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6] SDATA[7] SDATA[8] SDATA[9] SDATA[10] SDATA[11] SDATA[.
DS33Z41 Quad IMUX Ethernet Mapper 19 of 167 NAME PIN TYPE FUNCTION SCAS H4 O SDRAM Column Address Strobe. Active-low output, used to latch the column address on the ri sing edge of SDCLKO. It is used with commands for Bank A ctivate, Precharge, and Mode Register Write.
DS33Z41 Quad IMUX Ethernet Mapper 20 of 167 NAME PIN TYPE FUNCTION POWER SUPPLIES VDD3.3 G5–G10, H2, H5, H6, H7–H10 I VDD3.3: Connect to 3.3V Po wer Supply VDD1.
DS33Z41 Quad IMUX Ethernet Mapper 21 of 167 Figure 7-1. DS33Z41 256-Ball CSBGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 A A0 A2 A5 A8 D0 D1 D2 TX_CLK VSS RX _CLK RXD[3] VSS DCEDTES B A1 A3 A6 A9 D3 D4 D5 NC TXD[0] VSS RXD[0] RX_ERR COL_DET C CS A4 A7 RMIIMIIS D6 D7 QOVF RX_CRS TXD[1] VSS RXD[1 ] MDC MDIO D VSS VDD1.
DS33Z41 Quad IMUX Ethernet Mapper 22 of 167 8 FUNCTIONAL DESCRIPTION The DS33Z41 provides in terconnection and ma pping functionality between Et hernet Packet Systems and WA N Time-Division Multiplexed (TDM) syst ems such as T1/E1/J1, HDSL, and T3/E3.
DS33Z41 Quad IMUX Ethernet Mapper 23 of 167 8.1 Processor Interface Microprocessor control of the DS33Z41 is accomplish ed through the 20 interfa ce pins of the microprocesso r port. The 8-bit parallel d ata bus can be co nfigured for Intel or Motorola modes of op eration with the two M ODEC[1:0] pins.
DS33Z41 Quad IMUX Ethernet Mapper 24 of 167 8.2 Clock Structure The DS33Z41 clocks sources and funct ions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are use d to transfer data from the serial interface.
DS33Z41 Quad IMUX Ethernet Mapper 25 of 167 Figure 8-1. Clocking for the DS33Z41 MAC RMII MII SDRAM Interface Buffer Dev Div by 2 ,4,12 Output Clocks 25,50 Mhz 100 Mh z Oscillator SYSCLKI SDCLKO Buffer Div by 1,2,4, 8,10 Out put cl ocks : 50,25 Mhz, 2.
DS33Z41 Quad IMUX Ethernet Mapper 26 of 167 8.2.1 Serial Interface Clock Modes The Serial Interface timing is d etermined by the line cl oc ks. 8.192MHz is the required clock rate for interfacing th e IBO bus to Dallas Semiconductor F ramers and Singl e-Chip Transceivers.
DS33Z41 Quad IMUX Ethernet Mapper 27 of 167 8.3 Resets and Low-Pow er Modes The external RST pin and the global reset bit in GL.CR1 create an internal global re set signal. The globa l reset signal resets the status an d contro l registers on the chip (except the GL.
DS33Z41 Quad IMUX Ethernet Mapper 28 of 167 8.4 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits ou tlined in Section 8.3 . Clear all reset bits.
DS33Z41 Quad IMUX Ethernet Mapper 29 of 167 8.7 Device Interrupts Figure 8-2 diagrams the flow of interru pt conditions from thei r source status bits thro ugh the multiple levels o f information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched Status regi sters GL.
DS33Z41 Quad IMUX Ethernet Mapper 30 of 167 Figure 8-2. Device Interrupt Information Flow Diagram Receive FCS Errored Pack et 7 Receive A borted Packet 6 Receive Inv alid Packet Detected 5 Receive Sma.
DS33Z41 Quad IMUX Ethernet Mapper 31 of 167 8.8 Serial Interface The Serial Interface consists of physi cal serial po rt, IMUX/IBO Formatte r, and HDLC/X.86 engine. The Serial Interface supports time-div ision multiplexed serial data, in a format compati ble with Dallas Semicon ductor’s 8.
DS33Z41 Quad IMUX Ethernet Mapper 32 of 167 Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 T1E1 T1E1 LIU LIU LIU LIU Framer Framer Framer Framer I B O TSER RSER TSYNC RSYNC Line 1 IMU X Etherne t Port Arbite r SDRAM Inter face H D L C T1E1 T1E1 TCLKI RCLKI Figure 8-4.
DS33Z41 Quad IMUX Ethernet Mapper 33 of 167 8.9.1 Microprocessor Requirements Link aggregation requires an exte rnal host microp rocessor to issue in structions and to m onitor the IMUX f unction of the DS33Z41. The host microproc essor is responsible for the followin g tasks to open a transmit channel: • Configuring GL.
DS33Z41 Quad IMUX Ethernet Mapper 34 of 167 8.9.2 IMUX Command Protocol The format for all comman ds sent and received in C hannel 2 of the IBO Se rial Interface is shown in Figure 8-5 . The MSB for all commands is a “1”. The next 6 bits cont ai n the actual opcode for the com mand.
DS33Z41 Quad IMUX Ethernet Mapper 35 of 167 The command and status registers for the IMUX functi on are detailed below: Table 8-4. Command and Status for the IMUX for Processor Communication REGISTER NAME COMMENTS IMUX Configuration Register GL.IMXCN Used to configure the number of links participating and select T1 or E1.
DS33Z41 Quad IMUX Ethernet Mapper 36 of 167 8.9.3 Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization mo nitoring i s started. The device will declare an out of frame ( OOF) if 2 cons ecutive se quence err ors are rec e ived.
DS33Z41 Quad IMUX Ethernet Mapper 37 of 167 8.10 Connectio ns and Queues The multi-port devices in this product fa mily provide bidirectional cross-c onnecti ons between the multiple Ethernet ports and Serial port s when operating in software mode.
DS33Z41 Quad IMUX Ethernet Mapper 38 of 167 It is recommended that the user reset the queue p ointers for the connection after disconnection. The pointers must be reset before a co nnection is made. If this di sc onnect/connect p rocedure is not followed, in correct data may be transmitted.
DS33Z41 Quad IMUX Ethernet Mapper 39 of 167 8.12 Flow Control Flow control may be required to ensure that data queue s do not overflow and packet s are not lost. The DS33Z41 allows for optional flow control based on the queue high wa termark or through h ost processor intervention.
DS33Z41 Quad IMUX Ethernet Mapper 40 of 167 8.12.1 Full-Duplex Flow Control Automatic flow control i s enabled by default. The h ost processor can disable thi s functionality with SU.GCR .ATFLOW. The flow control mechanism is governed by t he high watermarks ( SU.
DS33Z41 Quad IMUX Ethernet Mapper 41 of 167 Figure 8-6. Flow Control Using Pause Control Frame Receive Queue Growth Receive Queue High Wa t e r M ar k Initiate Flo w co ntrol 8 Rx Data Receive Queue Low Wa te r 8.12.2 Half-Duplex Flow control Half duplex flow control uses a jamming sequence to ex ert backp r essure on the transmitting node.
DS33Z41 Quad IMUX Ethernet Mapper 42 of 167 8.13 Ethernet Interface Port The Ethernet port interface all ows for direct connecti on to an Ethernet PHY. The interface consi s ts of a 10/100Mbps MII/RMII interface and an Ether net MA C. In RMII operation, the inte rface contains 7 signals with a reference clock of 50MHz.
DS33Z41 Quad IMUX Ethernet Mapper 43 of 167 • MII error asserted during the receptio n of the frame. • Dribbling bits occurred in the frame. • CRC error occur red. • Length error occurred—the length indica ted by the frame length i s incons istent with the number of bytes received.
DS33Z41 Quad IMUX Ethernet Mapper 44 of 167 Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode MAC RXD[3:0] RXD[3:0] RX_CLK RX_CLK RX_ERR RX_ERR RX_CRS RX_CRS COL_DET COL_DET Ether.
DS33Z41 Quad IMUX Ethernet Mapper 45 of 167 Figure 8-9. DS33Z41 Configured as a DCE in MII Mode MAC TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_ER R RX_ERR TX_ EN RX_CRS COL_DET COL_DET DTE DCE TX_ EN RXDV MDC.
DS33Z41 Quad IMUX Ethernet Mapper 46 of 167 8.14 Ethernet MAC Indirect addressing is required to access the MAC regi ster settings. Writing to the MAC registers requires the SU.MACWD0 -3 registers to be written with 4 bytes of data. The address must be written to SU.
DS33Z41 Quad IMUX Ethernet Mapper 47 of 167 8.14.1 MII Mode The Ethernet interface can be configured for MII opera tion by setting the hardware pin RMIIMIIS low. T he MII interface consists of 17 pins. For instructions on clo cki ng the Ethernet Interface while in MII mode, see Section 8.
DS33Z41 Quad IMUX Ethernet Mapper 48 of 167 8.14.3 PHY MII Ma nagement Block and MDIO Interface The MII Management Block allo ws for the host to control up to 32 PHYs, e a ch with 32 registers. The MII block communicates with the external PHY us ing 2-wire serial interface composed of MDC (serial clock) and MDIO for data.
DS33Z41 Quad IMUX Ethernet Mapper 49 of 167 8.15.2 Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receiv es only the payload dat a and synchronizes the receive pattern generator to the incoming pattern.
DS33Z41 Quad IMUX Ethernet Mapper 50 of 167 Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync Match Verify 1 bit error Patter n Matche s 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 8.
DS33Z41 Quad IMUX Ethernet Mapper 51 of 167 8.15.5.2 Performance Monitoring Update All counters stop counting at their maximum count. A count er register is updated by asserting (low to high transition) the performance monitori ng update signal (P MU).
DS33Z41 Quad IMUX Ethernet Mapper 52 of 167 8.16 Transmit Packet Processor The Transmit Packet Processor accept s data from the Tr ansmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, pa cket abort sequence in sertio n, inter-frame padding, and p acket scrambling.
DS33Z41 Quad IMUX Ethernet Mapper 53 of 167 8.17 Receive Packet Processor The Receive Packet Processor accept s data from the Receive Serial Inte rface pe rforms pack et descramb ling, packet delineat.
DS33Z41 Quad IMUX Ethernet Mapper 54 of 167 FCS byte extraction discards th e FC S bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disable d , the FC S bytes are stored in the receive FI FO with the packet.
DS33Z41 Quad IMUX Ethernet Mapper 55 of 167 8.18 X.86 Encoding and Decoding X.86 protocol provides a method fo r encapsulating Ethernet Frame onto LAPS. LAPS provides a HDLC-type framing structure for enca psulation of Ethernet frames , but d oes not inflict dynamic bandwidth exp ansion as HDLC does.
DS33Z41 Quad IMUX Ethernet Mapper 56 of 167 Figure 8-15. X.86 Encapsula tion of the MAC field Flag(0x7E) Address (0x04) Control(0x03) 1st Octect o f SAPI(0x fe) 2nd Octect of SAPI (0x01) Destinat ion .
DS33Z41 Quad IMUX Ethernet Mapper 57 of 167 The X86 received frame is aborted if: • If 7d, 7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 o ctets. • Control, SAPI and address field are mism atched to the programmed value.
DS33Z41 Quad IMUX Ethernet Mapper 58 of 167 8.19 Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR can be used to re strict the transport of receiv ed MAC data to the serial port at a program mable rate. This is shown in Figure 8-16 .
DS33Z41 Quad IMUX Ethernet Mapper 59 of 167 Figure 8-16. CIR in th e WAN Transmit Path MAC RMII MII SDRAM Interface Buffer D ev Div by 2,4,12 Output Clock s 25,50 Mhz 100 Mhz Osc ill ator SYSCLKI SDCLKO Buffer Dev Div by 1,2 ,4,8, 10 Out put cl ocks: 50,25 Mhz, 2.
DS33Z41 Quad IMUX Ethernet Mapper 60 of 167 9 DEVICE REGISTERS Ten address lines are used to address the regi ster space. Table 9-1 shows the re gister map for the DS 33Z41. The addressable range f or the device is 0000h t o 08FFh . Each Register Section is 64 bytes deep.
DS33Z41 Quad IMUX Ethernet Mapper 61 of 167 9.1 Register Bit Maps Table 9-2 , Table 9-3 , Table 9-4 , Table 9-5 , Table 9-6 , and Table 9-7 contain the registers of the DS33Z41.
DS33Z41 Quad IMUX Ethernet Mapper 62 of 167 9.1.2 Arbiter Register Bit Ma p Table 9-3. Arbiter Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 040h AR .R QS C1 RQSC1[7] RQSC1[6] RQSC1[5] RQSC1[4] RQSC1[3] RQSC1[ 2] RQSC1[1] RQSC1[0] 041h AR .
DS33Z41 Quad IMUX Ethernet Mapper 63 of 167 9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Inte rface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0C0h Reserved - - - - - - - - 0C1h LI.RSTPD - - - - - - RESET - 0C2h LI.
DS33Z41 Quad IMUX Ethernet Mapper 64 of 167 A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 103h LI.RMPSCH RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8 104h LI.RPPSR - - - - - REPC RAPC RSPC 105h LI.RPPSRL REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL 106h LI.
DS33Z41 Quad IMUX Ethernet Mapper 65 of 167 9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet In terface Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 140h SU.MACRADL MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 141h SU.
DS33Z41 Quad IMUX Ethernet Mapper 66 of 167 9.1.6 MAC Regis ter Bit Map Table 9-7. MAC Indir ect Register Bit Map A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 0000h SU.MACCR 31:24 - - - HDB PS - - - 0001h 23:16 DRO OML1 OML0 F PM PAM - - 0002h 15:8 - - - LCC - DRTY - ASTP 0003h 7:0 BOLMT1 BOLMT0 DC - TE RE - - 0004h SU.
DS33Z41 Quad IMUX Ethernet Mapper 67 of 167 A DDR N AME B IT 7 B IT 6 B IT 5 B IT 4 B IT 3 B IT 2 B IT 1 B IT 0 110h RESERVED – initialize to FF - - - - - - - - 111h RESERVED – initialize to FF - - - - - - - - 112h RESERVED – initialize to FF - - - - - - - - 113h RESERVED – initialize to FF - - - - - - - - 200h SU.
DS33Z41 Quad IMUX Ethernet Mapper 68 of 167 9.2 Global Register Definitions Functions contained in th e global registers include: fram e r reset, LIU reset, device ID, B ERT interrupt status, framer interrupt status, IBO configur ation, MCLK configuration, and BPCLK configuration.
DS33Z41 Quad IMUX Ethernet Mapper 69 of 167 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name — — — — — R E F _ C L K O INTM RST Default 0 0 0 Bit 2: REF_CLKO OFF ( REF_CLKO).
DS33Z41 Quad IMUX Ethernet Mapper 70 of 167 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activ it y Latched Status Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name — — — RLCALS1 — — — TLCALS1 Default 0 0 0 0 0 0 0 0 Bit 4: Receive Serial Interface Clock Ac tivity Latched Status 1 (RLCALS1).
DS33Z41 Quad IMUX Ethernet Mapper 71 of 167 Register Name: GL.LIE Register Description: Global Serial Interface Interrupt Enable Register Address: 06h Bit # 7 6 5 4 3 2 1 0 Name — — — LIN1TIE — — — LIN1 RIE Default 0 0 0 0 0 0 0 0 Bit 4: Serial Interface 1 Tx Interrupt Enable (LINE1TIE).
DS33Z41 Quad IMUX Ethernet Mapper 72 of 167 Register Name: GL.TRQIE Register Description: Global Transmit Receive Queue Interrupt Enable Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0 Name — — — TQ1IE — — — RQ1IE Default 0 0 0 0 0 0 0 0 Bit 4: Transmit Queue 1 Interrup t Enable (TQ1IE).
DS33Z41 Quad IMUX Ethernet Mapper 73 of 167 Register Name: GL.CON1 Register Description: Connection Register for Ethernet Interface 1 Register Address: 0Eh Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — LINE1[0] Default 0 0 0 0 0 0 0 1 Bit 0: LINE1[0].
DS33Z41 Quad IMUX Ethernet Mapper 74 of 167 Register Name: GL.IMXCN Register Description: Inverse MUX Configuration Register Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Name — T1E1 RXE SENDE L4 L3 L2 L1 Default 0 0 0 0 0 0 0 0 Bit 6: T1E1 Mode (T1E1).
DS33Z41 Quad IMUX Ethernet Mapper 75 of 167 Register Name: GL.IMXSS Register Description: Inverse MUX Sync Status Register Address: 18h Bit # 7 6 5 4 3 2 1 0 Name ITSYNC4 ITSYNC3 ITSYNC2 ITSYNC1 IRSYNC4 IRSYNC3 IRSYNC2 IRSYNC1 Default 0 0 0 0 0 0 0 0 Bit 7: IMUX Transmit Sync 4 (ITSYNC4).
DS33Z41 Quad IMUX Ethernet Mapper 76 of 167 Register Name: GL.IMXSLS Register Description: Inverse MUX Sync Latched Status Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name ITSYNCLS4 ITSYNCLS3 ITSYNCLS2 ITSYNCLS1 IRSYNCLS4 IRSYNCLS3 IRSYNCLS2 IRSYNCLS1 Default 0 0 0 0 0 0 0 0 Bit 7: IMUX Transmit Sync Latched Statu s 4 (ITSYNCLS4).
DS33Z41 Quad IMUX Ethernet Mapper 77 of 167 Register Name: GL.IMXOOFIE Register Description: Inverse MUX OOF Interrupt Enable Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name TOOFIE4 TOOFIE3 TOOFIE2 TOOFIE1 ROOFIE4 ROOFIE3 ROOFIE2 ROOFIE1 Default 0 0 0 0 0 0 0 0 Bit 7: IMUX Transmit OOF Interr upt Enable 4 (TOOFIE4).
DS33Z41 Quad IMUX Ethernet Mapper 78 of 167 Register Name: GL.IMXOOFLS Register Description: Inverse MUX Out Of Frame Latched Status Register Address: 1Fh Bit # 7 6 5 4 3 2 1 0 Name TOOFLS4 OOFLS3 TOOFLS2 TOOFLS1 ROOFL4 ROOFL3 ROOFLS2 ROOFLS1 Default 0 0 0 0 0 0 0 0 Bit 7: IMUX Transmit OOF Latched S tatus 4 (TOOFLS4).
DS33Z41 Quad IMUX Ethernet Mapper 79 of 167 Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z 41 performs BIST testing on the SDRAM and the test passes. T his bit is set to 1 if the test failed. This bit is valid only after th e BIST test is comple te and the BIST DN bit is set.
DS33Z41 Quad IMUX Ethernet Mapper 80 of 167 Register Name: GL.SDRFTC Register Description Global SDRAM Refresh Time Contro l Register Address: 3Dh Bit # 7 6 5 4 3 2 1 0 Name SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 Default 0 1 0 0 0 1 1 0 Bits 7 to 0: SDRAM Refresh Tim e Control (SREFT7 to SREF T0).
DS33Z41 Quad IMUX Ethernet Mapper 81 of 167 9.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles req uests from the HDLC and MAC to transfer data to/from the SDRAM.
DS33Z41 Quad IMUX Ethernet Mapper 82 of 167 9.4 BERT Registers Register Name: BCR Register Description: BERT Control Register Register Address: 80h Bit # 7 6 5 4 3 2 1 0 Name — PMU RNPL RPIC MPR APRD TNPL TPIC Default 0 0 0 0 0 0 0 0 Bit 7: This bit must be kept lo w for proper operation.
DS33Z41 Quad IMUX Ethernet Mapper 83 of 167 Register Name: BPCLR Register Description: BERT Patte rn Configuration Lo w Register Register Address: 82h Bit # 7 6 5 4 3 2 1 0 Name — QRSS PTS PLF4 PLF3.
DS33Z41 Quad IMUX Ethernet Mapper 84 of 167 Register Name: BSPB0R Register Description: BERT Patte rn Byte 0 Regi ster Register Address: 84h Bit # 7 6 5 4 3 2 1 0 Name BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: BERT Pattern (BSP7 to BPS0).
DS33Z41 Quad IMUX Ethernet Mapper 85 of 167 Register Name: TEICR Register Description: Transmit Error Insertion Control Register Register Address: 88h Bit # 7 6 5 4 3 2 1 0 Name — — TIER2 TIER1 TIER0 BEI TSEI — Default 0 0 0 0 0 0 0 0 Bits 5 to 3: Transmit Err or In sertion Rate (TEIR2 to TEIR0).
DS33Z41 Quad IMUX Ethernet Mapper 86 of 167 Register Name: BSRL Register Description: BERT Status Register La tched Register Address: 8Eh Bit # 7 6 5 4 3 2 1 0 Name — — — — PMSL BEL BECL OOSL Default — — — — — — — — Bit 3: Performance Monitor Update Status Latched (PMSL).
DS33Z41 Quad IMUX Ethernet Mapper 87 of 167 Register Name: RBECB0R Register Description: Receiv e Bit Error Count Byte 0 Regis ter Register Address: 94h Bit # 7 6 5 4 3 2 1 0 Name BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Bit Error Count (BEC7 to BEC0).
DS33Z41 Quad IMUX Ethernet Mapper 88 of 167 Register Name: RBCB 1 Register Description: Receiv e Bit Count Byte 1 Register #1 Register Address: 99h Bit # 7 6 5 4 3 2 1 0 Name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Bit Count (BC 15 to BC8).
DS33Z41 Quad IMUX Ethernet Mapper 89 of 167 9.5 Serial Interface Registers The Serial Interface contains the Se ri al HDLC transport circuitry and the associated serial port. The Serial Interface register map consist s of registers that are co mmon functions, transmit functions, and receive functions.
DS33Z41 Quad IMUX Ethernet Mapper 90 of 167 9.5.3 Transmit HDLC Processor Registers Register Name: LI.TPPCL Register Description: Transmit Packet Pro cessor Control Lo w Register Register Address: 0C4.
DS33Z41 Quad IMUX Ethernet Mapper 91 of 167 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Ga pping Control Register Register Address: 0C5h Bit # 7 6 5 4 3 2 1 0 Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0 Default 0 0 0 0 0 0 0 1 Bits 7 to 0: Transmit Inter-Frame Gapping (TIFG7 to TIFG0).
DS33Z41 Quad IMUX Ethernet Mapper 92 of 167 Register Name: LI.TEPHC Register Description: Transmit Errored Pack et High Control Register Register Address: 0C7h Bit # 7 6 5 4 3 2 1 0 Name MEIMS TPER6 TPER5 TPER 4 TPER3 TPER2 TPER1 TPER0 Default 0 0 0 0 0 0 0 0 Bit 7: Manual Error Inse rt Mode Select (MEIMS).
DS33Z41 Quad IMUX Ethernet Mapper 93 of 167 Register Name: LI.TPPSR Register Description: Transmit Packet Pro cessor Status Register Register Address: 0C8h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — TEPF Default 0 0 0 0 0 0 0 0 Bit 0: Transmit Errored Packe t Insertion Finished (TEPF).
DS33Z41 Quad IMUX Ethernet Mapper 94 of 167 Register Name: LI.TPCR0 Register Description: Transmit Packet Count By te 0 Register Address: 0CCh Bit # 7 6 5 4 3 2 1 0 Name TPC7 TPC6 TPC5 TPC4 TPC3 TPC2 TPC1 TPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Transmit Packet Count (TPC7 to TP C0).
DS33Z41 Quad IMUX Ethernet Mapper 95 of 167 Register Name: LI.TBCR0 Register Description: Transmit By t e Count Byte 0 Register Address: 0D0h Bit # 7 6 5 4 3 2 1 0 Name TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Transmit Byte Count (TBC7 to TBC0 ).
DS33Z41 Quad IMUX Ethernet Mapper 96 of 167 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — TPMUU Default 0 0 0 0 0 0 0 0 Bit 0: Transm it PMU Update (TPMU U ).
DS33Z41 Quad IMUX Ethernet Mapper 97 of 167 9.5.4 X.86 Registers X.86 Transmit and commo n Registers are used to cont rol the operation of the X.86 encoder and decoder.
DS33Z41 Quad IMUX Ethernet Mapper 98 of 167 Register Name: LI.TRX86SAPIL Register Description: Transmit Receiv e X.86 SAPIL Register Address: 0DCh Bit # 7 6 5 4 3 2 1 0 Name TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 T RSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPIL0 Default 0 0 0 0 0 0 0 1 Bits 7 to 0: X86 Transmit Receiv e Control (TRSAPIL7 to TRSAPIL0).
DS33Z41 Quad IMUX Ethernet Mapper 99 of 167 9.5.5 Receive Serial Interface Serial Receive Re gisters are used to control the HDLC Rece iver associated with each Se rial Interface. Note that throughout this document HDLC Processor is also re ferred to as “Packet Processor”.
DS33Z41 Quad IMUX Ethernet Mapper 100 of 167 Register Name: LI.RMPSCH Register Description: Receiv e Max imum Packet Size Control High Register Register Address: 103h Bit # 7 6 5 4 3 2 1 0 Name RMX15 RMX14 RMX13 RMX 12 RMX11 RMX10 RMX9 RMX8 Default 0 0 0 0 0 1 1 1 Bits 7 to 0: Receiv e Maximum Packet Size (RMX15 to RMX8).
DS33Z41 Quad IMUX Ethernet Mapper 101 of 167 Register Name: LI.RPPSRL Register Description: Receiv e Packet Processor Status Register Latch ed Register Address: 105h Bit # 7 6 5 4 3 2 1 0 Name REPL RAPL RIPDL RSPDL RLPDL REPCL RAPCL RSPCL Default — — — — — — — — Bit 7: Receiv e FCS Errored Packet Latc hed (REPL).
DS33Z41 Quad IMUX Ethernet Mapper 102 of 167 Register Name: LI.RPPSRIE Register Description: Receiv e Packet Processor Status Register Interrupt Enable Register Address: 106h Bit # 7 6 5 4 3 2 1 0 Name REPIE RAPIE RIPDIE RSPDIE RLPDIE REPCIE RAPCIE RSPCIE Default 0 0 0 0 0 0 0 0 Bit 7: Receiv e FCS Errored Pack et Interrupt Enable (REPIE).
DS33Z41 Quad IMUX Ethernet Mapper 103 of 167 Register Name: LI.RPCB0 Register Description: Receiv e Packet Count Byte 0 Register Register Address: 108h Bit # 7 6 5 4 3 2 1 0 Name RPC7 RPC6 RPC5 RPC4 RPC3 RPC2 RPC1 RPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Packet Count (RP C7 to RPC0).
DS33Z41 Quad IMUX Ethernet Mapper 104 of 167 Register Name: LI.RFPCB0 Register Description: Receiv e FCS Errored Packet Count Byte 0 Register Register Address: 10Ch Bit # 7 6 5 4 3 2 1 0 Name RFPC7 RFPC6 RFPC5 RFPC4 RFPC3 RFPC2 RFPC1 RFPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive FCS Errored Packet Count (RFPC7 to RFP C 0).
DS33Z41 Quad IMUX Ethernet Mapper 105 of 167 Register Name: LI.RAPCB0 Register Description: Receiv e Aborted Packet Count Byte 0 Register Register Address: 110h Bit # 7 6 5 4 3 2 1 0 Name RAPC7 RAPC6 RAPC5 RAPC4 RAPC3 RAPC2 RAPC1 RAPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Aborted P ack et Count (RAPC7 to RAPC0).
DS33Z41 Quad IMUX Ethernet Mapper 106 of 167 Register Name: LI.RSPCB0 Register Description: Receiv e Size Violation Packet Count By te 0 Register Register Address: 114h Bit # 7 6 5 4 3 2 1 0 Name RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receiv e Siz e Violat ion Packet Count (RSPC7 to RSPC0).
DS33Z41 Quad IMUX Ethernet Mapper 107 of 167 Register Name: LI.RBC0 Register Description: Receive By t e Count 0 Register Register Address: 118h Bit # 7 6 5 4 3 2 1 0 Name RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Byte Count (RBC7 to RBC0).
DS33Z41 Quad IMUX Ethernet Mapper 108 of 167 Register Name: LI.RAC0 Register Description: Receive Aborted By te Count 0 Register Register Address: 11Ch Bit # 7 6 5 4 3 2 1 0 Name REBC7 REBC6 REBC5 REBC4 REBC3 REBC2 REBC1 REBC0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Receive Aborted Byte Count (RBC7 to RBC0 ).
DS33Z41 Quad IMUX Ethernet Mapper 109 of 167 Register Name: LI.RHPMUU Register Description: Serial Interface Receiv e HDLC PMU Update Regi ster Register Address: 120h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — RPMUU Default 0 0 0 0 0 0 0 0 Bit 0: Receive PMU Update (RPMUU).
DS33Z41 Quad IMUX Ethernet Mapper 110 of 167 Register Name: LI.RX86LSIE Register Description: Receiv e X.86 Interrupt Enable Register Address: 123h Bit # 7 6 5 4 3 2 1 0 Name — — — — SAPINE01IM SAPINEFEIM CNE3LIM ANE4IM Default 0 0 0 0 0 0 0 0 Bit 3: SAPI Octet Not Equal to LI.
DS33Z41 Quad IMUX Ethernet Mapper 111 of 167 Register Name: LI.TQHT Register Description: Serial Interface Transmit Queue High Threshold (Watermark) Register Address: 125h Bit # 7 6 5 4 3 2 1 0 Name TQHT7 TQHT6 TQHT5 TQHT4 TQHT3 TQHT2 TQHT1 TQHT0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Transmit Queue High Threshold (T QHT7 to TQTH0).
DS33Z41 Quad IMUX Ethernet Mapper 112 of 167 9.6 Ethernet Interface Registers The Ethernet Interface registers are used to configur e RMII/MII bus operation and es tablish the MAC parameters as required by the user. Th e MAC Registers cannot be addr essed directly from the Processor port.
DS33Z41 Quad IMUX Ethernet Mapper 113 of 167 Register Name: SU.MAC RD1 Register Description: MAC Rea d Data By te 1 Register Address: 143h Bit # 7 6 5 4 3 2 1 0 N a m e MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 M A C R D 9 M A C R D 8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: MAC Read Data By te 1 (MACRD15 to MACRD8).
DS33Z41 Quad IMUX Ethernet Mapper 114 of 167 Register Name: SU.MACWD1 Register Description: MAC Write D ata Byte 1 Register Address: 147h Bit # 7 6 5 4 3 2 1 0 N a m e MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: MAC Write Data By te 1 (MACWD15 to MACWD08 ).
DS33Z41 Quad IMUX Ethernet Mapper 115 of 167 Register Name: SU.MAC AWH Register Description: MAC Addres s Write High Register Address: 14Bh Bit # 7 6 5 4 3 2 1 0 N a m e MACAW 15 MACAW 14 MA CAW 13 MACAW12 MACAW11 MACAW10 M A C A W 9 M A C A W 8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: MAC Write Address (MACAW15 to MAC AW8).
DS33Z41 Quad IMUX Ethernet Mapper 116 of 167 Register Name: SU.LPBK Register Description: Ethernet Inte rface Loopback Contr ol Register Register Address: 14Fh Bit # 7 6 5 4 3 2 1 0 Name — — — — — — — QLP Default 0 0 0 0 0 0 0 0 Bit 0: Queue Loopback E nable (QLP).
DS33Z41 Quad IMUX Ethernet Mapper 117 of 167 Register Name: SU.TFRC Register Description: Transmit Fra me Resend Control Register Address: 151h Bit # 7 6 5 4 3 2 1 0 Name — — — — NCFQ TPDFCB TPRHBC TPRCB Default 0 0 0 0 0 0 0 0 Bit 3: No Carrier Queue Flush Bar ( N CFQ).
DS33Z41 Quad IMUX Ethernet Mapper 118 of 167 Register Name: SU.TFSL Register Description: Transmit Fra me Status Lo w Register Address: 152h Bit # 7 6 5 4 3 2 1 0 Name UR EC LC ED LOC NOC — FABORT Default 0 0 0 0 0 0 0 0 Bit 7: Under Run (UR).
DS33Z41 Quad IMUX Ethernet Mapper 119 of 167 Register Name: SU.RFSB0 Register Description: Receiv e Fra me Status Byte 0 Register Address: 154h Bit # 7 6 5 4 3 2 1 0 Name FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Frame Length (FL7 to FL 0).
DS33Z41 Quad IMUX Ethernet Mapper 120 of 167 Register Name: SU.RFSB3 Register Description: Receiv e Fra me Status Byte 3 Register Address: 157h Bit # 7 6 5 4 3 2 1 0 Name MF — — BF MCF UF CF LE Default 0 0 0 0 0 0 0 0 Bit 7: Missed Frame (MF) . This bit is set to 1 if the packet is n o t successfully received from the MAC by the packet Arbiter.
DS33Z41 Quad IMUX Ethernet Mapper 121 of 167 Register Name: SU.RMFSRL Register Description: Receiv er Ma ximum Frame Low Register Register Address: 158h Bit # 7 6 5 4 3 2 1 0 Name RMPS7 RMPS6 RMPS5 RMPS4 RMPS3 RMPS2 RMPS1 RMPS0 Default 1 1 1 0 0 0 0 0 Bits 7 to 0: Rec e iver Maximum Frame (RMPS7 to RMPS0).
DS33Z41 Quad IMUX Ethernet Mapper 122 of 167 Register Name: SU.QRIE Register Description: Receiv e Que ue Cross Threshold Enable Register Address: 15Ch Bit # 7 6 5 4 3 2 1 0 Name — — — — RFOVFIE RQVFIE RQLTIE RQHTIE Default 0 0 0 0 0 0 0 0 Bit 3: Receiv e FIFO Overflo w Interrupt Enable (RFOVFIE).
DS33Z41 Quad IMUX Ethernet Mapper 123 of 167 Register Name: SU.RFRC Register Description: Receiv e Fra me Rejection Control Register Address: 15Eh Bit # 7 6 5 4 3 2 1 0 Name — UCFR CFRR LERR CRCERR DBR MIIER BFR Default 0 0 0 0 0 0 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR).
DS33Z41 Quad IMUX Ethernet Mapper 124 of 167 9.6.2 MAC Registers The control registe rs related to the control of the in di vidual MACs are shown in the following table s. The DS33Z41 keeps statistics for the pa cket traffic sent and received. T he register addre ss map is shown in the following Table.
DS33Z41 Quad IMUX Ethernet Mapper 125 of 167 Bit 12: Late Collisi on Control (LCC). When set to 1, enables retransmi ssion of a collided packet even after the collision period. When this bit is clea r, retr ansmission of late collisions is disabled . Bit 10: Disable Retry (DRTY).
DS33Z41 Quad IMUX Ethernet Mapper 126 of 167 Register Name: SU.MAC AH Register Description: MAC Addr ess High Register Register Address: 0004h (indirect) 0004h: Bit # 31 30 29 28 27 26 25 24 Name Rese.
DS33Z41 Quad IMUX Ethernet Mapper 127 of 167 Register Name: SU.MACMIIA Register Description: MAC MII Managemen t (MDIO) Address Register Register Address: 0014h (indirect) 0014h: Bit # 31 30 29 28 27 .
DS33Z41 Quad IMUX Ethernet Mapper 128 of 167 Register Name: SU.MACMIID Register Description: MAC MII (MD IO) Data Register Register Address: 0018h (indirect) 0018h: Bit # 31 30 29 28 27 26 25 24 Name .
DS33Z41 Quad IMUX Ethernet Mapper 129 of 167 Register Name: SU.MAC FCR Register Description: MAC Flo w Control Register Register Address: 001Ch (indirect) 001Ch: Bit # 31 30 29 28 27 26 25 24 Name PT1.
DS33Z41 Quad IMUX Ethernet Mapper 130 of 167 Register Name: SU.MMCCTRL Register Description: MAC MMC C ontrol Register Register Address: 0100h (indirect) 0100h: Bit # 31 30 29 28 27 26 25 24 Name Rese.
DS33Z41 Quad IMUX Ethernet Mapper 131 of 167 Register Name: Reserved Register Description: MAC Res erved Control Register Register Address: 010Ch (indirect) 010Ch: Bit # 31 30 29 28 27 26 25 24 Name R.
DS33Z41 Quad IMUX Ethernet Mapper 132 of 167 Register Name: Reserved Register Description: MAC Res erved Control Register Register Address: 0110h (indirect) 0110h: Bit # 31 30 29 28 27 26 25 24 Name R.
DS33Z41 Quad IMUX Ethernet Mapper 133 of 167 Register Name: SU.RxFrmCtr Register Description: MAC All Fra mes Received Coun ter Register Address: 0200h (indirect) 0200h: Bit # 31 30 29 28 27 26 25 24 .
DS33Z41 Quad IMUX Ethernet Mapper 134 of 167 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counte r Register Address: 0204h (indirect) 0204h: Bit # 31 30 29 28 27 26 25 24 .
DS33Z41 Quad IMUX Ethernet Mapper 135 of 167 Register Name: SU.TxFrmCtr Register Description: MAC All Fra mes Transmitted Coun ter Register Address: 0300h (indirect) 0300h: Bit # 31 30 29 28 27 26 25 .
DS33Z41 Quad IMUX Ethernet Mapper 136 of 167 Register Name: SU.TxBytesCtr Register Description: MAC All By t es Transmitted Counter Register Address: 0308h (indirect) 0308h: Bit # 31 30 29 28 27 26 25.
DS33Z41 Quad IMUX Ethernet Mapper 137 of 167 Register Name: SU.TxBytesOkCtr Register Description: MAC Bytes Transmitted OK Counter Register Address: 030Ch (indirect) 030Ch: Bit # 31 30 29 28 27 26 25 .
DS33Z41 Quad IMUX Ethernet Mapper 138 of 167 Register Name: SU.TXFRMUNDR Register Description: MAC Trans mit Frame Under Run Counter Register Address: 0334h (indirect) 0334h: Bit # 31 30 29 28 27 26 2.
DS33Z41 Quad IMUX Ethernet Mapper 139 of 167 Register Name: SU.TxBdFrmCtr Register Description: MAC All Fra mes Aborted Counter Register Address: 0338h (indirect) 0338h: Bit # 31 30 29 28 27 26 25 24 .
DS33Z41 Quad IMUX Ethernet Mapper 140 of 167 10 FUNCTIONA L TIMING 10.1 MII and RMII Interfaces Each MII Interfa ce Transmit Port ha s its own TX_C LK and data interface. The data TXD [3:0] operates synchronously with TX_C LK. The LSB is presented first.
DS33Z41 Quad IMUX Ethernet Mapper 141 of 167 Receive Data (RXD[3:0]) is clocked from the extern al PHY synchronously with RX_CLK. T he RX_CLK signal is 2.
DS33Z41 Quad IMUX Ethernet Mapper 142 of 167 11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Resp ect to V SS (except V DD )…………………………………… …….–0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to V SS .
DS33Z41 Quad IMUX Ethernet Mapper 143 of 167 Note 1: Typical power is 145mW. Note 2: All outputs loaded with rated capacit ance; all inputs between VDD and VSS; inputs with pullups connected to V DD . Note 3: RST pin held low, or RST bit set. Note 4: RST pin held low, or RST bit set.
DS33Z41 Quad IMUX Ethernet Mapper 144 of 167 11.2 MII Interface Table 11-5. Transmit MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD, TX_EN Delay t4 0 20 0 20 ns Figure 11-1.
DS33Z41 Quad IMUX Ethernet Mapper 145 of 167 Table 11-6. Receive MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD, RX_DV to RX_CLK Setup Time t8 5 5 ns RX_CLK to RXD, RX_DV Hold Time t9 5 5 ns Figure 11-2.
DS33Z41 Quad IMUX Ethernet Mapper 146 of 167 11.3 RMII Interface Table 11-7. Transmit RMII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz ± 50ppm 50MH.
DS33Z41 Quad IMUX Ethernet Mapper 147 of 167 Table 11-8. Receive RMII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequence 50MHz ± 50ppm 50MHz ± 50ppm MHz REF_CL.
DS33Z41 Quad IMUX Ethernet Mapper 148 of 167 11.4 MDIO Interface Table 11-9. MDIO Interface PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 10 ns MDIO Hold Time t6 20 ns Figure 11-5.
DS33Z41 Quad IMUX Ethernet Mapper 149 of 167 11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS TCLKI Frequency 52 MHz TCLKI Period t1 19.2 ns TCLKI Low Time t2 8 ns TCLKI High Time t3 8 ns TCLKI to TSER Output Delay t4 3 10 ns TSYNC Setup Time t5 3.
DS33Z41 Quad IMUX Ethernet Mapper 150 of 167 11.6 Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19.2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSER Setup Time t4 7 ns RSYNC Setup Time t4 7 ns RSER Hold Time t5 2 ns RSYNC Hold Time t5 2 ns Figure 11-7.
DS33Z41 Quad IMUX Ethernet Mapper 151 of 167 11.7 SDRAM Timing Table 11-12. SDRAM Interface Timing 100MHz PARAMETER SYMBOL MIN TYP MAX UNITS SDCLKO Period t1 9.
DS33Z41 Quad IMUX Ethernet Mapper 152 of 167 Figure 11-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) t1 SDATA (input) S RAS , S CAS , S WE , S DC S (output) t2 t3 t5 t6 t7 t8 t10 t9 SDA, SB.
DS33Z41 Quad IMUX Ethernet Mapper 153 of 167 Figure 11-9. Receive IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Data on unused ch annels must be filled with all ones.
DS33Z41 Quad IMUX Ethernet Mapper 154 of 167 Figure 11-10. Transmit IBO Ch annel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Unused chann els filled with FFh.
DS33Z41 Quad IMUX Ethernet Mapper 155 of 167 11.8 Microprocessor Bus AC Characteristics Table 11-13. AC Characteristi cs—Microprocessor Bus Timing (VDD3.
DS33Z41 Quad IMUX Ethernet Mapper 156 of 167 Figure 11-11. Intel Bus Read Timing (MODEC = 00) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12: 0] DAT A[7 :0] CS RD WR t1 Figure 11-12.
DS33Z41 Quad IMUX Ethernet Mapper 157 of 167 Figure 11-13. Motorola Bus Read Timing (MODEC = 01) t2 t3 Address Va lid Data Valid t4 t9 t5 t10 ADD R[ 12: 0] DAT A[7 :0] CS DS RW t1 Figure 11-14.
DS33Z41 Quad IMUX Ethernet Mapper 158 of 167 11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%, VDD1.8 = 1.8V ± 5%, Tj = -40 ° C to +85 ° C.
DS33Z41 Quad IMUX Ethernet Mapper 159 of 167 12 JTAG INFORMATION The device supports the st andard instruction code s SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.
DS33Z41 Quad IMUX Ethernet Mapper 160 of 167 12.1 JTAG TAP Controller State Machine Descr iption This section covers the det ails on the operation of the Te st A ccess Po rt (TAP) Contro ller State Machine. The TAP controller is a finite state machine that respo n ds to the logic level at JTMS on the rising edge of JTCLK.
DS33Z41 Quad IMUX Ethernet Mapper 161 of 167 Update-DR A falling edge on JTCLK while in the Update-DR state will la tch the data from the shift register path of the test registers into the data output latche s. This prevents change s at the parallel output due to changes in the shift register.
DS33Z41 Quad IMUX Ethernet Mapper 162 of 167 Figure 12-2. TAP Controller State Diagram 12.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters t he Shift-IR state, the instruct ion shift register is co nnected between JTDI and JTDO.
DS33Z41 Quad IMUX Ethernet Mapper 163 of 167 Table 12-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGI STER INSTRUCTION CODES SAMPLE:PRELOAD Boundary Scan 010 BYPASS Bypass 111 EXTEST Boundary Scan 000 CLAMP Bypass 011 HIGHZ Bypass 100 IDCODE Device Identification 001 12.
DS33Z41 Quad IMUX Ethernet Mapper 164 of 167 12.3 JTAG ID Codes Table 12-2. ID Code Structure DEVICE REVISION ID[31:28 ] DEVICE CODE ID[27:12 ] MANUFACTURE R’S CODE ID[11:1] REQUIRED ID[0] DS33Z41 0000 0000 0000 0110 0010 000 1010 0001 1 12.4 Test Registers IEEE 1149.
DS33Z41 Quad IMUX Ethernet Mapper 165 of 167 12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from re set state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.
DS33Z41 Quad IMUX Ethernet Mapper 166 of 167 13 PACKAGE INFORMATION (The package dra wing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.
DS33Z41 Quad IMUX Ethernet Mapper 167 of 167 Maxim/Dallas Semiconductor cannot assume re s ponsibility for use of any circuitry other than circ uitry entirely embodied in a Ma xim/Dallas Semiconductor product.
An important point after buying a device Maxim DS33Z41 (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
If you have not bought Maxim DS33Z41 yet, this is a good time to familiarize yourself with the basic data on the product. First of all view first pages of the manual, you can find above. You should find there the most important technical data Maxim DS33Z41 - thus you can check whether the hardware meets your expectations. When delving into next pages of the user manual, Maxim DS33Z41 you will learn all the available features of the product, as well as information on its operation. The information that you get Maxim DS33Z41 will certainly help you make a decision on the purchase.
If you already are a holder of Maxim DS33Z41, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Maxim DS33Z41.
However, one of the most important roles played by the user manual is to help in solving problems with Maxim DS33Z41. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Maxim DS33Z41 along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
