Instruction/ maintenance manual of the product MultiProcessor Intel
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MultiProcessor Specification Version 1. 4 May 1997.
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. A license is hereby granted to copy and reproduce this specification for internal use only.
iii Revision History Revision Revision History Date Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93 -001 Version 1.1. Resolves conflicts with MCA-based systems.
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v Table of Contents Chapter 1 Introduction 1.1 Goals ........................................................................................................ 1-1 1.2 Features of the Specification .......................................................
Contents vi 3.6.6 APIC Identification ..................................................................... 3-13 3.6.7 APIC Interval Timers .................................................................. 3-13 3.6.8 Multiple I/O APIC Configurations .
Contents vii Appendix A System BIOS Programming Guidelines A.1 BIOS Post Initialization ............................................................................ A-1 A.2 Controlling the Application Processors .......................................
Contents viii Figures 1-1. Conceptual Overview ...................................................................... 1-1 1-2. Memory Layout Conventions .......................................................... 1-4 2-1. Multiprocessor System Architecture.
Contents ix 4-6. Feature Flags from CPUID Instruction ............................................ 4-9 4-7. Bus Entry Fields ............................................................................ 4-10 4-8. Bus Type String Values.................
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Version 1.4 1-1 1 Introduction The MultiProcessor Specification, hereafter known as the “MP specification,” defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification.
MultiProcessor Specification 1-2 Version 1.4 1.2 Features of the Specification The MP specification includes the following features: • A multiprocessor extension to the PC/AT platform that runs all existing uniprocessor shrink- wrapped binaries, as well as MP binaries.
Introduction Version 1.4 1-3 In addition to the hardware requirements, this document also specifies MP features that are visible to the BIOS and operating system. However, it is important to understand that as hardware technology progresses, the functions performed by the BIOS may change in accordance with the hardware technology.
MultiProcessor Specification 1-4 Version 1.4 1.6 Conventions Used in This Document Signal names that are followed by the character # represent active low signals. For example, FERR# is active when at its low-voltage state. Throughout this document, the Intel 82489DX APIC is referred to as the “discrete APIC.
Version 1.4 2-1 2 System O verview In the realm of multiprocessor architectures, there are several conceptual models for tying together computing elements, and there are a variety of interconnection schemes and details of implementation. Figure 2-1 shows the general structure of a design based on the MP specification.
MultiProcessor Specification 2-2 V ersion 1.4 HIGH-BANDWIDTH MEMORY BUS API C ADV ANCE D P RO G RAM M ABL E I NTE RRUPT C O NTROL LE R I CC I NTE RRUPT C O NTROL LE R COM M UNI CATI ONS CPU CPU CPU SHARED MEMORY MODULE GRAPHICS FRAME BUFFER I/O INTERFACE APIC I/O INTERFACE APIC ICC BUS I/O EXPANSION BUS I/O EXPANSION BUS Figure 2-1.
System Overview Version 1.4 2-3 only during the initialization and shutdown processes. The BSP is responsible for initializing the system and for booting the operating system; APs are activated only after the operating system is up and running. CPU1 is designated as the BSP.
MultiProcessor Specification 2-4 V ersion 1.4 The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to interrupt any other processor or set of processors. There are several types of IPIs. Among them, the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown.
System Overview Version 1.4 2-5 2.2 BIOS Overview A BIOS functions as an insulator between the hardware on one hand, and the operating system and applications software on the other. A standard uniprocessor BIOS performs the following functions: • Tests system components.
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Version 1.4 3-1 3 Hardware Specificat ion This section outlines the minimal set of common hardware features necessary for the operating system to operate on multiple hardware platforms. The MP hardware specification defines how the components mentioned in Chapter 2 are implemented.
MultiProcessor Specification 3-2 V ersion 1.4 SYST EM- BASED MEMO R Y VIDE O BUFFER ROM EX TEN SIONS EXPANSION ROM SHAD OWE D EXPANSIO N BIO S SHAD OWE D BIO S EXT END ED ME MO R Y R EG IO N I/O APIC .
Hardware Specification Version 1.4 3-3 Table 3-1. Memory Cacheability Map Addresses (in hex) Size Description Shared by All Processors? Cacheable? Comment 0000_0000h – 0009_FFFFh 640KB Main memory Y.
MultiProcessor Specification 3-4 V ersion 1.4 3.3 External Cache Subsystem Intel-compatible processors support multiprocessing both on the processor bus and on a memory bus, both with and without secondary cache units. Due to the high bandwidth demands of multiprocessor systems, external caches are often employed to improve performance.
Hardware Specification Version 1.4 3-5 operations over its internal shared memory bus, if it is AT compatible. Operating system and software developers must ensure that data is aligned if locked access is required, because lock operations on misaligned data are not guaranteed to work on all platforms .
MultiProcessor Specification 3-6 V ersion 1.4 Table 3-2. APIC Versions APIC Type Local APIC Version Register (hexadecimal) Integrated APIC Features 82489DX APIC 0x Integrated APIC, i.e., Pentium processors (73590, 815100) 1x STARTUP IPI. See Appendix B.
Hardware Specification Version 1.4 3-7 The first two interrupt modes, PIC Mode and Virtual Wire Mode, provide PC/AT-compatibility. At least one of these modes must be implemented in systems that comply with the MP specification.
MultiProcessor Specification 3-8 V ersion 1.4 LINTIN0 LINTIN1 NMI NMI INTR CPU 1 LINTIN0 LINTIN1 LINTIN0 LINTIN1 NMI INTR CPU 2 NMI INTR CPU 3 REG. MARK BSP AP1 AP2 LOCAL APIC 1 LOCAL APIC 2 LOCAL APIC 3 RESE T LINTIN 0 LINTIN1 ICC BUS IMCR E0 INTR I/O APIC 8259A- EQUIVALENT PICS INTERRUPT INPUTS SHADED AREAS INDICATE UNUSED CIRCUITS.
Hardware Specification Version 1.4 3-9 3.6.2.2 Virtual Wire Mode Virtual Wire Mode provides a uniprocessor hardware environment capable of booting and running all DOS shrink-wrapped software.
MultiProcessor Specification 3-10 V ersion 1.4 Figure 3-3 shows how Virtual Wire Mode can be implemented through the BSP’s local APIC. It is also permissible to program the I/O APIC for Virtual Wire Mode, as shown in Figure 3-4. In this case the interrupt signal passes through both the I/O APIC and the BSP’s local APIC.
Hardware Specification Version 1.4 3-11 3.6.2.3 Symmetric I/O Mode Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt lines are either masked or work together with the I/O APIC in a mixed mode.
MultiProcessor Specification 3-12 V ersion 1.4 3.6.3 Assignment of System Interrupts to the APIC Local Unit The APIC local unit has two general-purpose interrupt inputs, which are reserved for system interrupts. These interrupt inputs can be individually programmed to different operating modes.
Hardware Specification Version 1.4 3-13 3.6.6 APIC Identification Systems developers must assign APIC local unit IDs and ensure that all are unique. There are two acceptable ways to assign local APIC IDs, as follows: • By hardware. The ID of each APIC local unit is sampled from the appropriate pins at RESET.
MultiProcessor Specification 3-14 V ersion 1.4 REG. MARK I/O APIC 1 8259A- EQUIVALENT PICS NON-ISA INTERRUPT INTERRUPT ROUTING NETWORK I/O APIC 2 ICC BUS INTR/LINT0 ISA INTERRUPT Figure 3-6.
Hardware Specification Version 1.4 3-15 or by the front panel reset button (if the system is so equipped). This type of reset operates without regard to cycle boundaries, and, for example, is connected to the RESET pin of Pentium processors.
MultiProcessor Specification 3-16 V ersion 1.4 3.8 System Initial State The system initial state is the state before the BIOS gives control to the operating system. It is identical to the system initial state of a typical PC/AT system, with the additional MP components in the following state: 1.
Version 1.4 4-1 4 MP Configuration Table The operating system must have access to some information about the multiprocessor configuration. The MP specification provides two methods for passing this in.
MultiProcessor Specification 4-2 Version 1.4 The following two data structures are used: 1. The MP Floating Pointer Structure . This structure contains a physical address pointer to the MP configuration table and other MP feature information bytes. When present, this structure indicates that the system conforms to the MP specification.
MP Configuration Table Version 1.4 4- 3 4.1 MP Floating Pointer Structure An MP-compliant system must implement the MP floating pointer structure, which is a variable length data structure in multiples of 16 bytes. Currently, only one 16-byte data structure is defined.
MultiProcessor Specification 4-4 Version 1.4 Table 4-1. MP Floating Pointer Structure Fields (continued) Field Offset (in bytes:bits) Length (in bits) Description MP FEATURE INFORMATION BYTE 1 11 8 Bits 0-7: MP System Configuration Type. When these bits are all zeros, the MP configuration table is present.
MP Configuration Table Version 1.4 4-5 4.2 MP Configuration Table Header Figure 4-3 shows the format of the header of the MP configuration table, and Table 4-2 explains each of the fields.
MultiProcessor Specification 4-6 Version 1.4 Table 4-2. MP Configuration Table Header Fields Field Offset (in bytes) Length (in bits) Description SIGNATURE 0 3 2 The ASCII string representation of “PCMP,” which confirms the presence of the table.
MP Configuration Table Version 1.4 4-7 Table 4-3. Base MP Configuration Table Entry Types Entry Description Entry Type Code* Length (in bytes) Comments Processor 0 20 One entry per processor. Bus 1 8 One entry per bus. I/O APIC 2 8 One entry per I/O APIC.
MultiProcessor Specification 4-8 Version 1.4 Table 4-4. Processor Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 A value of 0 identifies a processor entry. LOCAL APIC ID 1 8 The local APIC ID number for the particular processor.
MP Configuration Table Version 1.4 4-9 Table 4-5. Intel486 and Pentium Processor Signatures Family Model Stepping a Description 0000 0000 0000 Not a valid CPU signature.
MultiProcessor Specification 4-10 Version 1.4 4.3.2 Bus Entries Bus entries identify the kinds of buses in the system. Because there may be more than one bus in a system, each bus is assigned a unique bus ID number by the BIOS. The bus ID number is used by the operating system to associate interrupt lines with specific buses.
MP Configuration Table Version 1.4 4-11 Table 4-8. Bus Type String Values Bus Type String Description CBUS Corollary CBus CBUSII Corollary CBUS II EISA Extended ISA FUTURE IEEE FutureBus INTERN Intern.
MultiProcessor Specification 4-12 Version 1.4 4.3.3 I/O APIC Entries The configuration table contains one or more entries for I/O APICs. Figure 4-6 shows the format of each I/O APIC entry, and Table 4-9 explains each field.
MP Configuration Table Version 1.4 4-13 2. No Interrupt Assignment Entries are declared for any of the bus source interrupts, and the operating system uses some other bus-specific knowledge of bus interrupt schemes in order to support the bus. This operating system bus-specific knowledge is beyond the scope of this specification.
MultiProcessor Specification 4-14 Version 1.4 Table 4-10. I/O Interrupt Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 3 identifies an I/O interrupt entry. INTERRUPT TYPE 1 8 See Table 4-11 for values.
MP Configuration Table Version 1.4 4-15 Table 4-11. Interrupt Type Values Interrupt Type* Description Comments 0 INT Signal is a vectored interrupt; vector is supplied by APIC redirection table. 1 NMI Signal is a nonmaskable interrupt. 2 SMI Signal is a system management interrupt.
MultiProcessor Specification 4-16 Version 1.4 Table 4-12. Local Interrupt Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 4 identifies a local interrupt entry.
MP Configuration Table Version 1.4 4-17 4.4 E xtended MP C onfiguration Table E ntries A variable number of variable-length entries are located in memory, immediately following entries in the base section of the MP configuration table described in Section 4.
MultiProcessor Specification 4-18 Version 1.4 4.4.1 System Address Space Mapping Entries System Address Space Mapping entries define the system addresses that are visible on a particular bus. Each b us defined in the Base Table can have any number of System Address Space Mapping entries included in the Extended Table .
MP Configuration Table Version 1.4 4-19 Table 4-14. System Address Space Mapping Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 128 identifies a System Address Space Mapping Entry. ENTRY LENGTH 1 8 A value of 20 indicates that an entry of this type is twenty bytes long.
MultiProcessor Specification 4-20 Version 1.4 Figure 4-10. Example System with Multiple Bus Types and Bridge Types Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.
MP Configuration Table Version 1.4 4-21 4.4.2 Bus Hierarchy Descriptor Entry If present, Bus Hierarchy Descriptor entries define how I/O buses are connected relative to each other in a system with more than one I/O bus.
MultiProcessor Specification 4-22 Version 1.4 Table 4-15 Bus Hierarchy Descriptor Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 129 identifies a Bus Hierarchy Descriptor Entry. ENTRY LENGTH 1 8 A value of 8 indicates that this entry type is eight bytes long.
MP Configuration Table Version 1.4 4-23 For example, a host bus bridge for a PCI bus that provides ISA compatibility may decode a predefined range of addresses used for ISA device support in addition to the addresses used for PCI devices on that bus.
MultiProcessor Specification 4-24 Version 1.4 Table 4-16. Compatibility Bus Address Space Modifier Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 130 identifies a Compatibility Bus Address Space Modifier Entry.
Version 1.4 5-1 5 Default Configurations The MP specification defines several default MP system configurations. The purpose of these defaults is to simplify BIOS design. If a system conforms to one of the default configurations, the BIOS will not need to provide the MP configuration table.
MultiProcessor Specification 5-2 V ersion 1.4 Table 5-1. Default Configurations Default Config Code Number of CPUs Bus Type APIC Type Variant Schematic 1 2 ISA 82489DX As in Figure 5-1, but without EISA logic. 2 2 EISA 82489DX Neither timer IRQ 0 nor DMA chaining As in Figure 5-1, but without IRQ0 and IRQ13 connection to the I/O APIC.
Default Configurations Version 1.4 5-3 B C D A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 IRQ1 0 1 2 3 4 5 6 7 I/O 82489DX APIC MASTER 8259A PIC SLAVE 8259A PIC IRQ8# 14 15 14 15 8254 TIMER.
MultiProcessor Specification 5-4 V ersion 1.4 The INTA TRAP and GLUE in the figure are the additional hardware interface logic needed for the 82489DX APIC. INTA TRAP conditions all interrupt acknowledge cycles with ExtINTA to steer the vector either from the 8259A PIC or the APIC.
Default Configurations Version 1.4 5-5 A B C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 IRQ1 0 1 2 3 4 5 6 7 I/O APIC MASTER 8259A PIC SLAVE 8259A PIC IRQ8# INT8 14 15 14 15 8254 TIMER 9 10 11 9 10 11 3 4 5 6 7 3 4 5 6 7 INTR NMI REG.
MultiProcessor Specification 5-6 V ersion 1.4 should be cross-connected between the BSP and AP processors. Although the INIT pin is cross- connected between BSP and AP, a targeted INIT IPI initializes only the targeted processor, because the INIT IPI does not cause the INIT pin to change state.
Default Configurations Version 1.4 5-7 Certain EISA chipsets do not bring out the IRQ0, 8254 timer interrupt, and IRQ13 EISA DMA chaining interrupt signals. If these signals are not directly available, INTIN2 and INTIN13 should be disabled. Refer to Section 5.
MultiProcessor Specification 5-8 V ersion 1.4 The 8259A INTR output signal is connected to the LINTIN0 of all local APICs, which makes INTR dynamically routable via software. NMI is connected to the LINTIN1 of all local APICs, which makes NMI dynamically routable via software.
Version 1.4 A-1 A System BIOS Progr amming Guidelines Depending on the MP components in a multiprocessor system, the system BIOS may have the following additional responsibilities: 1. Put the APs to sleep, so that they do not all try to execute the same BIOS code as the BSP.
MultiProcessor Specification A-2 Version 1.4 A.2 Controlling the Application Processors Provision must be made to prevent all processors from executing the BIOS after a power-on RESET. System developers may choose to do this by the hardware alone or by cooperation between hardware and the BIOS.
System BIOS Programming Guidelines Version 1.4 A-3 ;-----------------------------------------------------------------------; ; InitLocalAPIC( ) ; ;-----------------------------------------------------------------------; ; ; ; Initialize the local APIC to virtual wire mode.
MultiProcessor Specification A-4 Version 1.4 mov esi,LVT1 mov eax,[esi] ; read LVT1 and eax,0FFFE 00 FFH ; not masked, edge, active high or eax,00000 5 700H ; ExtInt mov [esi],eax ; write LVT1 ; ; Program LVT2 as NMI, which delivers the signal on the NMI signal of all ; processors' cores listed in the destination.
System BIOS Programming Guidelines Version 1.4 A-5 The BSP is responsible for positioning the MP configuration table. The table can be located within any unreported, hidden system memory space or within the BIOS ROM region. The BIOS can select any unused space in those regions.
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Version 1.4 B-1 B Operat ing System Progr amming Guidelines The goal of the MP specification is to transfer enough information about the hardware environment to the operating system that a single, shrink-wrapped, operating-system binary can boot-up and fully utilize a wide variety of multiprocessor systems.
MultiProcessor Specification B-2 V ersion 1.4 The operating system ’s first task is to determine whether the system conforms to the MP specification.
Operating System Programming Guidelines Version 1.4 B-3 Then the operating system should enable its own local APIC, thereby allowing IPI communications with other APIC-based processors.
MultiProcessor Specification B-4 V ersion 1.4 A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal operating conditions.
Operating System Programming Guidelines Version 1.4 B-5 By putting an appropriate pointer in the warm-reset vector, setting the shutdown code to 0Ah, then causing an INIT, the BIOS (or the operating system) can cause the current processor to jump immediately to any location.
MultiProcessor Specification B-6 V ersion 1.4 of an INIT IPI used to shut down an AP . As a result, the operating system must ensure that any required state information is captured and that caches are flushed as necessary before sending the INIT IPI.
Operating System Programming Guidelines Version 1.4 B-7 interrupt. The distributed APIC architecture, by its nature, is more vulnerable to spurious interrupt, because the device interrupt may be latched and recognized without the INTA cycle.
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Version 1.4 C-1 C System Compliance Checklist Any "NO" answer indicates non-compliance. Condition YES NO 1. PC/AT Compatibility Does system contain all necessary MP-compatible circuitry? Will system boot and run DOS and Microsoft Windows? 2.
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Version 1.4 D-1 D Multiple I/O APIC Multiple PCI Bus Systems The information in this specification describes the majority of multiprocessor systems. This appendix provides clarifications for implementors who are considering designs with more than one I/O APIC.
MultiProcessor Specification D-2 Version 1.4 If IMCR is implemented but the system includes one or more I/O APICs that are not controlled through IMCR, the hardware must accomplish routing changes for such I/O APICs by some other means when the system switches into symmetric I/O mode.
Multiple I/O APIC Multiple PCI Bus Systems Version 1.4 D-3 Fixed interrupt routing also implies a restriction on software that is implicit but important in the context of systems with more than one I/O APIC.
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Version 1.4 E-1 E Errata The following sections provided here are intended to replace the corresponding sections in the main body of the specification.
MultiProcessor Specification E-2 Version 1.4 Table 4-1. MP Floating Pointer Structure Fields Field Offset (in bytes:bits) Length (in bits) Description SIGNATURE 0 32 The ASCII string represented by “_MP_” which serves as a search key for locating the pointer structure.
MP Configuration Table Version 1.4 E-3 information byte 2, the IMCR present bit, is used by the operating system to determine whether PIC Mode or Virtual Wire Mode is implemented by the system. The physical address pointer field contains the address of the beginning of the MP configuration table.
MultiProcessor Specification E-4 Version 1.4 Table 4-14. System Address Space Mapping Entry Fields Field Offset (in bytes:bits) Length (in bits) Description ENTRY TYPE 0 8 Entry type 128 identifies a System Address Space Mapping Entry. ENTRY LENGTH 1 8 A value of 20 indicates that an entry of this type is twenty bytes long.
MP Configuration Table Version 1.4 E-5 Since all device settings must fall within supported System Address Space mapping for a given bus in order to be usable by the operating system, buses that do not support dynamically configurable devices (i.e., ISA, EISA) should support all possible addresses to that bus.
MultiProcessor Specification E-6 Version 1.4 31 0 3 74 8 11 12 15 16 19 20 23 24 27 28 00H 04H ENTRY LENGTH ENT R Y TY PE 129 BUS ID BUS INFO RESER VED PARE NT BU S S D 31 0 3 74 8 11 12 15 16 19 20 23 24 27 28 RESERVED Figure 4-11.
Version 1.4 Glossary-1 Glossary 82489DX: The 82489DX Advanced Programmable Interrupt Controller (APIC). 8259A: The 8259A Programmable Interrupt Controller (PIC) or its equivalent. AP: Application processor, one of the processors not responsible for system initialization.
MultiProcessor Specification Glossary-2 Version 1.4 PIC Mode: One of three interrupt modes defined by the MP specification. In this mode the APICs are effectively disabled, while interrupts are generated by 8259A-equivalent PICs and delivered directly to the BSP.
Order Number: 242016-00 6 Printed in U.S.A..
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