Instruction/ maintenance manual of the product SA14-2339-04 IBM
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P o werPC 405 Embedded Pr ocessor Core User’ s Manual SA14-2339-04.
Fifth Edition (December 2001) This edition of IBM PPC405 Embedded Processor Core User’s Manual applies to the IBM PPC405 32-bit embedded processor core, until otherwise indicated in ne w v ersions or application notes.
P atents and T rademarks IBM ma y hav e patents or pending patent applications cov ering the subject matter in this publication. The furnishing of this publication does not give y ou any license to these patents .
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Contents v Contents Figures ...................................................................................................................................... xv Tables ..............................................................................
vi PPC405 Core User’s Manual The CR0 Field ...................................................................................................................................... 2-12 The Time Base ....................................................
Contents vii Processor Management Instructions ......................................................................................................... 2-42 Extended Mnemonics ..........................................................................
viii PPC405 Core User’s Manual Alignment Interrupt ........................................................................................................................................ 5-19 Program Interrupt ......................................
Contents ix Real-Mode Storage Attribute Control ............................................................................................................. 7-17 Storage Attribute Control Registers ....................................................
x PPC405 Core User’s Manual addc ............................................................................................................................................................ 9-7 adde ..................................................
Contents xi lhau ............................................................................................................................................................ 9-76 lhaux ..................................................................
xii PPC405 Core User’s Manual nmachhw ................................................................................................................................................. 9-135 nmachhws ..................................................
Contents xiii xori ........................................................................................................................................................... 9-199 xoris ................................................................
xiv PPC405 Core User’s Manual Instruction Format Diagrams ..................................................................................................................... A-43 I-Form A-44 B-Form A-44 SC-Form A-44 D-Form A-44 X-Form A-45 XL-Form A-45 XFX-Form A-46 X0-Form A-46 M-Form A-46 B.
Figures xv Figures Figure 1-1. PPC405 Block Diagram ................................................................................................................ 1-4 Figure 2-1. PPC405 Programming Model—Registers .................................
xvi PPC405 Core User’s Manual Figure 8-3. Debug Status Register (DBSR) .................................................................................................... 8-8 Figure 8-4. Instruction Address Compare Registers (IAC1–IAC4) .........
Figures xvii Figure A-1. I Instruction Format ....................................................................................................................A-44 Figure A-2. B Instruction Format ...................................................
xviii PPC405 Core User’s Manual T ables Table 2-1. PPC405 SPRs ................................................................................................................................ 2-6 Table 2-2. XER[CA] Updating Instructions ............
Tables xix Table 5-13. Register Settings during Program Interrupts .............................................................................. 5-21 Table 5-14. Register Settings during FPU Unavailable Interrupts ....................................
xx PPC405 Core User’s Manual Table 9-23. Extended Mnemonics for mtspr ................................................................................................ 9-120 Table 9-24. Extended Mnemonics for nor, nor. ...............................
About This Book xxi About This Book This user’ s man ual provides the architectur al ov erview , programming model, and detailed inf ormation about the registers, the instruction set, and operations of the IBM™ P owerPC™ 405 (PPC405 core) 32-bit RISC embedded processor core.
xxii PPC405 Core User’s Manual T o help readers find material in these chapters, the book contains: Contents, on page v. Figures, on page xv. T ab les, on page xviii. Inde x, on page X-1. Con ventions The f ollowing is a list of notational con v entions frequently used in this manual.
About This Book xxiii FLD b ,b , . . . A list of bits, b y number or name , in a named instruction or register field REG b A bit in a named register REG b:b A range of bits in a named register REG b ,b , . . . A list of bits, b y number or name , in a named register REG[FLD] A field in a named register REG[FLD , FLD .
xxiv PPC405 Core User’s Manual EA b A bit in an eff ectiv e address. EA b:b A range of bits in an eff ectiv e address. RO TL((RS),n) Rotate left; the contents of RS are shifted left the number of bits specified by n . MASK(MB,ME) Mask having 1s in positions MB through ME (wr apping if MB > ME) and 0s elsewhere .
Overview 1-1 Chapter 1. Overview The IBM 405 32-bit reduced instruction set computer (RISC) processor core, ref erred to as the PPC405 core, implements the P o werPC Architecture with e xtensions f or embedded applications .
1-2 PPC405 Core User’s Manual – Instruction cache unit (ICU) non-bloc king during line fills, data cache unit (DCU) non-b locking during line fills and flushes – Read and write line buff ers .
Overview 1-3 1.2 P o werPC Ar chitecture The P o werPC Architecture comprises three le v els of standards: • P o werPC User Instruction Set Architecture (UISA), including the base user-le v el instruction set, user-le v el registers, progr amming model, data types, and addressing modes .
1-4 PPC405 Core User’s Manual 1.4 Pr ocessor Core Organization The processor core consists of a 5-stage pipeline, separate instruction and data cache units, virtual memor y management unit (MMU), three timers, deb ug, and interf aces to other functions.
Overview 1-5 unnecessar y line fills and enabling the ICU to handle the ne xt EXU f etch. Abor ting abandoned requests also eliminates unnecessar y e xter nal bus activity to increase e xternal bus utilization.
1-6 PPC405 Core User’s Manual associativ e; a page entr y can be placed anywhere in the TLB . The translation function of the MMU occurs pre-cache f or data accesses. Cache tags and inde xing use ph ysical addresses f or data accesses; instruction fetches are vir tually inde x ed and ph ysically tagged.
Overview 1-7 The time base is a 64-bit counter incremented either by an internal signal equal to the CPU clock r ate or by a separ ate e xternal timer clock signal. No interrupts are generated when the time base rolls ov er . The PIT is a 32-bit register that is decremented at the same rate as the time base is incremented.
1-8 PPC405 Core User’s Manual 1.4.5.1 Pr ocessor Local Bus The PLB-compliant interf ace provides separ ate 32-bit address and 64-bit data buses f or the instruction and data sides. 1.4.5.2 Device Contr ol Register Bus The De vice Control Register (DCR) bus supports the attachment of on-chip registers for de vice control.
Overview 1-9 significant byte). See “Byte Ordering” on page 2-17 f or more inf or mation about big and little endian operation. 1.4.7 Processor Core Register Set Summary The processor core regist.
1-10 PPC405 Core User’s Manual The mtdcr and mfdcr instructions are pr ivileged, for all DCRs . Theref ore, all accesses to DCRs are privileged. See “Pr ivileged Mode Operation” on page 2-30. All DCR numbers are reserved, and should be neither read nor written, unless they are par t of an IBM Core+ASIC implementation.
Programming Model 2-1 Chapter 2. Programming Model The programming model of the PPC405 embedded processor core describes the f ollowing f eatures and operations: • Memor y organization and addressin.
2-2 PPC405 Core User’s Manual 2.2.1 Storage Attributes The P o werPC Architecture defines stor age attributes that control data and instruction accesses.
Programming Model 2-3 Programming Note: A good coding practice is to perf orm the initial wr ite to a register with reser ved fields as described, and to perf orm all subsequent wr ites to the regist.
2-4 PPC405 Core User’s Manual User Model General-Purpose Registers GPR0 GPR1 GPR31 • • • Condition Register CR Fixed-P oint Exception Register XER Link Register LR Count Register CTR Time Base.
Programming Model 2-5 2.3.1 General Purpose Registers (R0-R31) The PPC405 core contains thir ty-two 32-bit general pur pose registers (GPRs). Data from memor y can be read into GPRs using load instructions and the contents of GPRs can be wr itten to memor y using store instructions.
2-6 PPC405 Core User’s Manual 2.3.2.1 Count Register (CTR) The CTR is written from a GPR using mtspr . The CTR contents can be used as a loop count that is decremented and tested by some br anch instructions. Alter nativ ely , the CTR contents can specify a target address f or the bcctr instruction, enabling branching to an y address.
Programming Model 2-7 2.3.2.2 Link Register (LR) The LR is written from a GPR using mtspr , and by br anch instructions that hav e the LK bit set to 1. Such branch instructions load the LR with the address of the instruction follo wing the branch instruction.
2-8 PPC405 Core User’s Manual Once set, XER[SO] is not reset until an mtspr (XER) is e x ecuted with data that e xplicitly puts a 0 in the SO bit, or until an mcrxr instruction is ex ecuted. XER[O V] is set to indicate whether an instruction that updates XER[O V] produces a result that “ov erflo ws” the 32-bit target register .
Programming Model 2-9 T ab le 2-2 and T able 2-3 list the PPC405 instructions that update the XER. In the tables , the syntax “[ o ]” indicates that the instruction has an “o” form that updates XER[SO ,O V], and a “non-o” form. The syntax “[ .
2-10 PPC405 Core User’s Manual SPRG0–SPRG7 provide tempor ar y storage locations. F or e xample , an interrupt handler might sav e the contents of a GPR to an SPRG, and later restore the GPR from it. This is f aster than perf orming a sav e/restore to memory .
Programming Model 2-11 descriptions in Chapter 9, “Instr uction Set. ” The CR contents can be used in conditional branch instructions. The CR can be modified in any of the f ollo wing wa ys: • mtcrf sets specified CR fields by writing to the CR from a GPR, under control of a mask specified as an instruction field.
2-12 PPC405 Core User’s Manual compares, the v alues are considered to be signed, where 31 bits represent the magnitude and the most-significant bit is a sign bit. F or logical compares, the v alues are considered to be unsigned, so all 32 bits represent magnitude.
Programming Model 2-13 Adding the largest 32-bit twos-complement negativ e number , 0x8000 0000, to itself results in an arithmetic ov erflow and 0x0000 0000 is recorded in the target register . CR[CR0] EQ, SO is set, indicating a result of 0, but the infinitely precise result is negativ e .
2-14 PPC405 Core User’s Manual The MSR contents are automatically sav ed, altered, and restored b y the interrupt-handling mechanism. See “Machine State Register (MSR)” on page 5-7. Figure 2-9. Machine State Register (MSR) 0:5 Reser ved 6 AP A uxiliar y Processor A v ailable 0 APU not av ailable .
Programming Model 2-15 2.3.6 Device Contr ol Register s De vice Control Registers (DCRs), on-chip registers that e xist architecturally outside the processor core, are not par t of the IBM P o werPC Embedded En vironment.
2-16 PPC405 Core User’s Manual 2.4 Data T ypes and Alignment The data types consist of bytes (eight bits), halfw ords (two b ytes), words (f our b ytes), and strings (1 to 128 bytes). Figure 2-10 sho ws the b yte, halfword, and w ord data types and their bit and byte definitions f or big endian representations of v alues.
Programming Model 2-17 Misalignments are addresses that are not naturally aligned on data type boundaries. An address not divisible b y f our is misaligned with respect to word instructions. An address not divisib le b y two is misaligned with respect to halfword instructions.
2-18 PPC405 Core User’s Manual storage , the scalar is stored in f our consecutive b yte addresses . It thus becomes meaningful to discuss the order of the byte addresses with respect to the v alue .
Programming Model 2-19 2.5.1.1 Big Endian Mapping The big endian mapping of structure s f ollows . (The data is highlighted in the structure mappings. Addresses, in he xadecimal, are belo w the data stored at the address.
2-20 PPC405 Core User’s Manual When address translation is enab led (MSR[IR] = 1 or MSR[DR] = 1), the E field in the corresponding TLB entr y controls the endianness of a memor y region. When address translation is disabled (MSR[IR] = 0 or MSR[DR] = 0), the SLER controls the endianness of a memor y region.
Programming Model 2-21 2.5.3.2 Accessing Data in Little Endian Storage Regions Unlike instruction f etches from little endian storage regions , data accesses from little endian storage regions are not byte-re v ersed betw een memor y and the DCU .
2-22 PPC405 Core User’s Manual Figure 2-11 illustrates the contents of a GPR and memory (star ting at address 00) after a nor mal load/store in a big endian storage region. Note that the results are identical to the results of a load/store with byte-re v erse in a little endian storage region, as illustrated in Figure 2-12.
Programming Model 2-23 Note that the results are identical to the results of a normal load/store in a little endian storage region, as illustrated in Figure 2-14.
2-24 PPC405 Core User’s Manual Branch instructions are e xamined in DCD and PFB0 while all other instructions are decoded in DCD . All instructions must pass through DCD before entering the EXU . The EXU contains the e x ecute , write-back and load write-back stages of the pipe .
Programming Model 2-25 F or the relativ e (AA = 0) forms ( bc , bc l ), the target address is the CIA plus the signed displacement. F or the absolute (AA = 1) forms ( bca , bcla ), the target address is 0 plus the signed displacement. If the sign bit (BD[0]) is 0, the displacement is the target address.
2-26 PPC405 Core User’s Manual T ab le 2-7 lists specific BO field contents, and the resulting actions; z represents a mandator y value of 0, and y is a branch prediction option discussed in “Branch Prediction. ” 2.7.5 Branch Prediction Conditional branches present a prob lem to the instruction fetcher .
Programming Model 2-27 the algebraic sign of the displacement is positiv e (s = 0), the branch target address is in low memory . Because these are absolute-addressing f or ms, there is no reason to treat high and lo w memor y diff erently .
2-28 PPC405 Core User’s Manual Note that when address translation is enab led, attempts to f etch from guarded storage result in instruction storage e xceptions.
Programming Model 2-29 T o understand the implications of this situation, consider the code sequence: handler : aaa bbb rfi subroutine: bctr When e x ecuting the interrupt handler , the f etcher does.
2-30 PPC405 Core User’s Manual T able 2-8 shows two address regions of the PPC405 core. Suppose a system designer can map all I/O de vices and all ROM and SRAM de vices into an y location in either region. The choices made b y the designer can pre v ent speculative accesses to the memory-mapped I/O devices .
Programming Model 2-31 which cer tain instr uctions cannot be e x ecuted, is called the “user mode, ” or “problem state . ” These ter ms are used in pairs: The architecture uses MSR[PR] to control the e x ecution mode.
2-32 PPC405 Core User’s Manual 2.9.3 Privileged SPRs All SPRs are privileged, except f or the LR, the CTR, the XER, USPRG0, and read access to SPRG4– SPRG7. Reading from the time base registers Time Base Low er (TBL) and Time Base Upper (TBU) is not privileged.
Programming Model 2-33 2.10 Synchr onization The PPC405 core suppor ts the synchronization operations of the P o werPC Architecture . The f ollowing book, chapter , and section numbers ref er to related inf ormation in The PowerPC Architecture: A Specification for a New Family of RISC Processors : • Book II, Section 1.
2-34 PPC405 Core User’s Manual In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after the ST ORE has occurred to memory . There is no guarantee which XYZ instruction will e x ecute; either the old v ersion or the new (stored) v ersion might.
Programming Model 2-35 isync guarantees that all subsequent instructions are fetched and e xecuted using the conte xt established b y all pre vious instructions. isync is a conte xt synchronizing operation; isync causes all subsequently pref etched instructions to be discarded and refetched.
2-36 PPC405 Core User’s Manual stw Store to peripheral sync W ait f or store to actually complete mtdcr Reconfigure device The eieio instruction guarantees the order of storage accesses.
Programming Model 2-37 2.11.1 Instructions Specific to the IBM P o werPC Embedded En vironment T o suppor t functions required in embedded real-time applications, the IBM P owerPC 400 f amily of embedded processors defines instructions that are not defined in the P ow erPC Architecture.
2-38 PPC405 Core User’s Manual 2.11.3 Arithmetic Instructions Arithmetic operations are perf or med on integer operands stored in GPRs. Instructions that perf orm operations on two oper ands are defined in a three-operand f ormat; an operation is perf or med on the operands , which are stored in two GPRs.
Programming Model 2-39 T able 2-14 lists additional arithmetic instr uctions for m ultiply-accumulate and multiply halfw ord operations . In the table , the syntax “[ o ]” indicates that an instruction has an “o” form that updates XER[SO ,O V], and a “non-o” form.
2-40 PPC405 Core User’s Manual 2.11.6 Branch Instructions These instructions unconditionally or conditionally branch to an address. Conditional branch instructions can test condition codes set by a pre vious instruction and branch accordingly .
Programming Model 2-41 2.11.6.3 Shift Instructions These instructions rotate operands stored in the GPRs. T able 2-20 lists the PPC405 shift instructions.
2-42 PPC405 Core User’s Manual 2.11.8 TLB Management Instructions The TLB management instructions read and wr ite entries of the TLB array in the MMU , search the TLB arra y f or an entry which will translate a given address , and inv alidate all TLB entries.
Programming Model 2-43 Ref er to the f ollowing chapter and appendix es f or lists of the e xtended mnemonics: • Chapter 9, “Instruction Set, ” lists e xtended mnemonics under the associated hardware instruction mnemonics.
2-44 PPC405 Core User’s Manual.
Initialization 3-1 Chapter 3. Initialization This chapter describes reset operations, the initial state of the PPC405 core after a reset, and an e xample of the initialization code required to begin e x ecuting application code.
3-2 PPC405 Core User’s Manual T wo SPRs contain status on the type of reset that has occurred. The Debug Status Register (DBSR) contains the most recent reset type.
Initialization 3-3 3.1.2 Contents of Special Purpose Registers after Reset In general, the contents of Special Purpose Registers (SPRs) are undefined after a core, chip , or system reset. Some SPRs retain the contents they had bef ore a reset occurred.
3-4 PPC405 Core User’s Manual Because the processor is initially in big endian mode, initialization code must be in big endian f ormat until the endian storage attribute f or the addressed region is changed, or until code branches to a region defined as little endian storage .
Initialization 3-5 3.4 Initialization Code Example The f ollowing initialization code illustr ates the steps that should be taken to initializ e the processor bef ore an operating system or user progr ams begin e x ecution. The e xample is presented in pseudo- code; function calls are named similarly to PPC405 mnemonics where appropr iate.
3-6 PPC405 Core User’s Manual mtspr(EVPR, prefix_addr); /* initialize exception v ector prefix */ /* Initialize v ector tab le and interrupt handlers if not already done */ /* Initialize and con.
Cache Operations 4-1 Chapter 4. Cache Operations The PPC405 core incor porates two internal cache units, an instruction cache unit (ICU) and a data cache unit (DCU). Instructions and data can be accessed in the caches much faster than in main memor y, if instruction and data cache arrays are implemented.
4-2 PPC405 Core User’s Manual The PPC405 core can include an instruction cache arra y and a data cache arra y . The size of the cache arra ys can v ary by core implementation, as shown in T able 4-1.
Cache Operations 4-3 cache line. The remaining address bits (A 22 :27 ) ser ve as an inde x to the cache arr a y . The two cache lines that correspond with the same line inde x are called a congruence class. T able 4-3 shows the v alues of m and n f or v arious cache array siz es.
4-4 PPC405 Core User’s Manual Figure 4-1 shows the relationships between the ICU and the instruction pipeline. 4.2.1 ICU Operations Instructions from cachable memor y regions are copied into the instruction cache array , if an arra y is present. The f etcher can access instructions much more quickly from a cache arr a y than from memor y .
Cache Operations 4-5 4.2.2 Instruction Cachability Contr ol When instruction address translation is enabled (MSR[IR] = 1), instruction cachability is controlled by the I storage attribute in the tr anslation lookaside buff er (TLB) entry for the memory page.
4-6 PPC405 Core User’s Manual In practice , cache synonyms occur when a real instruction page having m ultiple vir tual mappings e xists in multiple cache lines . F or 1KB pages, all EAs diff ering in EA 19:21 must be cast out of cache , using an icbi instruction for each such EA (up to 8 per cache line in the page).
Cache Operations 4-7 and proceed sequentially to the last word of the line . In both types of fills, the fill b uff er , when full, is transf erred to the data cache arra y . The cache line is mar ked v alid when it is filled. Loads that result in a line fill, and loads from non-cachable memory , are sent to a GPR.
4-8 PPC405 Core User’s Manual write-through is enabled and caching is inhibited. 4.3.3 DCU Load and Store Strategies The DCU can control whether a load receives one w ord or one line of data from main memor y . F or cachable memory , the load without allocate (L W O A) field of the CCR0 controls the type of load resulting from a load miss.
Cache Operations 4-9 enabling the cache . Address translation can then be enab led, if required, and the TLB or the DCCR can then be configured f or the desired cachability .
4-10 PPC405 Core User’s Manual 4.4.2 DCU Instructions Data cache flushes and fills are triggered by load, store and cache control instructions. Cache control instructions are provided to fill, flush, or inv alidate cache b loc ks. The f ollowing instructions control data cache operations .
Cache Operations 4-11 4.5 Cache Contr ol and Deb ugging Features Registers and instructions are provided to control cache operation and help deb ug cache problems . F or ICU debug, the icread instruction and the Instruction Cache Debug Data Register (ICDBDR) are provided.
4-12 PPC405 Core User’s Manual 8 SWO A Store Without Allocate 0 Store misses result in line fills 1 Store misses do not result in line fills, but in non-cachable stores 9 DPP1 DCU PLB Prior ity Bit 1 0 DCU PLB prior ity 0 on bit 1 1 DCU PLB prior ity 1 on bit 1 Note: DCU logic dynamically controls DCU prior ity bit 0.
Cache Operations 4-13 4.5.1 CCR0 Programming Guidelines Se v eral fields in CCR0 aff ect ICU and DCU operation. Altering these fields while the cache units are inv olv ed in PLB transf ers can cause errant operation, including a processor hang.
4-14 PPC405 Core User’s Manual In the f ollowing sample code , registers RN, RM, RX, and RZ are any a v ailab le GPRs. ! SEQUENCE 2 Alter CCR0[DPP1, U0XE) ! T ur n off interr upts mfmsr RM addis RZ,r0,0x0002 ! CE bit ori RZ,RZ,0x8000 ! EE bit andc RZ,RM,RZ ! T ur n off MSR[CE,EE] mtmsr RZ ! sync sync ! Alter CCR0 bits mfspr RN,CCR0 ! Read CCR0.
Cache Operations 4-15 ICU tag inf ormation is placed into the ICDBDR as shown: If CCR0[CIS] = 0, the data is a word of ICU data from the addressed line, specified b y EA 27:29 . If CCR0[CWS] = 0, the data is from the A-wa y; otherwise; the data from the B-wa y .
4-16 PPC405 Core User’s Manual DCU tag inf ormation is placed into the GPR as shown: Note: A “dir ty” cache line is one which has been accessed by a store instruction after it was established, and can be inconsistent with e xternal memor y .
Cache Operations 4-17 The DCU can accept up to two load commands . If the data f or the first load command is not immediately av ailab le, the DCU can still accept the second load command. If the load data is not required by subsequent instructions, those instructions will continue to e x ecute .
4-18 PPC405 Core User’s Manual 4.6.4 Sequential Cache Operations Some common cache operations , when perf or med sequentially , can limit DCU performance: sequential loads/stores to non-cachable stor age regions, sequential line fills , and sequential line flushes.
Fixed-Point Interrupts and Exceptions 5-1 Chapter 5. Fixed-P oint Interrupts and Exceptions An interrupt is the action in which the processor sav es its old conte xt (MSR and instruction pointer) and begins e x ecution at a pre-deter mined interrupt-handler address, with a modified MSR.
5-2 PPC405 Core User’s Manual 3. The instruction having its address repor ted to the interr upt handler may appear not to ha v e begun e x ecution, or ma y hav e partially completed. Synchronous interrupts are caused directly by the e x ecution (or attempted e x ecution) of instructions.
Fixed-Point Interrupts and Exceptions 5-3 Synchronous precise interrupts include most debug e v ent interrupts, program interrupts, instruction and data storage interrupts,auxiliary processor unit (APU) interr upts, floating point unit (FPU interrupts, TLB miss interrupts, system call interrupts, and alignment interrupts.
5-4 PPC405 Core User’s Manual All asynchronous interrupt types can be masked. In addition, cer tain synchronous interr upt types can be masked. T able 5-1.
Fixed-Point Interrupts and Exceptions 5-5 5.4 Critical and Noncritical Interrupts The PPC405 processes interrupts as noncr itical and critical. The following interrupts are defined as noncritical : d.
5-6 PPC405 Core User’s Manual written by the time of the interrupt; when the instr uction restar ts, the registers will simply be written again. Similarly , some of the target memory of a store instr uction may ha v e been written, and is written again when the instr uction restar ts.
Fixed-Point Interrupts and Exceptions 5-7 5.5 General Interrupt Handling Registers The general interrupt handling registers are the Machine State Register (MSR), SRR0–SRR3, the Exception V ector Prefix Register (EVPR), the Exception Syndrome Register (ESR), and the Data Exception Address Register (DEAR).
5-8 PPC405 Core User’s Manual 14 CE Critical Interr upt Enable 0 Critical interr upts are disabled. 1 Critical interr upts are enabled. Controls the critical interr upt input and watchdog timer first time-out interrupts. 15 Reser ved 16 EE Exter nal Interrupt Enable 0 Asynchronous interruptsare disabled.
Fixed-Point Interrupts and Exceptions 5-9 5.5.2 Save/Restore Register s 0 and 1 (SRR0–SRR1) SRR0 and SRR1 are 32-bit registers that hold the interrupted machine context when a noncritical interrupt is processed. On interr upt, SRR0 is set to the current or next instruction address and the contents of the MSR are written to SRR1.
5-10 PPC405 Core User’s Manual The contents of SRR2 and SRR3 can be written to GPRs using the mfspr instr uction. The contents of GPRs can be written to SRR2 and SRR3 using the mtspr instr uction. Figure 5-4 shows the bit definitions f or SRR2. . Figure 5-5 shows the bit definitions f or SRR3.
Fixed-Point Interrupts and Exceptions 5-11 5.5.5 Exception Syndr ome Register (ESR) The ESR is a 32-bit register whose bits help to specify the e xact cause of v arious synchronous interrupts.
5-12 PPC405 Core User’s Manual In general, ESR bits are set to indicate the type of precise interrupt that occurred; other bits are cleared. How e v er , the machine chec k—instruction (ESR[MCI]) bit behav es diff erently .
Fixed-Point Interrupts and Exceptions 5-13 occurred; the other ESR bits are set or cleared to indicate the other interrupt. These scenar ios are summarized in T able 5-3 Engineering Note: An implementation can use additional ESR bits to identify implementation- specific e xception types.
5-14 PPC405 Core User’s Manual SRR2. Simultaneously , the contents of the MSR are sav ed in SRR3. MSR[CE] is reset to 0 to pre v ent another critical interr upt or the watchdog timer first time-out interrupt from interrupting the cr itical interrupt handler before SRR2 and SRR3 get sa v ed.
Fixed-Point Interrupts and Exceptions 5-15 handler (EVPR[0:15] || 0x0200), setting ESR[MCI]. Note that only a bus error can cause a machine check—instruction interrupt.
5-16 PPC405 Core User’s Manual 5.8 Data Storage Interrupt The data storage interrupt occurs when the desired access to the effectiv e address is not permitted f or any of the f ollo wing reasons: .
Fixed-Point Interrupts and Exceptions 5-17 F or instructions that can simultaneously generate progr am interrupts (pr ivileged instr uctions e x ecuted in Problem State) and data stor age interrupts, the program interrupt has prior ity .
5-18 PPC405 Core User’s Manual The f ollowing registers are modified to the specified v alues: 5.10 External Interrupt Exter nal interrupts are tr iggered by activ e le v els on the e xternal interr upt inputs. All external interrupting ev ents are presented to the processor as a single e xternal interr upt.
Fixed-Point Interrupts and Exceptions 5-19 Ex ecuting an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and e x ecution resumes at the address in the program counter .
5-20 PPC405 Core User’s Manual 5.12 Pr ogram Interrupt Program interrupts are caused b y attempting to e x ecute: • An illegal instruction • A privileged instr uction while in the problem state .
Fixed-Point Interrupts and Exceptions 5-21 Attempted e x ecution of an APU instruction while the APUc405exception signal is asser ted) results in a program interrupt. Similarly , attempted e x ecution of an FPU instruction whilethe FPUc405e xception signal is asser ted) also results in a program interrupt.
5-22 PPC405 Core User’s Manual 5.14 System Call Interrupt System call interrupts occur when a sc instr uction is ex ecuted. The PPC405 writes the address of the instruction follo wing the sc into SRR0. The contents of the MSR are written into SRR1 and the MSR bits are written with the values sho wn in T able 5-15.
Fixed-Point Interrupts and Exceptions 5-23 simultaneously , the contents of the MSR are written into SRR1 and the MSR is wr itten with the values shown in T able 5-17. The high-order 16 bits of the program counter are then written with the contents of the EVPR and the low-order 16 bits of the progr am counter are written with 0x1000.
5-24 PPC405 Core User’s Manual Ex ecuting an rfi instruction restores the program counter from SRR0 and the MSR from SRR1, and e x ecution resumes at the address in the program counter . 5.18 W atchdog Timer Interrupt F or a general description of the PPC405 timer f acilities, see Chapter 6, “Timer F acilities.
Fixed-Point Interrupts and Exceptions 5-25 5.19 Data TLB Miss Interrupt The data TLB miss interrupt is generated if data translation is enabled and a v alid TLB entr y matching the EA and PID is not present. The address of the instruction generating the untranslatable eff ective data address is sav ed in SRR0.
5-26 PPC405 Core User’s Manual is activ e. Theref ore , insure that SRR0 and SRR1 are sav ed bef ore enab ling translation in an interrupt handler . 5.
Timer Facilities 6-1 Chapter 6. Timer Facilities The PPC405 provides f our timer f acilities: a time base , a Programmab le Interval Timer (PIT), a fix ed inter val timer (FIT), and a w atchdog timer .
6-2 PPC405 Core User’s Manual the time base. The TBR n umbers (0x10C and 0x10D; TBL and TBU , respectiv ely) that specify the time base registers to mftb are not SPR numbers. Ho we v er , the P o werPC Architecture allows an implementation to handle mftb as mfspr .
Timer Facilities 6-3 T able 6-1 summarizes the TBRs, instructions used to access the TBRs, and access restrictions. 6.1.1 Reading the Time Base The f ollowing code pro vides an e xample of reading the time base. mftb mo v es the low-order 32 bits of the time base to a GPR; mftbu mo v es the high-order 32 bits of the time base to a second GPR.
6-4 PPC405 Core User’s Manual 6.2 Pr ogrammable Interval Timer (PIT) The PIT is a 32-bit SPR that decrements at the same rate as the time base. The PIT is read and written using mfspr and mtspr , respectiv ely . Wr iting to the PIT also simultaneously writes to a hidden reload register .
Timer Facilities 6-5 6.2.1 Fixed Interval Timer (FIT) The FIT provides timer interrupts having a repeatab le period. The FIT is functionally similar to an auto-reload PIT , except that only a smaller fix ed selection of interrupt periods are av ailable .
6-6 PPC405 Core User’s Manual 6.3 W atc hdog Timer The watchdog timer aids system reco v er y from software or hardware f aults . A watchdog timeout occurs on 0 → 1 tr ansitions of a selected bit from the time base, as sho wn in the f ollowing tab le.
Timer Facilities 6-7 Figure 6-5 describes the watchdog state machine. In the figure, n umbers in parentheses ref er to descriptions of operating modes that f ollow the tab le. The controls described in Figure 6-5 imply three different wa ys of using the w atchdog timer .
6-8 PPC405 Core User’s Manual T o clear TSR[ENW], use mtspr to wr ite a 1 to TSR[ENW] (and to any other bits that are to be cleared), with 0 in all other bit locations.
Timer Facilities 6-9 6.5 Timer Contr ol Register (TCR) The TCR controls PIT , FIT , and watchdog timer operation. The TCR[WRC] field is cleared to 0 by all processor resets . (Chapter 3, “Initialization, ” descr ibes the types of processor reset.
6-10 PPC405 Core User’s Manual 8 FIE FIT Interrupt Enable 0 Disable FIT interrupt. 1 Enable FIT interrupt. 9 ARE Auto Reload Enab le 0 Disable auto reload.
Memory Management 7-1 Chapter 7. Memor y Management The PPC405 has a 4-gigabyte (GB) address space , which is presented as a flat address space.The PPC405 memor y management unit (MMU) performs address translation and protection functions.
7-2 PPC405 Core User’s Manual In address translation, the EA is combined with an 8-bit process ID (PID) to create a 40-bit vir tual address. The vir tual address is compared to all of the TLB entries. A matching entr y supplies the real address f or the storage ref erence .
Memory Management 7-3 real page number (RPN), access control bits (ZSEL, EX, WR), and storage attributes (W , I, M, G, E, U0 The vir tual address space is extended b y adding an 8-bit translation ID (TID) loaded from the Process ID (PID) register during a TLB access.
7-4 PPC405 Core User’s Manual The e xact comparison depends on the page size, as sho wn in T able 7-1. SIZE (page size , 3 bits) Selects one of the eight page sizes , 1KB–16MB, listed in T able 7-1. V (v alid,1 bit) Indicates whether a TLB entr y is valid and can be used f or tr anslation.
Memory Management 7-5 7.3.2.3 Access Contr ol Fields Se v eral access controls are a v ailable in the UTLB entries. ZSEL (zone select, 4 bits) Selects one of 16 zone fields (Z0—Z15) from the Zone Protection Register (ZPR). The ZPR field bits can modify the access protection specified by the TLB_entry[V , EX, WR] bits of a TLB entr y .
7-6 PPC405 Core User’s Manual M (memor y coherent,1 bit) F or implementations that suppor t multiprocessing, the M storage attribute improv es the perf ormance of memor y coherency management. Because the PPC405 does not provide multi-processor support or hardware suppor t f or data coherency , the M bit is implemented, but has no eff ect.
Memory Management 7-7 7.3.3.1 ITLB Accesses The instruction unit accesses the ITLB independently of the rest of the MMU. ITLB accesses are transparent to the e x ecuting progr am, e xcept that ITLB hits contribute to higher ov er all instruction throughput by allo wing data address translations to occur in par allel.
7-8 PPC405 Core User’s Manual and translation is disab led. If the operating system simply made the TLB updates and returned from the handler (using rfi or rfci ), no additional e xplicit software action would be required to synchroniz e the ITLB and DTLB.
Memory Management 7-9 Figure 7-3 illustrates the relationship of the shadow TLBs and UTLB in address tr anslation: 7.4 TLB-Related Interrupts The processor relies on interrupt handling software to implement paged vir tual memor y , and to enf orce protection of specified memor y pages.
7-10 PPC405 Core User’s Manual address and is passed directly to the memor y subsystem (including cache units). Such untranslated addresses bypass all memory protection checks that would otherwise be perf ormed by the MMU .
Memory Management 7-11 See “Zone Protection” on page 7-14 for a detailed discussion of z one protection. See “Instruction Storage Interrupt” on page 5-17 for a detailed discussion of the instruction storage interrupt.
7-12 PPC405 Core User’s Manual 7.5.1 TLB Searc h Instructions (tlbsx/tlbsx.) tlbsx locates entries in the TLB, to find the TLB entr y associated with an interrupt, or to locate candidate entries to cast out. tlbsx searches the UTLB array f or a matching entry .
Memory Management 7-13 The PPC405 does not provide hardw are ref erence or change bits, b ut TLB miss interrupts and data storage interrupts enable system softw are to maintain ref erence inf ormation for TLB entries and their associated pages, respectiv ely .
7-14 PPC405 Core User’s Manual If TLB_entr y[TID] = 0x00, the associated memor y page is accessible to all programs , regardless of their PID . This enables multiple processes to share common code and data. The common area is still subject to all other access protection mechanisms.
Memory Management 7-15 The ZSEL v alues 0 − 15 select ZPR fields Z0 − Z15, respectively . The fields are defined within the ZPR as f ollows: While it is common f or TLB_entr y[EX, WR] to be identical for all member pages in a g roup , this is not required.
7-16 PPC405 Core User’s Manual Setting ZPR[Z n ] = 00 for a ZPR field is the only w a y to deny read access to a page defined b y an otherwise v alid TLB entr y .
Memory Management 7-17 the operand address of the instruction). T o restrict possible damage from an instruction which can change data and yet a v oids the protection mechanism, the dccci instruction is pr ivileged.
7-18 PPC405 Core User’s Manual implemented f or the M storage attribute because the PPC405 does not pro vide multi-processor suppor t or hardware suppor t for data coherency . These SPRs, called stor age attribute control registers, control the v arious storage attributes when address translation is disab led.
Memory Management 7-19 7.8.1 Storage Attribute Contr ol Register s Figure 7-6 shows a generic storage attribute control register . The storage attr ibute control registers hav e the same bit n umbering and address ranges.
7-20 PPC405 Core User’s Manual 7.8.1.2 Data Cache Cac hability Register (DCCR) The DCCR controls the I storage attribute f or data accesses and cache management instructions.
Debugging 8-1 Chapter 8. Deb ugging The debug f acilities of the PPC405 include support for deb ug modes f or debugging during hardware and software de v elopment, and deb ug e v ents that allow de v elopers to control the deb ug process. Debug registers control the deb ug modes and deb ug e v ents.
8-2 PPC405 Core User’s Manual T o enable internal debug mode, the Deb ug Control Register 0 (DBCR0) field IDM is set to 1 (DBCR0[IDM] = 1). T o enable deb ug interrupts, MSR[DE] = 1. A debug interrupt occurs on a debug e v ent only if DBCR0[IDM] = 1 and MSR[DE] = 1.
Debugging 8-3 In this mode, access to the processor is through the JT A G debug por t. 8.2.4 Real-time T race Debug Mode Real-time trace deb ug mode suppor ts the generation of trigger ev ents f or tracing the instruction stream being e x ecuted out of the instruction cache in real-time.
8-4 PPC405 Core User’s Manual 8.4 Pr ocessor Status The processor e x ecution status, e xception status , and most recent reset can be monitored. 8.5 Deb ug Registers Se v eral deb ug registers, a v ailable to deb ug tools running on the processor , are not intended f or use by application code .
Debugging 8-5 4 IC Instruction Completion Debug Event 0 Disabled 1 Enabled 5 BT Branch T aken Debug Ev ent 0 Disabled 1 Enabled 6 EDE Exception Debug Ev ent 0 Disabled 1 Enabled 7 TDE T rap Debug Ev e.
8-6 PPC405 Core User’s Manual 8.5.1.2 Deb ug Control Register1 (DBCR1) 31 FT F reeze timers on deb ug e v ent 0 Timers not frozen 1 Timers frozen Figure 8-2.
Debugging 8-7 8.5.2 Debug Status Register (DBSR) The DBSR contains status on debug e v ents and the most recent reset; the status is obtained b y reading the DBSR. The status bits are nor mally set by deb ug e v ents or b y any of the three reset types.
8-8 PPC405 Core User’s Manual Figure 8-3. Debug Status Register (DBSR) 0 IC Instruction Completion Debug Ev ent 0 Event did not occur 1 Event occurred 1 BT Branch T aken Debug Ev ent 0 Event did not.
Debugging 8-9 8.5.3 Instruction Address Compare Register s (IA C1–IA C4) The PPC405 can take a deb ug e v ent upon an attempt to e x ecute an instruction from an address. The address, which m ust be word-aligned, is defined in an IA C register . The DBCR0[IA1, IA2] fields of DBCR0 controls the instruction address compare (IAC) deb ug e v ent.
8-10 PPC405 Core User’s Manual 8.5.5 Data V alue Compare Registers (D VC1–D VC2) The PPC405 can take a deb ug e v ent upon storage or cache ref erences to addresses specified in the D A C registers , that also require the data at that address to match the value specified in the D VC registers.
Debugging 8-11 T able 8-1 lists the debug e v ents and the related fields in DBCR0, DBCR1, and DBSR. DBCR0 and DBCR1 enable the deb ugs e v ents , and the DBSR fields repor t their occurrence. 8.5.7 Instruction Complete Debug Event This debug e v ent occurs after the completion of an instruction.
8-12 PPC405 Core User’s Manual 8.5.10 T rap T aken Debug Event This debug e v ent occurs bef ore e x ecution of a tr ap instruction where the conditions are such that the trap will occur .
Debugging 8-13 Figure 8-7 shows the range selected in an inclusiv e IA C range address compare . Note that the address in IA C1 is considered par t of the range, b ut the address in IA C2 is not, as shown in the preceding e xamples. The thic k lines indicate that the indicated address is included in the compare results.
8-14 PPC405 Core User’s Manual The address f or a D A C is the eff ectiv e address (EA) of a storage ref erence instruction. EAs are alwa ys gener ated within a single aligned word of memor y . Unaligned load and store, strings, and multiples generate m ultiple EAs to be used in D A C comparisons.
Debugging 8-15 preceding e xamples. The thic k lines indicate that the indicated address is included in the compare results. Figure 8-10 shows the range selected in an e xclusiv e D AC range address compare .
8-16 PPC405 Core User’s Manual Architecturally , the dcbi and dcbz instr uctions are “stores. ” These instructions can change data, or cause the loss of data by in v alidating a dir ty line. Theref ore, the y can cause D AC-write debug e v ents .
Debugging 8-17 comparison and by setting any bit combination in the DBCR1[D V1BE]. Each bit in DBCR1[D V1BE, D V2BE] correspondes to a byte in D VC1 and D VC2. Exact address compare and range address compare work the same f or D VC as for a simple D AC .
8-18 PPC405 Core User’s Manual When DBCR1[D V n M] = 11, the compar ison is an AND-OR (halfword) comparison. This is intended f or use when DBCR1[D V n BE] is set to 0011, 0111, or 1111. Other v alues of DBCR1[D V n BE] can be compared, but the results are more easily understood using the AND and OR comparisons.
Debugging 8-19 T able 8-6 illustrates comparisons for misaligned D VC accesses . In the “D VC1” and “D VC2” columns, “x” indicates a don’t care. Note: Misaligned accesses stop the processor on the instruction causing the compare hit. The second par t of an instr uction is not perf or med if the first par t of the compare hits.
8-20 PPC405 Core User’s Manual specifications f or v endor-specific e xtensions, are compatib le with standard JT AG hardw are f or boundar y-scan system testing. 8.7 JT A G Connector A 16-pin male 2x8 header connector is suggested as the JT AG deb ug por t connector .
Debugging 8-21 1. A 10K ohm pullup resistor should be connected to this signal to reduce chip power consumption. The pullup resistor is not required. 2. The +POWER signal, sourced from the target de v elopment board, indicates whether the processor is operating.
8-22 PPC405 Core User’s Manual robust e xtensions that can be used f or internal test generation and to write software f or hardware debug and diagnostics . The primar y components of BSDL include the logical por t descr iption, the ph ysical pin map , the instruction set, and the boundar y register descr iption.
Instruction Set 9-1 Chapter 9. Instruction Set Descriptions of the PPC405 instr uctions follo w . Each description contains the following elements: • Instruction names (mnemonic and full) • Instru.
9-2 PPC405 Core User’s Manual 9.2 Instruction Formats F or more detailed inf ormation about instr uction formats, including a summary of instr uction field usage and instruction format diagrams f or the PPC405 core, see “Instruction F or mats” on page 9-2.
Instruction Set 9-3 || Concatenation =, ≠ Equal, not equal relations <, > Signed comparison relations , Unsigned comparison relations if ...then...else... Conditional e x ecution; if condition then a else b , where a and b represent one or more pseudocode statements.
9-4 PPC405 Core User’s Manual xx Bit positions which are don’t-cares. CEIL(x) Least integer ≥ x. EXTS(x) The result of e xtending x on the left with sign bits. PC Program counter . RESER VE Reser ve bit; indicates whether a process has reserved a b loc k of storage .
Instruction Set 9-5 9.3.1 Operator Precedence T able 9-2 lists the pseudocode operators and their associativity in descending order of precedence: 9.4 Register Usage Each instruction descr iption lists the registers altered by the instruction.
9-6 PPC405 Core User’s Manual add Add 9.Instruction Set add Add (R T) ← (RA) + (RB) The sum of the contents of register RA and the contents of register RB is placed into register R T .
Instruction Set 9-7 addc Add Carrying addc Add Carrying (R T) ← (RA) + (RB) if (RA) + (RB) 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and register RB is placed into register R T . XER[CA] is set to a v alue deter mined by the unsigned magnitude of the result of the add oper ation.
9-8 PPC405 Core User’s Manual adde Add Extended adde Add Extended (R T) ← (RA) + (RB) + XER[CA] if (RA) + (RB) + XER[CA] 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA, register RB, and XER[CA] is placed into register R T .
Instruction Set 9-9 addi Add Immediate addi Add Immediate (R T) ← (RA|0) + EXTS(IM) If the RA field is 0, the IM field, sign-e xtended to 32 bits, is placed into register R T . If the RA field is nonzero , the sum of the contents of register RA and the contents of the IM field, sign- e xtended to 32 bits, is placed into register R T .
9-10 PPC405 Core User’s Manual addic Add Immediate Carrying addic Add Immediate Carrying (R T) ← (RA) + EXTS(IM) if (RA) + EXTS(IM) 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and the contents of the IM field, sign-e xtended to 32 bits, is placed into register R T .
Instruction Set 9-11 addic. Add Immediate Carrying and Record addic. Add Immediate Carrying and Record (R T) ← (RA) + EXTS(IM) if (RA) + EXTS(IM) 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and the contents of the IM field, sign-e xtended to 32 bits, is placed into register R T .
9-12 PPC405 Core User’s Manual addis Add Immediate Shifted addis Add Immediate Shifted (R T) ← (RA|0) + (IM || 16 0) If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT . If the RA field is nonzero , the contents of register RA are added to the contents of the extended IM field.
Instruction Set 9-13 addme Add to Minus One Extended addme Add to Minus One Extended (R T) ← (RA) + XER[CA] + (–1) if (RA) + XER[CA] + 0xFFFF FFFF 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA, XER[CA], and –1 is placed into register R T .
9-14 PPC405 Core User’s Manual addze Add to Zero Extended addze Add to Zero Extended (R T) ← (RA) + XER[CA] if (RA) + XER[CA] 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and XER[CA] is placed into register R T .
Instruction Set 9-15 and AND and AND (RA) ← (RS) ∧ (RB) The contents of register RS are ANDed with the contents of register RB; the result is placed into register RA. Registers Altered •R A • CR[CR0] L T , GT , EQ, SO if Rc contains 1 Arc hitecture Note This instruction is par t of the P o werPC User Instruction Set Architecture.
9-16 PPC405 Core User’s Manual andc AND with Complement andc AND with Complement (RA) ← (RS) ∧¬ (RB) The contents of register RS are ANDed with the ones complement of the contents of register RB; the result is placed into register RA.
Instruction Set 9-17 andi. AND Immediate andi. AND Immediate (RA) ← (RS) ∧ ( 16 0 || IM) The IM field is e xtended to 32 bits by concatenating 16 0-bits on its left. The contents of register RS is ANDed with the e xtended IM field; the result is placed into register RA.
9-18 PPC405 Core User’s Manual andis. AND Immediate Shifted andis. AND Immediate Shifted (RA) ← (RS) ∧ (IM || 16 0) The IM field is e xtended to 32 bits b y concatenating 16 0-bits on its right. The contents of register RS are ANDed with the e xtended IM field; the result is placed into register RA.
Instruction Set 9-19 b Branch b Branch If AA = 1 then LI ← target 6:29 NIA ← EXTS(LI || 2 0) else LI ← (target – CIA) 6:29 NIA ← CIA + EXTS(LI || 2 0) if LK = 1 then (LR) ← C I A+4 PC ← NIA The ne xt instruction address (NIA) is the effectiv e address of the br anch.
9-20 PPC405 Core User’s Manual bc Branch Conditional bc Branch Conditional if BO 2 = 0 then CTR ← C T R–1 if (BO 2 = 1 ∨ ((CTR = 0) = BO 3 )) ∧ (BO 0 =1 ∨ (CR BI = BO 1 )) then if AA = 1 t.
Instruction Set 9-21 bc Branch Conditional Arc hitecture Note This instruction is par t of the P o werPC User Instruction Set Architecture. T able 9-7. Extended Mnemonics for bc, bca, bcl, bc la Mnemonic Operands Function Other Registers Altered bdnz target Decrement CTR; branch if CTR ≠ 0.
9-22 PPC405 Core User’s Manual bc Branch Conditional bdzf cr_bit, target Decrement CTR Branch if CTR = 0 AND CR cr_bit =0 . Extended mnemonic f or bc 2,cr_bit,target bdzfa Extended mnemonic f or bca 2,cr_bit,target bdzfl Extended mnemonic f or bcl 2,cr_bit,tar get (LR) ← CIA + 4.
Instruction Set 9-23 bc Branch Conditional bge [cr_field,] target Branch if greater than or equal. Use CR0 if cr_field is omitted. Extended mnemonic f or bc 4,4 ∗ cr_field+0,target bgea Extended .
9-24 PPC405 Core User’s Manual bc Branch Conditional bne [cr_field,] target Branch if not equal. Use CR0 if cr_field is omitted. Extended mnemonic f or bc 4,4 ∗ cr_field+2,target bnea Extended mnemonic f or bca 4,4 ∗ cr_field+2,target bnel Extended mnemonic f or bcl 4,4*cr_field+2,tar get (LR) ← CIA + 4.
Instruction Set 9-25 bc Branch Conditional bnu [cr_field,] target Branch if not unordered. Use CR0 if cr_field is omitted. Extended mnemonic f or bc 4,4 ∗ cr_field+3,target bnua Extended mnemonic f or bca 4,4 ∗ cr_field+3,target bnul Extended mnemonic f or bcl 4,4 ∗ cr_field+3,tar get (LR) ← CIA + 4.
9-26 PPC405 Core User’s Manual bcctr Branch Conditional to Count Register bcctr Branch Conditional to Count Register if BO 2 = 0 then CTR ← C T R–1 if (BO 2 = 1 ∨ ((CTR = 0) = BO 3 )) ∧ (BO .
Instruction Set 9-27 bcctr Branch Conditional to Count Register T able 9-8. Extended Mnemonics for bcctr , bcctrl Mnemonic Operands Function Other Registers Altered bctr Branch unconditionally to address in CTR. Extended mnemonic f or bcctr 20,0 bctrl Extended mnemonic f or bcctrl 20,0 (LR) ← CIA + 4.
9-28 PPC405 Core User’s Manual bcctr Branch Conditional to Count Register bnectr [cr_field] Branch, if not equal, to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+2 bnectrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+2 (LR) ← CIA + 4.
Instruction Set 9-29 bcctr Branch Conditional to Count Register bunctr [cr_field] Branch if unordered to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 12,4 ∗ cr_field+3 bunctrl Extended mnemonic f or bcctrl 12,4 ∗ cr_field+3 (LR) ← CIA + 4.
9-30 PPC405 Core User’s Manual bclr Branch Conditional to Link Register bclr Branch Conditional to Link Register if BO 2 = 0 then CTR ← C T R–1 if (BO 2 = 1 ∨ ((CTR = 0) = BO 3 )) ∧ (BO 0 =1.
Instruction Set 9-31 bclr Branch Conditional to Link Register bdnzlr Decrement CTR. Branch if CTR ≠ 0 to address in LR. Extended mnemonic f or bclr 16,0 bdnzlrl Extended mnemonic f or bclrl 16,0 (LR) ← C I A+4 . bdnzflr cr_bit Decrement CTR. Branch if CTR ≠ 0 AND CR cr_bit = 0 to address in LR.
9-32 PPC405 Core User’s Manual bclr Branch Conditional to Link Register bflr cr_bit Branch if CR cr_bit = 0 to address in LR. Extended mnemonic f or bclr 4,cr_bit bflrl Extended mnemonic f or bclrl 4,cr_bit (LR) ← C I A+4 . bgelr [cr_field] Branch, if greater than or equal, to address in LR.
Instruction Set 9-33 bclr Branch Conditional to Link Register bnllr [cr_field] Branch, if not less than, to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 4,4 ∗ cr_field+0 bnllrl Extended mnemonic f or bclrl 4,4 ∗ cr_field+0 (LR) ← C I A+4 .
9-34 PPC405 Core User’s Manual cmp Compare cmp Compare c 0:3 ← 4 0 if (RA) < (RB) then c 0 ← 1 if (RA) > (RB) then c 1 ← 1 if (RA) = (RB) then c 2 ← 1 c 3 ← XER[SO] n ← BF CR[CRn] ← c 0:3 The contents of register RA are compared with the contents of register RB using a 32-bit signed compare.
Instruction Set 9-35 cmpi Compare Immediate cmpi Compare Immediate c 0:3 ← 4 0 if (RA) < EXTS(IM) then c 0 ← 1 if (RA) > EXTS(IM) then c 1 ← 1 if (RA) = EXTS(IM) then c 2 ← 1 c 3 ← XER[SO] n ← BF CR[CRn] ← c 0:3 The IM field is sign-e xtended to 32 bits.
9-36 PPC405 Core User’s Manual cmpl Compare Logical cmpl Compare Logical c 0:3 ← 4 0 if (RA) (RB) then c 0 ← 1 if (RA) (RB) then c 1 ← 1 if (RA) (RB) then c 2 ← 1 c 3 ← XER[SO] n ← BF CR[CRn] ← c 0:3 The contents of register RA are compared with the contents of register RB, using a 32-bit unsigned compare.
Instruction Set 9-37 cmpli Compare Logical Immediate cmpli Compare Logical Immediate c 0:3 ← 4 0 if (RA) ( 16 0 || IM) then c 0 ← 1 if (RA) ( 16 0 || IM) then c 1 ← 1 if (RA) ( 16 0 || IM) then c 2 ← 1 c 3 ← XER[SO] n ← BF CR[CRn] ← c 0:3 The IM field is e xtended to 32 bits by concatenating 16 0-bits to its left.
9-38 PPC405 Core User’s Manual cntlzw Count Leading Zeros Word cntlzw Count Leading Zeros Word n ← 0 do while n < 32 if (RS) n = 1 then leav e n ← n+1 (RA) ← n The consecutiv e leading 0 bits in register RS are counted; the count is placed into register RA.
Instruction Set 9-39 crand Condition Register AND crand Condition Register AND CR BT ← CR BA ∧ CR BB The CR bit specified by the BA field is ANDed with the CR bit specified b y the BB field; the result is placed into the CR bit specified by the BT field.
9-40 PPC405 Core User’s Manual crandc Condition Register AND with Complement crandc Condition Register AND with Complement CR BT ← CR BA ∧¬ CR BB The CR bit specified by the BA field is ANDed with the ones complement of the CR bit specified b y the BB field; the result is placed into the CR bit specified by the BT field.
Instruction Set 9-41 creqv Condition Register Equivalent creqv Condition Register Equivalent CR BT ←¬ (CR BA ⊕ CR BB ) The CR bit specified by the BA field is XORed with the CR bit specified b y the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
9-42 PPC405 Core User’s Manual crnand Condition Register NAND crnand Condition Register NAND CR BT ←¬ (CR BA ∧ CR BB ) The CR bit specified by the BA field is ANDed with the CR bit specified b y the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
Instruction Set 9-43 crnor Condition Register NOR crnor Condition Register NOR CR BT ←¬ (CR BA ∨ CR BB ) The CR bit specified by the BA field is ORed with the CR bit specified b y the BB field; the ones complement of the result is placed into the CR bit specified by the BT field.
9-44 PPC405 Core User’s Manual cror Condition Register OR cror Condition Register OR CR BT ← CR BA ∨ CR BB The CR bit specified by the BA field is ORed with the CR bit specified b y the BB field; the result is placed into the CR bit specified by the BT field.
Instruction Set 9-45 crorc Condition Register OR with Complement crorc Condition Register OR with Complement CR BT ← CR BA ∨¬ CR BB The condition register (CR) bit specified by the BA field is ORed with the ones complement of the CR bit specified by the BB field; the result is placed into the CR bit specified b y the BT field.
9-46 PPC405 Core User’s Manual crxor Condition Register XOR crxor Condition Register XOR CR BT ← CR BA ⊕ CR BB The CR bit specified by the BA field is XORed with the CR bit specified b y the BB field; the result is placed into the CR bit specified by the BT field.
Instruction Set 9-47 dcba Data Cache Block Allocate dcba Data Cache Block Allocate EA ← (RA|0) + (RB) DCBA(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise .
9-48 PPC405 Core User’s Manual dcba Data Cache Block Allocate Exceptions This instruction is considered a “store” with respect to data storage exceptions . How e v er , this instruction does not cause data storage exceptions or data TLB-miss e xceptions .
Instruction Set 9-49 dcbf Data Cache Block Flush dcbf Data Cache Block Flush EA ← (RA|0) + (RB) DCBF(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise .
9-50 PPC405 Core User’s Manual dcbi Data Cache Block Invalidate dcbi Data Cache Block Invalidate EA ← (RA|0) + (RB) DCBI(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-51 dcbst Data Cache Block Store dcbst Data Cache Block Store EA ← (RA|0) + (RB) DCBST(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 if the RA field is 0, and is the contents of register RA otherwise .
9-52 PPC405 Core User’s Manual dcbt Data Cache Block Touch dcbt Data Cache Block T ouch EA ← (RA|0) + (RB) DCBT(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
Instruction Set 9-53 dcbtst Data Cache Block Touch for Store dcbtst Data Cache Block T ouch for Store EA ← (RA|0) + (RB) DCBTST(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-54 PPC405 Core User’s Manual dcbz Data Cache Block Set to Zero dcbz Data Cache Block Set to Zero EA ← (RA|0) + (RB) DCBZ(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-55 dcbz Data Cache Block Set to Zero Exceptions An alignment e xception occurs if the EA is marked as non-cachab le or as write-through. This instruction is considered a “store” with respect to data storage exceptions . See “Data Storage Interrupt” on page 5-16.
9-56 PPC405 Core User’s Manual dccci Data Cache Congruence Class Invalidate dccci Data Cache Congruence Class Invalidate EA ← (RA|0) + (RB) DCCCI(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-57 dcread Data Cache Read dcread Data Cache Read EA ← (RA|0) + (RB) if ((CCR0[CIS] = 0) ∧ (CCR0[CWS] = 0)) then (R T) ← (d-cache data, wa y A) if ((CCR0[CIS] = 0) ∧ (CCR0[CWS.
9-58 PPC405 Core User’s Manual dcread Data Cache Read Programming Note Ex ecution of this instruction is pr ivileged. Exceptions If EA is not word-aligned, an alignment e xception occurs . This instruction is considered a “load” with respect to data storage exceptions , b ut cannot cause a data storage e xception.
Instruction Set 9-59 divw Divide Word divw Divide Word (R T) ← (RA) ÷ (RB) The contents of register RA are divided by the contents of register RB . The quotient is placed into register R T . Both the dividend and the divisor are inter preted as signed integers.
9-60 PPC405 Core User’s Manual divwu Divide Word Unsigned divwu Divide Word Unsigned (R T) ← (RA) ÷ (RB) The contents of register RA are divided by the contents of register RB . The quotient is placed into register R T . The dividend and the divisor are inter preted as unsigned integers.
Instruction Set 9-61 eieio Enforce In Order Execution of I/O eieio Enforce In Order Execution of I/O The eieio instruction ensures that all loads and stores preceding eieio complete with respect to main storage bef ore an y loads and stores f ollowing eieio access main storage .
9-62 PPC405 Core User’s Manual eqv Equivalent eqv Equivalent (RA) ←¬ ((RS) ⊕ (RB)) The contents of register RS are XORed with the contents of register RB; the ones complement of the result is placed into register RA.
Instruction Set 9-63 extsb Extend Sign Byte extsb Extend Sign Byte (RA) ← EXTS(RS) 24:31 The least significant byte of register RS is sign-e xtended to 32 bits b y replicating bit 24 of the register into bits 0 through 23 of the result. The result is placed into register RA.
9-64 PPC405 Core User’s Manual extsh Extend Sign Halfword extsh Extend Sign Halfword (RA) ← EXTS(RS) 16:31 The least significant halfword of register RS is sign-e xtended to 32 bits b y replicating bit 16 of the register into bits 0 through 15 of the result.
Instruction Set 9-65 icbi Instruction Cache Block Invalidate 9.Instruction Set icbi Instruction Cache Block Invalidate EA ← (RA | 0) + (RB) ICBI(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-66 PPC405 Core User’s Manual icbt Instruction Cache Block Touch icbt Instruction Cache Block Touch EA ← (RA|0) + (RB) ICBT(EA) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-67 iccci Instruction Cache Congruence Class Invalidate iccci Instruction Cache Congruence Class Invalidate EA ← (RA|0) + (RB) ICCCI(ICU cache arra y) This instruction inv alidates the entire ICU cache arra y . The EA is not used; previous implementations hav e used the EA f or protection chec ks .
9-68 PPC405 Core User’s Manual icread Instruction Cache Read icread Instruction Cache Read EA ← (RA|0) + (RB) if ((CCR0[CIS] = 0) ∧ (CCR0[CWS] = 0)) then (ICDBDR) ← (i-cache data, wa y A) if (.
Instruction Set 9-69 icread Instruction Cache Read The instruction pipeline does not automatically wait f or data from icread to arrive at the ICDBDR bef ore attempting to use the contents of the ICDBDR. Theref ore, inser t an isync instruction between icread and mficdbdr .
9-70 PPC405 Core User’s Manual isync Instruction Synchronize isync Instruction Synchronize The isync instruction is a context synchronizing instruction. isync provides an ordering function f or the eff ects of all instructions ex ecuted b y the processor .
Instruction Set 9-71 lbz Load Byte and Zero lbz Load Byte and Zero EA ← (RA|0) + EXTS(D) (R T) ← 24 0 || MS(EA,1) An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-72 PPC405 Core User’s Manual lbzu Load Byte and Zero with Update lbzu Load Byte and Zero with Update EA ← (RA|0) + EXTS(D) (RA) ← EA (R T) ← 24 0 || MS(EA,1) An eff ectiv e address (EA) is f or med by adding a displacement to a base address .
Instruction Set 9-73 lbzux Load Byte and Zero with Update Indexed lbzux Load Byte and Zero with Update Indexed EA ← (RA|0) + (RB) (RA) ← EA (R T) ← 24 0 || MS(EA,1) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-74 PPC405 Core User’s Manual lbzx Load Byte and Zero Indexed lbzx Load Byte and Zero Indexed EA ← (RA|0) + (RB) (R T) ← 24 0 || MS(EA,1) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-75 lha Load Halfword Algebraic 9.Instruction Set lha Load Halfword Algebraic EA ← (RA|0) + EXTS(D) (R T) ← EXTS(MS(EA,2)) An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-76 PPC405 Core User’s Manual lhau Load Halfword Algebraic with Update lhau Load Halfword Algebraic with Update EA ← (RA) + EXTS(D) (RA) ← EA (R T) ← EXTS(MS(EA,2)) An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA.
Instruction Set 9-77 lhaux Load Halfword Algebraic with Update Indexed lhaux Load Halfword Algebraic with Update Indexed EA ← (RA) + (RB) (RA) ← EA (R T) ← EXTS(MS(EA,2)) An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
9-78 PPC405 Core User’s Manual lhax Load Halfword Algebraic Indexed lhax Load Halfword Algebraic Indexed EA ← (RA|0) + (RB) (R T) ← EXTS(MS(EA,2)) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-79 lhbrx Load Halfword Byte-Reverse Indexed lhbrx Load Halfword Byte-Reverse Indexed EA ← (RA|0) + (RB) (R T) ← 16 0 || MS(EA +1,1) || MS(EA,1) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-80 PPC405 Core User’s Manual lhz Load Halfword and Zero lhz Load Halfword and Zero EA ← (RA|0) + EXTS(D) (R T) ← 16 0 || MS(EA,2) An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
Instruction Set 9-81 lhzu Load Halfword and Zero with Update lhzu Load Halfword and Zero with Update EA ← (RA) + EXTS(D) (RA) ← EA (R T) ← 16 0 || MS(EA,2) An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA.
9-82 PPC405 Core User’s Manual lhzux Load Halfword and Zero with Update Indexed lhzux Load Halfword and Zero with Update Indexed EA ← (RA) + (RB) (RA) ← EA (R T) ← 16 0 || MS(EA,2) An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
Instruction Set 9-83 lhzx Load Halfword and Zero Indexed lhzx Load Halfword and Zero Indexed EA ← (RA|0) + (RB) (R T) ← 16 0 || MS(EA,2) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-84 PPC405 Core User’s Manual lmw Load Multiple Word lmw Load Multiple Word EA ← (RA|0) + EXTS(D) r ← RT do while r ≤ 31 if ((r ≠ RA) ∨ (r = 31)) then (GPR(r)) ← MS(EA,4) r ← r+1 EA ← E A+4 An eff ectiv e address (EA) is f or med by adding a displacement to a base address .
Instruction Set 9-85 lswi Load String Word Immediate lswi Load String Word Immediate EA ← (RA|0) if NB = 0 then CNT ← 32 else CNT ← NB n ← CNT R FINAL ← ((R T + CEIL(CNT/4) – 1) % 32) r .
9-86 PPC405 Core User’s Manual lswi Load String Word Immediate In v alid Instruction Forms • Reser ved fields • RA is in the range of registers to be loaded • R A=R T=0 Arc hitecture Note This instruction is par t of the P o werPC User Instruction Set Architecture.
Instruction Set 9-87 lswx Load String Word Indexed lswx Load String Word Indexed EA ← (RA|0) + (RB) CNT ← XER[TBC] n ← CNT R FINAL ← ((R T + CEIL(CNT/4) – 1) % 32) r ← RT – 1 i ← 0 do .
9-88 PPC405 Core User’s Manual lswx Load String Word Indexed In v alid Instruction Forms • Reser ved fields • RA or RB is in the range of registers to be loaded. • R A=R T=0 Programming Note If XER[TBC] = 0, the contents of register RT are unchanged and ls wx is treated as a no-op .
Instruction Set 9-89 lwarx Load Word and Reserve Indexed lwarx Load Word and Reserve Indexed EA ← (RA|0) + (RB) RESER VE ← 1 (R T) ← MS(EA,4) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-90 PPC405 Core User’s Manual lwbrx Load Word Byte-Reverse Indexed lwbrx Load Word Byte-Reverse Index ed EA ← (RA|0) + (RB) (R T) ← MS(EA+3,1) || MS(EA+2,1) || MS(EA+1,1) || MS(EA,1) An eff ectiv e address (EA) is f or med by adding an inde x to a base address .
Instruction Set 9-91 lwz Load Word and Zero lwz Load Word and Zero EA ← (RA|0) + EXTS(D) (R T) ← MS(EA,4) An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-92 PPC405 Core User’s Manual lwzu Load Word and Zero with Update lwzu Load Word and Zero with Update EA ← (RA) + EXTS(D) (RA) ← EA (R T) ← MS(EA,4) An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA.
Instruction Set 9-93 lwzux Load Word and Zero with Update Indexed lwzux Load Word and Zero with Update Indexed EA ← (RA) + (RB) (RA) ← EA (R T) ← MS(EA,4) An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
9-94 PPC405 Core User’s Manual lwzx Load Word and Zero Indexed lwzx Load Word and Zero Indexed EA ← (RA|0) + (RB) (R T) ← MS(EA,4) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-95 macchw Multiply Accumulate Cross Halfword to Word Modulo Signed macchw Multiply Accumulate Cross Halfword to Word Modulo Signed prod 0:31 ← (RA) 16:31 x (RB) 0:15 signed temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The low-order halfw ord of RA is multiplied b y the high-order halfword of RB .
9-96 PPC405 Core User’s Manual macchws Multiply Accumulate Cross Halfword to Word Saturate Signed macchws Multiply Accumulate Cross Halfword to Word Saturate Signed prod 0:31 ← (RA) 16:31 x (RB) 0.
Instruction Set 9-97 macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned prod 0:31 ← (RA) 16:31 x (RB) 0:15 un.
9-98 PPC405 Core User’s Manual macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned prod 0:31 ← (RA) 16:31 x (RB) 0:15 unsigned temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The low-order halfw ord of RA is multiplied b y the high-order halfword of RB .
Instruction Set 9-99 machhw Multiply Accumulate High Halfword to Word Modulo Signed machhw Multiply Accumulate High Halfword to Word Modulo Signed prod 0:31 ← (RA) 0:15 x (RB) 0:15 signed temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The high-order halfword of RA is multiplied b y the high-order halfword of RB .
9-100 PPC405 Core User’s Manual machhws Multiply Accumulate High Halfword to Word Saturate Signed machhws Multiply Accumulate High Halfword to Word Saturate Signed prod 0:31 ← (RA) 0:15 x (RB) 0:1.
Instruction Set 9-101 machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned prod 0:31 ← (RA) 0:15 x (RB) 0:15 unsi.
9-102 PPC405 Core User’s Manual machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned prod 0:31 ← (RA) 0:15 x (RB) 0:15 unsigned temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The high-order halfword of RA is multiplied b y the high-order halfw ord of RB.
Instruction Set 9-103 maclhw Multiply Accumulate Low Halfword to Word Modulo Signed maclhw Multiply Accumulate Low Halfword to Word Modulo Signed prod 0:31 ← (RA) 16:31 x (RB) 16:31 signed temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The low-order halfw ord of RA is multiplied b y the low-order halfword of RB .
9-104 PPC405 Core User’s Manual maclhws Multiply Accumulate Low Halfword to Word Saturate Signed maclhws Multiply Accumulate Low Halfword to Word Saturate Signed prod 0:31 ← (RA) 16:31 x (RB) 16:3.
Instruction Set 9-105 maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned prod 0:31 ← (RA) 16:31 x (RB) 16:31 unsi.
9-106 PPC405 Core User’s Manual maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned prod 0:31 ← (RA) 16:31 x (RB) 16:31 unsigned temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 The low-order halfw ord of RA is multiplied b y the low-order halfword of RB .
Instruction Set 9-107 mcrf Move Condition Register Field mcrf Move Condition Register Field m ← BF A n ← BF (CR[CRn]) ← (CR[CRm]) The contents of the CR field specified by the BF A field are placed into the CR field specified b y the BF field.
9-108 PPC405 Core User’s Manual mcrxr Move to Condition Register from XER 9.Instruction Set mcrxr Move to Condition Register from XER n ← BF (CR[CRn]) ← XER 0:3 XER 0:3 ← 4 0 The contents of XER 0:3 are placed into the CR field specified by the BF field.
Instruction Set 9-109 mfcr Move From Condition Register mfcr Move From Condition Register (R T) ← (CR) The contents of the CR are placed into register R T .
9-110 PPC405 Core User’s Manual mfdcr Move from Device Control Register mfdcr Move from Device Control Register DCRN ← DCRF 5:9 || DCRF 0:4 (R T) ← (DCR(DCRN)) The contents of the DCR specified by the DCRF field are placed into register R T . If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Instruction Set 9-111 mfmsr Move From Machine State Register 9.Instruction Set mfmsr Move From Machine State Register (R T) ← (MSR) The contents of the MSR are placed into register R T . If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
9-112 PPC405 Core User’s Manual mfspr Move From Special Purpose Register mfspr Move From Special Purpose Register SPRN ← SPRF 5:9 || SPRF 0:4 (R T) ← (SPR(SPRN)) The contents of the SPR specified by the SPRF field are placed into register R T .
Instruction Set 9-113 mfspr Move From Special Purpose Register T able 9-19. Extended Mnemonics for mfspr Mnemonic Operands Function Other Registers Changed mfccr0 mfctr mfdac1 mfdac2 mfdear mfdbcr0 mf.
9-114 PPC405 Core User’s Manual mftb Move From Time Base mftb Move From Time Base TBRN ← TBRF 5:9 || TBRF 0:4 (R T) ← (TBR(TBRN)) The contents of the time base register (TBR) specified by the TBRF field are placed into register R T . The f ollowing tab le lists the TBRN and TBRF v alues.
Instruction Set 9-115 mftb Move From Time Base Arc hitecture Note This instruction is par t of the IBM P o werPC Embedded Vir tual Environment. T able 9-21. Extended Mnemonics for mftb Mnemonic Operands Function Other Registers Altered mftb R T Move the contents of TBL into R T .
9-116 PPC405 Core User’s Manual mtcrf Move to Condition Register Fields mtcrf Move to Condition Register Fields mask ← 4 (FXM 0 ) || 4 (FXM 1 ) || ... || 4 (FXM 6 ) || 4 (FXM 7 ) (CR) ← ((RS) ∧ mask) ∨ ((CR) ∧¬ mask) Some or all of the contents of register RS are placed into the CR as specified by the FXM field.
Instruction Set 9-117 mtdcr Move To Device Control Register mtdcr Move T o Device Control Register DCRN ← DCRF 5:9 || DCRF 0:4 (DCR(DCRN)) ← (RS) The contents of register RS are placed into the DCR specified by the DCRF field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
9-118 PPC405 Core User’s Manual mtmsr Move To Machine State Register 9.Instruction Set mtmsr Move T o Machine State Register (MSR) ← (RS) The contents of register RS are placed into the MSR. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Instruction Set 9-119 mtspr Move To Special Purpose Register mtspr Move T o Special Purpose Register SPRN ← SPRF 5:9 || SPRF 0:4 (SPR(SPRN)) ← (RS) The contents of register RS are placed into register R T . See “Special Pur pose Registers” on page 10-2 f or a listing of SPR mnemonics and corresponding SPRN and SPRF values .
9-120 PPC405 Core User’s Manual mtspr Move To Special Purpose Register T able 9-23. Extended Mnemonics for mtspr Mnemonic Operands Function Other Registers Altered mtccr0 mtctr mtdac1 mtdac2 mtdbcr0.
Instruction Set 9-121 mulchw Multiply Cross Halfword to Word Signed 9.Instruction Set mulchw Multiply Cross Halfword to Word Signed (R T) 0 :31 ← (RA) 16:31 x (RB) 0:15 signed The low-order halfw ord of RA is multiplied b y the high-order halfword of RB .
9-122 PPC405 Core User’s Manual mulchwu Multiply Cross Halfword to Word Unsigned mulchwu Multiply Cross Halfword to Word Unsigned (R T) 0 : 31 ← (RA) 16:31 x (RB) 0:15 unsigned The low-order halfw ord of RA is multiplied b y the high-order halfword of RB .
Instruction Set 9-123 mulhhw Multiply High Halfword to Word Signed mulhhw Multiply High Halfword to Word Signed (R T) 0 : 31 ← (RA) 0:15 x (RB) 0:15 signed The high-order halfword of RA is multiplied b y the high-order halfword of RB . The resulting signed product replaces the contents of R T .
9-124 PPC405 Core User’s Manual mulhhwu Multiply High Halfword to Word Unsigned mulhhwu Multiply High Halfword to Word Unsigned (R T) 0 : 31 ← (RA) 0:15 x (RB) 0:15 unsigned The high-order halfword of RA is multiplied b y the high-order halfword of RB .
Instruction Set 9-125 mulhw Multiply High Word mulhw Multiply High Word prod 0:63 ← (RA) × (RB) signed (R T) ← prod 0:31 The 64-bit signed product of registers RA and RB is f or med. The most significant 32 bits of the result is placed into register R T .
9-126 PPC405 Core User’s Manual mulhwu Multiply High Word Unsigned mulhwu Multiply High Word Unsigned prod 0:63 ← (RA) × (RB) unsigned (R T) ← prod 0:31 The 64-bit unsigned product of registers RA and RB is f or med. The most significant 32 bits of the result are placed into register R T .
Instruction Set 9-127 mullhw Multiply Low Halfword to Word Signed mullhw Multiply High Halfword to Word Signed (R T) 0 : 31 ← (RA) 16:31 x (RB) 16:31 signed The low-order halfw ord of RA is multiplied b y the low-order halfword of RB . The resulting signed product replaces the contents of R T .
9-128 PPC405 Core User’s Manual mullhwu Multiply Low Halfword to Word Unsigned mullhwu Multiply High Halfword to Word Unsigned (R T) 0 : 31 ← (RA) 16:31 x (RB) 16:31 unsigned The low-order halfw ord of RA is multiplied b y the low-order halfword of RB .
Instruction Set 9-129 mulli Multiply Low Immediate mulli Multiply Low Immediate prod 0:47 ← (RA) × EXTS(IM) signed (R T) ← prod 16:47 The 48-bit product of register RA and the sign-e xtended IM field is f ormed. Both register RA and the IM field are inter preted as signed quantities.
9-130 PPC405 Core User’s Manual mullw Multiply Low Word mullw Multiply Low Word prod 0:63 ← (RA) × (RB) signed (R T) ← prod 32:63 The 64-bit signed product of register RA and register RB is f ormed. The least significant 32 bits of the result is placed into register R T .
Instruction Set 9-131 nand NAND nand NAND (RA) ←¬ ((RS) ∧ (RB)) The contents of register RS is ANDed with the contents of register RB; the ones complement of the result is placed into register RA.
9-132 PPC405 Core User’s Manual neg Negate neg Negate (R T) ←¬ (RA) + 1 The twos complement of the contents of register RA are placed into register R T .
Instruction Set 9-133 nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed nprod 0:31 ← –((RA) 16:31 .
9-134 PPC405 Core User’s Manual nmacchws Negative Multiply Accumulate Cross Halfword to Word Saturate Signed nmacchws Negative Multiply Accumulate High Halfword to Word Saturate Signed nprod 0:31 .
Instruction Set 9-135 nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed nprod 0:31 ← –((RA) 0:15 x (RB) 0:15 ) signed temp 0:32 ← nprod 0:31 + (R T) (R T) ← temp 1:32 The high-order halfword of RA is multiplied b y the high-order halfword of RB .
9-136 PPC405 Core User’s Manual nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nprod 0:31 ←.
Instruction Set 9-137 nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed nprod 0:31 ← –((RA) 16:31 x (RB) 16:31 ) signed temp 0:32 ← nprod 0:31 + (R T) (R T) ← temp 1:32 The low-order halfw ord of RA is multiplied b y the low-order halfword of RB .
9-138 PPC405 Core User’s Manual nmaclhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmaclhws Negative Multiply Accumulate Low Halfword to Word Saturate Signed nprod 0:31 ← .
Instruction Set 9-139 nor NOR nor NOR (RA) ←¬ ((RS) ∨ (RB)) The contents of register RS is ORed with the contents of register RB; the ones complement of the result is placed into register RA.
9-140 PPC405 Core User’s Manual or OR or OR (RA) ← (RS) ∨ (RB) The contents of register RS is ORed with the contents of register RB; the result is placed into register RA. Registers Altered •R A • CR[CR0] L T , GT , EQ, SO if Rc contains 1 Arc hitecture Note This instruction is par t of the P o werPC User Instruction Set Architecture.
Instruction Set 9-141 orc OR with Complement orc OR with Complement (RA) ← (RS) ∨¬ (RB) The contents of register RS is ORed with the ones complement of the contents of register RB; the result is placed into register RA.
9-142 PPC405 Core User’s Manual ori OR Immediate ori OR Immediate (RA) ← (RS) ∨ ( 16 0| |I M ) The IM field is e xtended to 32 bits by concatenating 16 0-bits on the left. Register RS is ORed with the e xtended IM field; the result is placed into register RA.
Instruction Set 9-143 oris OR Immediate Shifted oris OR Immediate Shifted (RA) ← (RS) ∨ (IM || 16 0) The IM Field is e xtended to 32 bits by concatenating 16 0-bits on the right. Register RS is ORed with the e xtended IM field and the result is placed into register RA.
9-144 PPC405 Core User’s Manual rfci Return From Critical Interrupt rfci Return From Critical Interrupt (PC) ← (SRR2) (MSR ) ← (SRR3) The program counter (PC) is restored with the contents of SRR2 and the MSR is restored with the contents of SRR3.
Instruction Set 9-145 rfi Return From Interrupt rfi Return From Interrupt (PC) ← (SRR0) (MSR) ← (SRR1) The program counter (PC) is restored with the contents of SRR0 and the MSR is restored with the contents of SRR1. Instruction ex ecution returns to the address contained in the PC.
9-146 PPC405 Core User’s Manual rlwimi Rotate Left Word Immediate then Mask Insert rlwimi Rotate Left Word Immediate then Mask Insert r ← RO TL((RS), SH) m ← MASK(MB, ME) (RA) ← (r ∧ m) ∨ ((RA) ∧¬ m) The contents of register RS are rotated left by the n umber of bit positions specified in the SH field.
Instruction Set 9-147 rlwinm Rotate Left Word Immediate then AND with Mask rlwinm Rotate Left Word Immediate then AND with Mask r ← RO TL((RS), SH) m ← MASK(MB, ME) (RA) ← r ∧ m The contents of register RS are rotated left by the n umber of bit positions specified in the SH field.
9-148 PPC405 Core User’s Manual rlwinm Rotate Left Word Immediate then AND with Mask clrrwi RA, RS , n Clear r ight immediate. ( n < 32) (RA) 32-n:31 ← n 0 Extended mnemonic fo r rlwinm RA,RS,0,0,31 − n clrrwi. Extended mnemonic f or rlwinm. RA,RS,0,0,31 − n CR[CR0] extl wi RA, RS, n, b Extract and left justify immediate.
Instruction Set 9-149 rlwinm Rotate Left Word Immediate then AND with Mask srwi RA, RS, n Shift right immediate. ( n < 32) (RA) n:31 ← (RS) 0:31-n (RA) 0:n-1 ← n 0 Extended mnemonic f or rlwinm RA,RS,32 − n,n,31 srwi. Extended mnemonic f or rlwinm.
9-150 PPC405 Core User’s Manual rlwnm Rotate Left Word then AND with Mask rlwnm Rotate Left Word then AND with Mask r ← RO TL((RS), (RB) 27:31 ) m ← MASK(MB, ME) (RA) ← r ∧ m The contents of register RS are rotated left by the number of bit positions specified by the contents of register RB 27:31 .
Instruction Set 9-151 sc System Call sc System Call (SRR1) ← (MSR) (SRR0) ← (PC) PC ← EVPR 0:15 || 0x0C00 (MSR[WE, EE, PR, DR, IR]) ← 0 A system call e xception is generated. The contents of the MSR are copied into SRR1 and (4 + address of sc instr uction) is placed into SRR0.
9-152 PPC405 Core User’s Manual slw Shift Left Word slw Shift Left Word n ← (RB) 27:31 r ← RO TL((RS), n) if (RB) 26 = 0 then m ← MASK(0, 31 – n) else m ← 32 0 (RA) ← r ∧ m The contents of register RS are shifted left by the n umber of bits specified by the contents of register RB 27:31 .
Instruction Set 9-153 sraw Shift Right Algebraic Word sraw Shift Right Algebraic Word n ← (RB) 27:31 r ← RO TL((RS), 32 – n) if (RB) 26 = 0 then m ← MASK(n, 31) else m ← 32 0 s ← (RS) 0 (R.
9-154 PPC405 Core User’s Manual srawi Shift Right Algebraic Word Immediate srawi Shift Right Algebraic Word Immediate n ← SH r ← RO TL((RS), 32 – n) m ← MASK(n, 31) s ← (RS) 0 (RA) ← (r .
Instruction Set 9-155 srw Shift Right Word srw Shift Right Word n ← (RB) 27:31 r ← RO TL((RS), 32 – n) if (RB) 26 = 0 then m ← MASK(n, 31) else m ← 32 0 (RA) ← r ∧ m The contents of register RS are shifted right by the number of bits specified the contents of register RB 27:31 .
9-156 PPC405 Core User’s Manual stb Store Byte stb Store Byte EA ← (RA|0) + EXTS(D) MS(EA, 1) ← (RS) 24:31 An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
Instruction Set 9-157 stbu Store Byte with Update stbu Store Byte with Update EA ← (RA) + EXTS(D) MS(EA, 1) ← (RS) 24:31 (RA) ← EA An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA. The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-158 PPC405 Core User’s Manual stbux Store Byte with Update Indexed stbux Store Byte with Update Indexed EA ← (RA) + (RB) MS(EA, 1) ← (RS) 24:31 (RA) ← EA An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
Instruction Set 9-159 stbx Store Byte Indexed stbx Store Byte Indexed EA ← (RA|0) + (RB) MS(EA, 1) ← (RS) 24:31 An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
9-160 PPC405 Core User’s Manual sth Store Halfword 9.Instruction Set sth Store Halfword EA ← (RA|0) + EXTS(D) MS(EA, 2) ← (RS) 16:31 An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
Instruction Set 9-161 sthbrx Store Halfword Byte-Reverse Indexed sthbrx Store Halfword Byte-Reverse Indexed EA ← (RA|0) + (RB) MS(EA, 2) ← (RS) 24:31 || (RS) 16:23 An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
9-162 PPC405 Core User’s Manual sthu Store Halfword with Update sthu Store Halfword with Update EA ← (RA) + EXTS(D) MS(EA, 2) ← (RS) 16:31 (RA) ← EA An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA.
Instruction Set 9-163 sthux Store Halfword with Update Indexed sthux Store Halfword with Update Indexed EA ← (RA) + (RB) MS(EA, 2) ← (RS) 16:31 (RA) ← EA An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
9-164 PPC405 Core User’s Manual sthx Store Halfword Indexed sthx Store Halfword Indexed EA ← (RA|0) + (RB) MS(EA, 2) ← (RS) 16:31 An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB.
Instruction Set 9-165 stmw Store Multiple Word stmw Store Multiple Word EA ← (RA|0) + EXTS(D) r ← RS do while r ≤ 31 MS(EA, 4) ← (GPR(r)) r ← r+1 EA ← E A+4 An eff ectiv e address (EA) is f or med by adding a displacement to a base address .
9-166 PPC405 Core User’s Manual stswi Store String Word Immediate stswi Store String Word Immediate EA ← (RA|0) if NB = 0 then n ← 32 else n ← NB r ← RS – 1 i ← 0 do whil en>0 i fi=0 .
Instruction Set 9-167 stswx Store String Word Indexed stswx Store String Word Indexed EA ← (RA|0) + (RB) n ← XER[TBC] r ← RS – 1 i ← 0 do whil en>0 i fi=0 then r ← r+1 i fr=3 2 then r .
9-168 PPC405 Core User’s Manual stswx Store String Word Indexed How e ver , the architecture makes no statement regarding imprecise e xceptions related to sts wx when XER[TBC] = 0.
Instruction Set 9-169 stw Store Word stw Store Word EA ← (RA|0) + EXTS(D) MS(EA, 4) ← (RS) An eff ectiv e address (EA) is f or med by adding a displacement to a base address . The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-170 PPC405 Core User’s Manual stwbrx Store Word Byte-Reverse Indexed stwbrx Store Word Byte-Reverse Index ed EA ← (RA|0) + (RB) MS(EA, 4) ← (RS) 24:31 || (RS) 16:23 || (RS) 8:15 || (RS) 0:7 An EA is f or med by adding an inde x to a base address .
Instruction Set 9-171 stwcx. Store Word Conditional Indexed stwcx. Store Word Conditional Indexed EA ← (RA|0) + (RB) if RESER VE = 1 then MS(EA, 4) ← (RS) RESER VE ← 0 (CR[CR0]) ← 2 0 || 1 || XER so else (CR[CR0]) ← 2 0 || 0 || XER so An eff ectiv e address (EA) is f or med by adding an inde x to a base address .
9-172 PPC405 Core User’s Manual stwcx. Store Word Conditional Indexed Arc hitecture Note This instruction is par t of the P o werPC User Instruction Set Architecture.
Instruction Set 9-173 stwu Store Word with Update stwu Store Word with Update EA ← (RA) + EXTS(D) MS(EA, 4) ← (RS) (RA) ← EA An eff ectiv e address (EA) is f or med by adding a displacement to the base address in register RA. The displacement is obtained by sign-e xtending the 16-bit D field to 32 bits .
9-174 PPC405 Core User’s Manual stwux Store Word with Update Indexed stwux Store Word with Update Indexed EA ← (RA) + (RB) MS(EA, 4) ← (RS) (RA) ← EA An eff ectiv e address (EA) is f or med by adding an inde x to the base address in register RA.
Instruction Set 9-175 stwx Store Word Indexed stwx Store Word Indexed EA ← (RA|0) + (RB) MS(EA,4) ← (RS) An eff ectiv e address (EA) is f or med by adding an inde x to a base address . The inde x is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
9-176 PPC405 Core User’s Manual subf Subtract From subf Subtract From (R T) ←¬ (RA) + (RB) + 1 The sum of the ones complement of register RA, register RB, and 1 is stored into register R T .
Instruction Set 9-177 subfc Subtract From Carrying subfc Subtract From Carrying (R T) ←¬ (RA) + (RB) + 1 if ¬ (RA) + (RB) + 1 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, register RB, and 1 is stored into register R T .
9-178 PPC405 Core User’s Manual subfe Subtract From Extended subfe Subtract From Extended (R T) ←¬ (RA) + (RB) + XER[CA] if ¬ (RA) + (RB) + XER[CA] 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, register RB, and XER[CA] is placed into register R T .
Instruction Set 9-179 subfic Subtract From Immediate Carrying subfic Subtract From Immediate Carrying (R T) ←¬ (RA) + EXTS(IM) + 1 if ¬ (RA) + EXTS(IM) + 1 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of RA, the IM field sign-e xtended to 32 bits, and 1 is placed into register R T .
9-180 PPC405 Core User’s Manual subfme Subtract from Minus One Extended subfme Subtract from Minus One Extended (R T) ←¬ (RA) – 1 + XER[CA] if ¬ (RA) + 0xFFFF FFFF + XER[CA] 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, –1, and XER[CA] is placed into register R T .
Instruction Set 9-181 subfze Subtract from Zero Extended subfze Subtract from Zero Extended (R T) ←¬ (RA) + XER[CA] if ¬ (RA) + XER[CA] 2 32 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA and XER[CA] is stored into register R T .
9-182 PPC405 Core User’s Manual sync Synchronize sync Synchronize The sync instruction guarantees that all instructions initiated by the processor preceding sync will complete bef ore sync completes, and that no subsequent instructions will be initiated by the processor until after sync completes.
Instruction Set 9-183 tlbia TLB Invalidate All tlbia TLB Invalidate All All of the entries in the TLB are inv alidated and become unav ailab le f or translation b y clearing the v alid (V) bit in the TLBHI por tion of each TLB entr y . The rest of the fields in the TLB entr ies are unmodified.
9-184 PPC405 Core User’s Manual tlbre TLB Read Entry tlbre TLB Read Entry if WS 4 = 1 (R T) ← TLBLO[(RA 26:31 )] else (R T) ← TLBHI[(RA 26:31 )] (PID) ← TID from TLB[(RA 26:31 )] The contents of the selected TLB entr y is placed into register RT (and possib ly into PID).
Instruction Set 9-185 tlbre TLB Read Entry Arc hitecture Note This instruction par t of the IBM P o werPC Embedded Operating En vironment. T able 9-32. Extended Mnemonics for tlbre Mnemonic Operands Function Other Registers Altered tlbrehi R T , RA Load TLBHI por tion of the selected TLB entr y into R T .
9-186 PPC405 Core User’s Manual tlbsx TLB Search Indexed tlbsx TLB Search Indexed EA ← (RA|0) + (RB) if Rc = 1 CR[CR0] LT ← 0 CR[CR0] GT ← 0 CR[CR0] SO ← XER[SO] if V alid TLB entry matching.
Instruction Set 9-187 tlbsync TLB Synchronize tlbsync TLB Synchronize The tlbsync instruction is provided in the P o werPC architecture to support synchronization of TLB operations among the processors of a multi-processor system. In the PPC405 core, this instruction perf orms no operation, and is provided to f acilitate code por tability .
9-188 PPC405 Core User’s Manual tlbwe TLB Write Entry tlbwe TLB Write Entry if WS 4 = 1 TLBLO[(RA 26:31 )] ← (RS) else TLBHI[(RA 26:31 )] ← (RS) TID of TLB[(RA 26:31 )] ← (PID 24:31 ) The contents of the selected TLB entr y is replaced with the contents of register RS (and possibly PID).
Instruction Set 9-189 tlbwe TLB Write Entry If WS = 1 (TLBLO): RPN[0:21] ← R T[0:21] EX,WR ← RS[22:23] ZSEL[0:3] ← RS[24:27] WIMG ← RS[28:31] Arc hitecture Note This instruction par t of the IBM P o werPC Embedded Operating En vironment. T able 9-33.
9-190 PPC405 Core User’s Manual tw Trap Word tw Tr ap Word if ( ((RA) (RB) ∧ TO 0 =1 ) ∨ ((RA) (RB) ∧ TO 1 =1 ) ∨ ((RA) (RB) ∧ TO 2 =1 ) ∨ ((RA) (RB) ∧ TO 3 =1 ) ∨ ((RA) (RB) ∧ TO 4 = 1) ) then TRAP (see details below) Register RA is compared with register RB.
Instruction Set 9-191 tw Trap Word (SRR0) ← address of tw instruction (SRR1) ← (MSR) (ESR[PTR]) ← 1 (DBSR[TIE,IDE]) ← 1,1 (MSR[WE, EE, PR, DR, IR]) ← 0 PC ← EVPR 0:15 || 0x0700 If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
9-192 PPC405 Core User’s Manual tw Trap Word twlle RA, RB T rap if (RA) logically less than or equal to (RB). Extended mnemonic f or tw 6,RA,RB twllt RA, RB T rap if (RA) logically less than (RB). Extended mnemonic f or tw 2,RA,RB twlng RA, RB T rap if (RA) logically not greater than (RB).
Instruction Set 9-193 twi Trap Word Immediate twi Tr ap Word Immediate if ( ((RA) EXTS(IM) ∧ TO 0 =1 ) ∨ ((RA) EXTS(IM) ∧ TO 1 =1 ) ∨ ((RA) EXTS(IM) ∧ TO 2 =1 ) ∨ ((RA) EXTS(IM) ∧ TO 3 =.
9-194 PPC405 Core User’s Manual twi Trap Word Immediate (SRR0) ← address of twi instruction (SRR1) ← (MSR) (ESR[PTR]) ← 1 (DBSR[TIE,IDE]) ← 1,1 (MSR[WE, EE, PR, DR, IR]) ← 0 PC ← EVPR 0:.
Instruction Set 9-195 twi Trap Word Immediate twlnli RA, IM T rap if (RA) logically not less than EXTS(IM). Extended mnemonic f or twi 5,RA,IM twlti RA, IM T rap if (RA) less than EXTS(IM). Extended mnemonic f or twi 16,RA,IM twnei RA, IM T rap if (RA) not equal to EXTS(IM).
9-196 PPC405 Core User’s Manual wrtee Write External Enable wrtee Write External Enable MSR[EE] ← (RS) 16 The MSR[EE] is set to the v alue specified by bit 16 of register RS . If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Instruction Set 9-197 wrteei Write External Enable Immediate wrteei Write External Enable Immediate MSR[EE] ← E MSR[EE] is set to the v alue specified by the E field.
9-198 PPC405 Core User’s Manual xor XOR xor XOR (RA) ← (RS) ⊕ (RB) The contents of register RS are XORed with the contents of register RB; the result is placed into register RA.
Instruction Set 9-199 xori XOR Immediate xori XOR Immediate (RA) ← (RS) ⊕ ( 16 0 || IM) The IM field is e xtended to 32 bits by concatenating 16 0-bits on the left. The contents of register RS are XORed with the e xtended IM field; the result is placed into register RA.
9-200 PPC405 Core User’s Manual xoris XOR Immediate Shifted xoris XOR Immediate Shifted (RA) ← (RS) ⊕ (IM || 16 0) The IM field is e xtended to 32 bits by concatenating 16 0-bits on the right. The contents of register RS are XORed with the e xtended IM field; the result is placed into register RA.
Register Summary 10-1 Chapter 10. Register Summary All registers contained in the PPC405 core are architected as 32-bits. T able 10-1 and T able 10-2 define the addressing required to access the registers. The pages f ollo wing these tables define the bit usage within each register .
10-2 PPC405 Core User’s Manual 10.5 Special Purpose Register s Special Pur pose Registers (SPRs), which are par t of the P ow erPC Embedded Environment, are accessed using the mtspr and mfspr instr uctions. SPRs control the use of the deb ug f acilities, timers, interrupts, stor age control attributes, and other architected processor resources .
Register Summary 10-3 ICCR Instr uction Cache Cachability Register 1019 0x3FB 0x37F Read/Wr ite ICDBDR Instruction Cache Debug Data Register 979 0x3D3 0x27E Read-only LR Link Register 8 0x008 0x100 Re.
10-4 PPC405 Core User’s Manual 10.6 Time Base Register s The P o werPC Architecture pro vides a 64-bit time base. Chapter 6, “Timer F acilities, ” descr ibes the architected time base. In the PPC405 core, the time base is implemented as two 32-bit time base registers (TBRs).
Register Summary 10-5 10.Register Summary 10.8 Alphabetical Listing of PPC405 Register s The f ollowing pages list the registers a v ailable in the PPC405 core.
CCR0 Core Configuration Register 0 10-6 PPC405 Core User’s Manual CCR0 SPR 0x3B3 See “Core Configuration Register 0 (CCR0)” on page 4-11. Figure 10-1.
CCR0 (cont.) Core Configuration Register 0 Register Summary 10-7 21 PFNC ICU Prefetching f or Non-Cachab le Regions 0 Disables pref etching f or non-cachab le regions 1 Enables pref etching f or non-c.
CR Condition Register 10-8 PPC405 Core User’s Manual CR See “Condition Register (CR)” on page 2-10. Figure 10-2. Condition Register (CR) 0:3 CR0 Condition Register Field 0 4:7 CR1 Condition Regi.
CTR Count Register Register Summary 10-9 CTR SPR 0x009 See “Count Register (CTR)” on page 2-6. Figure 10-3. Count Register (CTR) 0:31 Count Used as count f or branch conditional with decrement instructions, or as address f or branch-to-counter instructions.
DAC1–DAC2 Data Address Compare Registers 10-10 PPC405 Core User’s Manual DAC1–DA C2 SPR 0x3F6–0x3F7 See “Data Address Compare Registers (D A C1–D A C2)” on page 8-9. Figure 10-4. Data Address Compare Registers (D AC1–D A C2) 0:31 Data Address Compare (D A C) b yte address DBCR0[D1S] determines which address bits are e xamined.
DBCR0 Debug Control Register 0 Register Summary 10-11 DBCR0 SPR 0x3F2 See “Debug Control Registers” on page 8-4. Figure 10-5. Debug Contr ol Register 0 (DBCR0) 0 EDM Exter nal Debug Mode 0 Disable.
DBCR0 (cont.) Debug Control Register 0 10-12 PPC405 Core User’s Manual 11 IA12X Enable Instruction Address Exclusive Range Compare 1–2 0 Inclusive 1 Exclusive Selects the range defined b y IA C1 and IA C2 to be inclusive or e xclusiv e .
DBCR1 Debug Control Register 1 Register Summary 10-13 DBCR1 SPR 0x3BD See “Debug Control Registers” on page 8-4. Figure 10-6. Debug Contr ol Register 1 (DBCR1) 0 D1R D AC1 Read Deb ug Event 0 Disa.
DBCR1 (cont.) Debug Control Register 1 10-14 PPC405 Core User’s Manual 12:13 D V1M Data V alue Compare 1 Mode 00 Undefined 01 AND 10 OR 11 AND-OR T ype of data comparison used: All bytes selected b y DBCR1[D V1BE] must compare to the appropriate bytes of D VC1.
DBSR Debug Status Register Register Summary 10-15 DBSR SPR 0x3F0 Read/Clear See “Debug Status Register (DBSR)” on page 8-7. Figure 10-7. Debug Status Register (DBSR) 0 IC Instr uction Completion D.
DBSR (cont.) Debug Status Register 10-16 PPC405 Core User’s Manual 11 IDE Imprecise Debug Ev ent 0 No circumstance that would cause a debug e v ent (if MSR[DE] = 1) occurred 1 A debug e v ent would .
DCCR Data Cache Cacheability Register Register Summary 10-17 DCCR SPR 0x3F A See “Real-Mode Storage Attribute Control” on page 7-17. Figure 10-8. Data Cache Cachability Register (DCCR) 0 S0 0 Nonc.
DCCR (cont.) Data Cache Cacheability Register 10-18 PPC405 Core User’s Manual 16 S16 0 Noncachable 1 Cachable 0x8000 0000 – 0x87FF FFFF 17 S17 0 Noncachable 1 Cachable 0x8800 0000 – 0x8FFF FFFF .
DCWR Data Cache Write-through Register Register Summary 10-19 DCWR SPR 0x3B A See “Real-Mode Storage Attribute Control” on page 7-17. Figure 10-9. Data Cache Write-through Register (DCWR) 0 W0 0 W.
DCWR (cont.) Data Cache Write-through Register 10-20 PPC405 Core User’s Manual 16 W16 0 Wr ite-back 1 Write-through 0x8000 0000 – 0x87FF FFFF 17 W17 0 Wr ite-back 1 Write-through 0x8800 0000 – 0.
DEAR Data Exception Address Register Register Summary 10-21 DEAR SPR 0x3D5 See “Data Exception Address Register (DEAR)” on page 5-13. Figure 10-10.
DVC1–DVC2 Data Value Compare Registers 10-22 PPC405 Core User’s Manual DVCR1–DVCR2 SPR 0x3B6–0x3B7 See “Data V alue Compare Registers (D VC1–D VC2)” on page 8-10.
ESR Exception Syndrome Register Register Summary 10-23 ESR SPR 0x3D4 See “Exception Syndrome Register (ESR)” on page 5-11. Figure 10-12. Exception Syndrome Register (ESR) 0 MCI Machine check—instruction 0 Instruction machine check did not occur .
ESR (cont.) Exception Syndrome Register 10-24 PPC405 Core User’s Manual 16 U0F Data storage interrupt—U0 fault 0 Excepting instruction did not cause a U0 f ault.
EVPR Exception Vector Prefix Register Register Summary 10-25 EVPR SPR 0x3D6 See “Exception V ector Prefix Register (EVPR)” on page 5-10. Figure 10-13.
GPR0–GPR31 General Purpose Registers 10-26 PPC405 Core User’s Manual GPR0–GPR31 See “General Purpose Registers (R0-R31)” on page 2-5. Figure 10-14.
IAC1–IAC4 Instruction Address Compare Registers Register Summary 10-27 IAC1–IAC4 SPR 0x3F4–0x3F5 See “Instruction Address Compare Registers (IAC1–IA C4)” on page 8-9. Figure 10-15. Instruction Address Compare Registers (IA C1–IAC4) 0:29 Instruction Address Compare word address Omit two low-order bits of complete address.
ICCR Instruction Cache Cacheability Register 10-28 PPC405 Core User’s Manual ICCR SPR 0x3FB See “Real-Mode Storage Attribute Control” on page 7-17.
ICCR (cont.) Instruction Cache Cacheability Register Register Summary 10-29 16 S16 0 Noncachable 1 Cachable 0x8000 0000 – 0x87FF FFFF 17 S17 0 Noncachable 1 Cachable 0x8800 0000 – 0x8FFF FFFF 18 S.
ICDBDR Instruction Cache Debug Data Register 10-30 PPC405 Core User’s Manual ICDBDR SPR 0x3D3 Read-Only See “ICU Debugging” on page 4-14. ICU tag inf ormation is placed into the ICDBDR as shown: Figure 10-17. Instruction Cache Debug Data Register (ICDBDR) 0:31 Instruction cache information See icread , page -68.
LR Link Register Register Summary 10-31 LR SPR 0x008 See “Link Register (LR)” on page 2-7. Figure 10-18. Link Register (LR) 0:31 Link Register contents If (LR) represents an instr uction address, LR 30:31 should be 0.
MSR Machine State Register 10-32 PPC405 Core User’s Manual MSR See “Machine State Register (MSR)” on page 5-7. Figure 10-19. Machine State Register (MSR) 0:5 Reser ved 6 AP A uxiliar y Processor A v ailable 0 APU not av ailable . 1 APU av ailable .
MSR (cont.) Machine State Register Register Summary 10-33 20 FE0 Floating-point e xception mode 0 0 If MSR[FE1] = 0, ignore exceptions mode; if MSR[FE1] = 1, imprecise nonrecov erab le mode 1 If MSR[FE1] = 0, imprecise recover able mode; if MSR[FE1] = 1, precise mode 21 D WE Debug W ait Enable 0 Debug w ait mode is disabled.
PID Process ID 10-34 PPC405 Core User’s Manual PID SPR 0x3B1 See “Address T ranslation” on page 7-1. Figure 10-20. Process ID (PID) 0:23 Reser ved 24:31 Process ID 0 23 24 31.
PIT Programmable Interval Timer Register Summary 10-35 PIT SPR 0x3DB See “Programmab le Interval Timer (PIT)” on page 6-4. Figure 10-21. Programmab le Interval Timer (PIT) 0:31 Programmed interval.
PVR Processor Version Register 10-36 PPC405 Core User’s Manual PVR SPR 0x11F Read-Only See “Processor V ersion Register (PVR)” on page 2-10. Figure 10-22. Processor V ersion Register (PVR) 0:11 O WN Owner Identifier Identifies the owner of a core 12:15 PCF Processor Core F amily Identifies the processor core f amily .
SGR Storage Guarded Register Register Summary 10-37 SGR SPR 0x3B9 See “Real-Mode Storage Attribute Control” on page 7-17. Figure 10-23. Storage Guarded Register (SGR) 0 G0 0 Nor mal 1 Guarded 0x00.
SGR (cont.) Storage Guarded Register 10-38 PPC405 Core User’s Manual 16 G16 0 Nor mal 1 Guarded 0x8000 0000 – 0x87FF FFFF 17 G17 0 Nor mal 1 Guarded 0x8800 0000 – 0x8FFF FFFF 18 G18 0 Nor mal 1 .
SLER Storage Little-Endian Register Register Summary 10-39 SLER SPR 0x3BB See “Real-Mode Storage Attribute Control” on page 7-17. Figure 10-24. Storage Little-Endian Register (SLER) 0 S0 0 Big end.
SLER (cont.) Storage Little-Endian Register 10-40 PPC405 Core User’s Manual 16 S16 0 Big endian 1 Little endian 0x8000 0000 – 0x87FF FFFF 17 S17 0 Big endian 1 Little endian 0x8800 0000 – 0x8FFF.
SPRG0–SPRG7 Special Purpose Registers General Register Summary 10-41 SPRG0–SPRG7 SPR 0x104–0x107 (User Read-only); 0x110–0x117 (Privileged Read/Write) See “Special Pur pose Register General (SPRG0–SPRG7)” on page 2-9. Figure 10-25. Special Purpose Registers General (SPRG0–SPRG7) 0:31 General data Software v alue; no hardware usage .
SRR0 Save/Restore Register 0 10-42 PPC405 Core User’s Manual SRR0 SPR 0x01A See “Sav e/Restore Registers 0 and 1 (SRR0–SRR1)” on page 5-9. . Figure 10-26. Save/Restore Register 0 (SRR0) 0:29 SRR0 receives an instruction address when a non-critical interrupt is taken; the Program Counter is restored from SRR0 when rfi ex ecutes .
SRR1 Save/Restore Register 1 Register Summary 10-43 SRR1 SPR 0x01B See “Sav e/Restore Registers 0 and 1 (SRR0–SRR1)” on page 5-9. Figure 10-27. Save/Restore Register 1 (SRR1) 0:31 SRR1 receives a cop y of the MSR when an interrupt is taken; the MSR is restored from SRR1 when rfi e x ecutes .
SRR2 Save/Restore Register 2 10-44 PPC405 Core User’s Manual SRR2 SPR 0x3DE See “Sav e/Restore Registers 2 and 3 (SRR2–SRR3)” on page 5-9. . Figure 10-28. Save/Restore Register 2 (SRR2) 0:29 SRR2 receives an instruction address when a critical interrupt is taken; the Program Counter is restored from SRR2 when rfci e x ecutes .
SRR3 Save/Restore Register 3 Register Summary 10-45 SRR3 SPR 0x3DF See “Sav e/Restore Registers 2 and 3 (SRR2–SRR3)” on page 5-9. Figure 10-29. Save/Restore Register 3 (SRR3) 0:31 SRR3 receives a cop y of the MSR when a critical interr upt is taken; the MSR is restored from SRR3 when rfci e x ecutes .
SU0R Storage User-Defined 0 Register 10-46 PPC405 Core User’s Manual SU0R SPR 0x3BC See “Real-Mode Storage Attribute Control” on page 7-17. Figure 10-30.
SU0R (cont.) Storage User-Defined 0 Register Register Summary 10-47 16 UD16 0 Storage compression is off 1 Storage compression is on 0x8000 0000 – 0x87FF FFFF 17 UD17 0 Storage compression is off 1 .
TBL Time Base Lower 10-48 PPC405 Core User’s Manual TBL TBR 0x10C (Read-only); SPR 0x11C (Privileged write-only) See “Time Base” on page 6-1. Figure 10-31. Time Base Lower (TBL) 0:31 Time Base Lower Current count; low-order 32 bits of time base.
TBU Time Base Upper Register Summary 10-49 TBU TBR 0x10D (Read-only); SPR 0x11D (Privileged write-only) See “Time Base” on page 6-1. Figure 10-32. Time Base Upper (TBU) 0:31 Time Base Upper Current count, high-order 32 bits of time base.
TCR Timer Control Register 10-50 PPC405 Core User’s Manual TCR SPR 0x3D A See “Timer Control Register (TCR)” on page 6-9. Figure 10-33. Timer Control Register (TCR) 0:1 WP W atchdog P er iod 00 2 17 clocks 01 2 21 clocks 10 2 25 clocks 11 2 29 clocks 2:3 WRC Watchdog Reset Control 00 No W atchdog reset will occur .
TSR Timer Status Register Register Summary 10-51 TSR SPR 0x3D8 Read/Clear See “Timer Status Register (TSR)” on page 6-8. Figure 10-34. Timer Status Register (TSR) 0 ENW Enable Ne xt W atchdog 0 Action on next w atchdog e v ent is to set TSR[ENW] = 1.
USPRG0 User Special Purpose Register General 0 10-52 PPC405 Core User’s Manual USPRG0 SPR 0x100 (User R/W) See “Special Pur pose Register General (SPRG0–SPRG7)” on page 2-9. Figure 10-35. User SPR General 0 (USPRG0) 0:31 General data Software v alue; no hardware usage .
XER Fixed Point Exception Register Register Summary 10-53 XER SPR 0x001 See “Fix ed P oint Exception Register (XER)” on page 2-7. Figure 10-36. Fixed P oint Exception Register (XER) 0 SO Summary Overflow 0 No ov erflow has occurred. 1 Overflo w has occurred.
ZPR Zone Protection Register 10-54 PPC405 Core User’s Manual ZPR SPR 0x3B0 See “Zone Protection” on page 7-14. Figure 10-37. Zone Protection Register (ZPR) 0:1 Z0 TLB page access control for all pages in this zone .
Instruction Summary A-1 Appendix A. Instruction Summary This appendix contains PPC405 instructions summar ized alphabetically and b y opcode. “Instruction Set and Extended Mnemonics – Alphabetical” lists all PPC405 mnemonics, including e xtended mnemonics, alphabetically .
A-2 PPC405 Core User’s Manual addc R T , RA, RB Add (RA) to (RB). Place result in R T . Place carr y-out in XER[CA]. 9-7 addc. CR[CR0] addco XER[SO , O V] addco. CR[CR0] XER[SO , O V] adde R T , RA, RB Add XER[CA], (RA), (RB). Place result in R T . Place carr y-out in XER[CA].
Instruction Summary A-3 b target Branch unconditional relativ e . LI ← (target – CIA) 6:29 NIA ← CIA + EXTS(LI || 2 0) 9-19 ba Branch unconditional absolute. LI ← target 6:29 NIA ← EXTS(LI || 2 0) bl Branch unconditional relativ e. LI ← (target – CIA) 6:29 NIA ← CIA + EXTS(LI || 2 0) (LR) ← C I A+4 .
A-4 PPC405 Core User’s Manual bdnzlr Decrement CTR. Branch if CTR ≠ 0 to address in LR. Extended mnemonic f or bclr 16,0 9-30 bdnzlrl Extended mnemonic f or bclrl 16,0 (LR) ← C I A+4 . bdnzf cr_bit, target Decrement CTR. Branch if CTR ≠ 0 AND CR cr_bit =0 .
Instruction Summary A-5 bdzlr Decrement CTR. Branch if CTR = 0 to address in LR. Extended mnemonic f or bclr 18,0 9-30 bdzlrl Extended mnemonic f or bclrl 18,0 (LR) ← C I A+4 .
A-6 PPC405 Core User’s Manual beqctr [cr_field] Branch if equal to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 12,4 ∗ cr_field+2 9-26 beqctrl Extended mnemonic f or bcctrl 12,4 ∗ cr_field+2 (LR) ← C I A+4 .
Instruction Summary A-7 bgelr [cr_field] Branch if greater than or equal to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 4,4 ∗ cr_field+0 9-30 bgelrl Extended mnemonic f or bclrl 4,4 ∗ cr_field+0 (LR) ← C I A+4 .
A-8 PPC405 Core User’s Manual blelr [cr_field] Branch if less than or equal to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 4,4 ∗ cr_field+1 9-30 blelrl Extended mnemonic f or bclrl 4,4 ∗ cr_field+1 (LR) ← C I A+4 .
Instruction Summary A-9 bnectr [cr_field] Branch if not equal to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+2 9-26 bnectrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+2 (LR) ← C I A+4 . bnelr [cr_field] Branch if not equal to address in LR.
A-10 PPC405 Core User’s Manual bnlctr [cr_field] Branch if not less than to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+0 9-26 bnlctrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+0 (LR) ← C I A+4 .
Instruction Summary A-11 bnuctr [cr_field] Branch if not unordered to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+3 9-26 bnuctrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+3 (LR) ← C I A+4 . bnulr [cr_field] Branch if not unordered to address in LR.
A-12 PPC405 Core User’s Manual btlr cr_bit Branch if CR cr_bit =1 , to address in LR. Extended mnemonic f or bclr 12,cr_bit 9-30 btlrl Extended mnemonic f or bclrl 12,cr_bit (LR) ← C I A+4 . bun [cr_field], target Branch if unordered. Use CR0 if cr_field is omitted.
Instruction Summary A-13 clrrwi RA, RS , n Clear r ight immediate. (n < 32) (RA) 32 − n:31 ← n 0 Extended mnemonic f or rlwinm RA,RS,0,0,31 − n 9-147 clrrwi. Extended mnemonic f or rlwinm. RA,RS,0,0,31 − n CR[CR0] cmp BF , 0, RA, RB Compare (RA) to (RB), signed.
A-14 PPC405 Core User’s Manual crnor BT , BA, BB NOR bit (CR BA ) with (CR BB ). Place result in CR BT . 9-43 crnot bx, by Condition register not. Extended mnemonic f or crnor bx,by ,by 9-43 cror BT , BA, BB OR bit (CR BA ) with (CR BB ). Place result in CR BT .
Instruction Summary A-15 eieio Storage synchronization. All loads and stores that precede the eieio instruction complete bef ore any loads and stores that f ollow the instruction access main storage. Implemented as sync , which is more restrictive . 9-61 eqv RA, RS, RB Equivalence of (RS) with (RB).
A-16 PPC405 Core User’s Manual isync Synchronize e x ecution conte xt b y flushing the pref etch queue. 9-70 la R T , D(RA) Load address. (RA ≠ 0) D is an offset from a base address that is assumed to be (RA).
Instruction Summary A-17 lhzu R T , D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad left with zeroes , (R T) ← 16 0 || MS(EA,2). Update the base address, (RA) ← EA. 9-81 lhzux R T , RA, RB Load halfword from EA = (RA|0) + (RB) and pad left with zeroes , (R T) ← 16 0 || MS(EA,2).
A-18 PPC405 Core User’s Manual lwz RT , D(RA) Load word from EA = (RA|0) + EXTS(D) and place in RT , (R T) ← MS(EA,4). 9-91 lwzu R T , D(RA) Load word from EA = (RA|0) + EXTS(D) and place in RT , (R T) ← MS(EA,4). Update the base address, (RA) ← EA.
Instruction Summary A-19 machhwsu R T , RA, RB prod 0:31 ← (RA) 0:15 x (RB) 0:15 unsigned temp 0:32 ← prod 0:31 + (R T) (R T) ← (temp 1:32 ∨ 32 temp 0 ) 9-101 machhwsu.
A-20 PPC405 Core User’s Manual mfccr0 mfctr mfdac1 mfdac2 mfdear mfdbcr0 mfdbcr1 mfdbsr mfdccr mfdcwr mfdvc1 mfdvc2 mfesr mfevpr mfiac1 mfiac2 mfiac3 mfiac4 mficcr mficdbdr mflr mfpid mfpit m.
Instruction Summary A-21 mftbu R T Mov e the contents of TBU into R T , (R T) ← (TBU) Extended mnemonic f or mftb RT ,TBU 9-114 mr R T , RS Move register . (R T) ← (RS) Extended mnemonic f or or RT ,RS,RS 9-140 mr . Extended mnemonic f or or . RT ,RS,RS CR[CR0] mtcr RS Move to Condition Register .
A-22 PPC405 Core User’s Manual mtccr0 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbsr mtdccr mtdear mtdcwr mtdvc1 mtdvc2 mtesr mtevpr mtiac1 mtiac2 mtiac3 mtiac4 mticcr mticdbdr mtlr mtpid mtpit mtpvr mt.
Instruction Summary A-23 mulhhw R T , RA, RB (R T) 0:31 ← (RA) 0:15 x (RB) 0:15 signed 9-123 mulhhw . CR[CR0] mulhhwu R T , RA, RB (R T) 0:31 ← (RA) 0:15 x (RB) 0:15 unsigned 9-124 mulhhwu. CR[CR0] mullhw R T , RA, RB (R T) 0:31 ← (RA) 16:31 x (RB) 16:31 signed 9-125 mullhw .
A-24 PPC405 Core User’s Manual nmachhw R T , RA, RB nprod 0:31 ← –((RA) 0:15 x (RB) 0:15 ) signed temp 0:32 ← nprod 0:31 + (R T) (R T) ← temp 1:32 9-135 nmachhw .
Instruction Summary A-25 rfi Return from interr upt. (PC) ← (SRR0). (MSR) ← (SRR1). 9-145 rlwimi RA, RS , SH, MB, ME Rotate left word immediate, then insert according to mask. r ← RO TL((RS), SH) m ← MASK(MB, ME) (RA) ← (r ∧ m) ∨ ((RA) ∧¬ m) 9-146 rlwimi.
A-26 PPC405 Core User’s Manual slwi RA, RS , n Shift left immediate. (n < 32) (RA) 0:31 − n ← (RS) n:31 (RA) 32 − n:31 ← n 0 Extended mnemonic f or rlwinm RA,RS,n,0,31 − n 9-147 slwi. Extended mnemonic f or rlwinm. RA,RS,n,0,31 − n CR[CR0] sraw RA, RS , RB Shift right algebraic (RS) by (RB) 27:31 .
Instruction Summary A-27 sthbrx RS, RA, RB Store halfword (RS) 16:31 byte-re v ersed in memory at EA = (RA|0) + (RB). MS(EA, 2) ← (RS) 24:31 || (RS) 16:23 9-161 sthu RS, D(RA) Store halfword (RS) 16:31 in memor y at EA = (RA|0) + EXTS(D). Update the base address, (RA) ← EA.
A-28 PPC405 Core User’s Manual stwux RS, RA, RB Store word (RS) in memor y at EA = (RA|0) + (RB). Update the base address, (RA) ← EA. 9-174 stwx RS, RA, RB Store word (RS) in memor y at EA = (RA|0) + (RB). 9-175 sub R T , RA, RB Subtract (RB) from (RA).
Instruction Summary A-29 subfme R T , RA, RB Subtract (RA) from (–1) with carr y-in. (R T) ←¬ (RA) + (–1) + XER[CA]. Place carr y-out in XER[CA]. 9-180 subfme. CR[CR0] subfmeo XER[SO , O V] subfmeo. CR[CR0] XER[SO , O V] subfze RT , RA, RB Subtract (RA) from zero with carry-in.
A-30 PPC405 Core User’s Manual tlbrehi R T , RA Load TLBHI of the selected TLB entr y into R T . Load PID with the contents of the TID field of the selected TLB entr y . (R T) ← TLBHI[(RA)] (PID) ← TLB[(RA)] TID Extended mnemonic f or tlbre RT ,RA,0 9-184 tlbrelo R T , RA Load TLBLO of the selected TLB entr y into R T .
Instruction Summary A-31 trap T rap unconditionally . Extended mnemonic f or tw 31,0,0 9-190 tweq RA, RB T rap if (RA) equal to (RB). Extended mnemonic f or tw 4,RA,RB twge T rap if (RA) greater than or equal to (RB). Extended mnemonic f or tw 12,RA,RB twgt T rap if (RA) greater than (RB).
A-32 PPC405 Core User’s Manual tweqi RA, IM T rap if (RA) equal to EXTS(IM). Extended mnemonic f or twi 4,RA,IM 9-193 twgei T rap if (RA) greater than or equal to EXTS(IM). Extended mnemonic f or twi 12,RA,IM twgti T rap if (RA) greater than EXTS(IM).
Instruction Summary A-33 A.2 Instructions Sor ted by Opcode All instructions are four b ytes long and word aligned. All instructions hav e a primar y opcode field (shown as field OPCD in Figure A-1 through Figure A-9, beginning on page A-44) in bits 0:5.
A-34 PPC405 Core User’s Manual 4 76 (588) XO machhwsu RT , RA, RB 9-101 machhwsu. machhwsuo machhwsuo. 4 108 (620) XO machhws R T , RA, RB 9-100 machhws. machhwso machhwso. 4 110 (622) XO nmachhws R T , RA, RB 9-136 nmachhws. nmachhwso nmachhwso. 4 136 X mulchwu R T , RA, RB 9-122 mulc hwu.
Instruction Summary A-35 4 392 X mullhwu R T , RA, RB 9-128 mullhwu. 4 396 (908) XO maclhwu R T , RA, RB 9-106 maclhwu. maclhwuo maclhwuo. 4 424 X mullhw R T , RA, RB 9-127 mullhw . 4 428 (940) XO maclhw R T , RA, RB 9-103 maclhw . maclhw o maclhw o. 4 430 (942) XO nmaclhw R T , RA, RB 9-137 nmaclhw .
A-36 PPC405 Core User’s Manual 18 I b target 9-19 ba bl bla 19 0 XL mcrf BF , BF A 9-107 19 16 XL bc lr BO , BI 9-30 bclrl 19 33 XL crnor BT , BA, BB 9-43 19 50 XL rfi 9-145 19 51 XL rfci 9-144 19 .
Instruction Summary A-37 31 10 (522) XO addc R T , RA, RB 9-7 addc. addco addco. 31 11 XO mulhwu R T , RA, RB 9-126 mulhwu. 31 19 X mfcr R T 9-109 31 20 X lwarx R T , RA, RB 9-89 31 23 X lwzx R T , RA, RB 9-94 31 24 X slw RA, RS , RB 9-169 slw . 31 26 X cntlzw RA, RS 9-38 cntlzw .
A-38 PPC405 Core User’s Manual 31 138 (650) XO adde R T , RA, RB 9-8 adde. addeo addeo. 31 144 XFX mtcrf FXM, RS 9-116 31 146 X mtmsr RS 9-118 31 150 X stwcx. RS, RA, RB 9-171 31 151 X stwx RS, RA, RB 9-175 31 163 X wr teei E 9-197 31 183 X stwux RS, RA, RB 9-174 31 200 (712) XO subfze RT , RA, RB 9-181 subfze .
Instruction Summary A-39 31 284 X eqv RA, RS, RB 9-62 eqv . 31 311 X lhzux RT , RA, RB 9-82 31 316 X xor RA, RS, RB 9-198 xor . 31 323 XFX mfdcr R T , DCRN 9-110 31 339 XFX mfspr R T , SPRN 9-112 31 3.
A-40 PPC405 Core User’s Manual 31 662 X stwbrx RS, RA, RB 9-170 31 725 X stswi RS, RA, NB 9-166 31 758 X dcba RA, RB 9-47 31 790 X lhbrx RT , RA, RB 9-79 31 792 X sraw RA, RS, RB 9-153 sraw . 31 824 X srawi RA, RS, SH 9-154 srawi. 31 854 X eieio 9-61 31 914 X tlbsx RT , RA, RB 9-186 tlbsx.
Instruction Summary A-41 A.3 Instruction Formats Instructions are four b ytes long. Instruction addresses are alwa ys word-aligned. Instruction bits 0 through 5 alwa ys contain the primar y opcode. Many instructions hav e an e xtended opcode in another field.
A-42 PPC405 Core User’s Manual BO (6:10) Specifies options f or conditional branch instructions. See “BO Field on Conditional Branches” on page 2-25. BT (6:10) Specifies a bit in the CR used as a target as the result of a CR-Logical instruction.
Instruction Summary A-43 XO (22:30) Extended opcode for instructions with an OE field. Extended opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions. The XO field name does not appear in instruction descr iptions.
A-44 PPC405 Core User’s Manual A.3.2.1 I-Form A.3.2.2 B-Form A.3.2.3 SC-Form A.3.2.4 D-Form OPCD LI 06 31 Figure A-1. I Instruction Format OPCD BO BI BD AA LK 0 6 11 16 30 31 Figure A-2. B Instruction Format OPCD /// /// /// 1 / 0 6 11 16 30 31 Figure A-3.
Instruction Summary A-45 A.3.2.5 X-Form A.3.2.6 XL-Form OPCD RT RA RB XO Rc OPCD R T R A R B X O / OPCD R T R A N B X O / OPCD R T R A W S XO / OPCD RT /// RB XO / OPCD R T / / / / / / X O / OPCD R S .
A-46 PPC405 Core User’s Manual A.3.2.7 XFX-Form A.3.2.8 X0-Form A.3.2.9 M-Form OPCD RT SPRF XO / OPCD R T DCRF XO / OPCD R T / F X M / X O / OPCD R S SPRF XO / OPCD R S DCRF XO / 0 6 11 16 21 31 Figure A-7. XFX Instruction Format OPCD RT RA RB OE XO Rc OPCD R T R A R B O E X O R c OPCD R T R A / / / / X O R c 0 6 11 16 21 22 31 Figure A-8.
Instructions by Category B-1 Appendix B. Instructions by Category Chapter 9, “Instruction Set, ” contains detailed descriptions of the instr uctions, their operands , and notation. T able B-1 summarizes the instruction categor ies in the PPC405 instr uction set.
B-2 PPC405 Core User’s Manual macchw R T , RA, RB prod 0:31 ← (RA) 16:31 x (RB) 0:15 signed temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 9-95 macchw .
Instructions by Category B-3 machhwu R T , RA, RB prod 0:31 ← (RA) 0:15 x (RB) 0:15 unsigned temp 0:32 ← prod 0:31 + (R T) (R T) ← temp 1:32 9-102 machhwu.
B-4 PPC405 Core User’s Manual mullhwu R T , RA, RB (R T) 16:31 ← (RA) 0:15 x (RB) 16:31 unsigned 9-128 mullhwu. CR[CR0] nmacchw R T , RA, RB nprod 0:31 ← –((RA) 16:31 x (RB) 0:15 ) signed temp 0:32 ← nprod 0:31 + (R T) (R T) ← temp 1:32 9-133 nmacchw .
Instructions by Category B-5 B.2 Instructions in the IBM P o werPC Embedded En vironment T o meet the functional requirements of processors for embedded systems and real-time applications , the IBM P o werPC Embedded En vironment defines instructions that are not par t of the P owerPC Architecture.
B-6 PPC405 Core User’s Manual mftb R T Move the contents of a Time Base Register (TBR) into R T , TBRN ← TBRF 5:9 || TBRF 0:4 (R T) ← (TBR(TBRN)) 9-114 mtdcr DCRN, RS Move to DCR from RS , (DCR(DCRN)) ← (RS). 9-117 mtmsr RS Move to MSR from RS , (MSR) ← (RS).
Instructions by Category B-7 B.3 Privileged Instructions T able B-4 lists instructions that are under control of the MSR[PR] bit. These instr uctions are not allow ed to be e x ecuted when MSR[PR] = 1: tlbsx R T ,RA,RB Search the TLB arra y f or a v alid entr y which translates the EA EA = (RA|0) + (RB).
B-8 PPC405 Core User’s Manual dcread R T , RA, RB Read either tag or data inf or mation from the data cache congruence class associated with the EA (RA|0) + (RB).
Instructions by Category B-9 B.4 Assembler Extended Mnemonics In the appendix “Assembler Extended Mnemonics” of the P owerPC Architecture , it is required that a P o werPC assemb ler suppor t at least a minimal set of extended mnemonics .
B-10 PPC405 Core User’s Manual As specific e xamples, bc also could be coded as bc+ or bc − , and bne also could be coded bne+ or bne − . These alter nate codings set BO 4 = 1 only if the requested prediction diff ers from the standard prediction (see “Branch Prediction” on page 2-26).
Instructions by Category B-11 bdnzt cr_bit, target Decrement CTR. Branch if CTR ≠ 0 AND CR cr_bit =1 . Extended mnemonic f or bc 8,cr_bit,target 9-20 bdnzta Extended mnemonic f or bca 8,cr_bit,target bdnztl Extended mnemonic f or bcl 8,cr_bit,tar get (LR) ← CIA + 4.
B-12 PPC405 Core User’s Manual bdzflr cr_bit Decrement CTR. Branch, if CTR = 0 AND CR cr_bit = 0 to address in LR. Extended mnemonic f or bclr 2,cr_bit 9-30 bdzflrl Extended mnemonic f or bclrl 2,cr_bit (LR) ← CIA + 4. bdzt cr_bit, target Decrement CTR.
Instructions by Category B-13 beqlr [cr_field] Branch, if equal, to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 12,4 ∗ cr_field+2 9-30 beqlrl Extended mnemonic f or bclrl 12,4 ∗ cr_field+2 (LR) ← CIA + 4. bf cr_bit, target Branch if CR cr_bit =0 .
B-14 PPC405 Core User’s Manual bgelr [cr_field] Branch, if greater than or equal, to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 4,4 ∗ cr_field+0 9-30 bgelrl Extended mnemonic f or bclrl 4,4 ∗ cr_field+0 (LR) ← CIA + 4.
Instructions by Category B-15 blectr [cr_field] Branch, if less than or equal, to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+1 9-26 blectrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+1 (LR) ← CIA + 4.
B-16 PPC405 Core User’s Manual bne [cr_field,] target Branch if not equal. Use CR0 if cr_field is omitted. Extended mnemonic f or bc 4,4 ∗ cr_field+2,target 9-20 bnea Extended mnemonic f or bca 4,4 ∗ cr_field+2,target bnel Extended mnemonic f or bcl 4,4 ∗ cr_field+2,tar get (LR) ← CIA + 4.
Instructions by Category B-17 bnglr [cr_field] Branch, if not greater than, to address in LR. Use CR0 if cr_field is omitted. Extended mnemonic f or bclr 4,4 ∗ cr_field+1 9-30 bnglrl Extended mnemonic f or bclrl 4,4 ∗ cr_field+1 (LR) ← CIA + 4.
B-18 PPC405 Core User’s Manual bnsctr [cr_field] Branch, if not summar y ov erflow , to address in CTR. Use CR0 if cr_field is omitted. Extended mnemonic f or bcctr 4,4 ∗ cr_field+3 9-26 bnsctrl Extended mnemonic f or bcctrl 4,4 ∗ cr_field+3 (LR) ← CIA + 4.
Instructions by Category B-19 bso [cr_field,] target Branch if summary overflo w . Use CR0 if cr_field is omitted. Extended mnemonic f or bc 12,4 ∗ cr_field+3,target 9-20 bsoa Extended mnemonic f or bca 12,4 ∗ cr_field+3,target bsol Extended mnemonic f or bcl 12,4 ∗ cr_field+3,tar get (LR) ← CIA + 4.
B-20 PPC405 Core User’s Manual bun [cr_field,] target Branch if unordered. Use CR0 if cr_field is omitted. Extended mnemonic f or bc 12,4 ∗ cr_field+3,target 9-20 buna Extended mnemonic f or bca 12,4 ∗ cr_field+3,target bunl Extended mnemonic f or bcl 12,4 ∗ cr_field+3,tar get (LR) ← CIA + 4.
Instructions by Category B-21 cmplw [BF ,] RA, RB Compare Logical W ord. Use CR0 if BF is omitted. Extended mnemonic f or cmpl BF ,0,RA,RB 9-36 cmplwi [BF ,] RA, IM Compare Logical Word Immediate . Use CR0 if BF is omitted. Extended mnemonic f or cmpli BF ,0,RA,IM 9-37 cmpw [BF ,] RA, RB Compare Word.
B-22 PPC405 Core User’s Manual inslwi RA, RS , n, b Inser t from left immediate. (n > 0) (RA) b:b+n − 1 ← (RS) 0:n − 1 Extended mnemonic f or rlwimi RA,RS,32 − b,b,b+n − 1 9-146 inslwi. Extended mnemonic f or rlwimi. RA,RS,32 − b,b,b+n − 1 CR[CR0] insrwi RA, RS, n, b Inser t from r ight immediate.
Instructions by Category B-23 mfccr0 mfctr mfdac1 mfdac2 mfdear mfdbcr0 mfdbcr1 mfdbsr mfdccr mfdcwr mfdvc1 mfdvc2 mfesr mfevpr mfiac1 mfiac2 mfiac3 mfiac4 mficcr mficdbdr mflr mfpid mfpit mfpv.
B-24 PPC405 Core User’s Manual mftbu R T Mov e the contents of TBU into R T , (R T) ← (TBU) Extended mnemonic f or mftb RT ,TBU 9-114 mr R T , RS Move register . (R T) ← (RS) Extended mnemonic f or or RT ,RS,RS 9-140 mr . Extended mnemonic f or or .
Instructions by Category B-25 mtccr0 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbsr mtdccr mtdear mtdcwr mtdvc1 mtdvc2 mtesr mtevpr mtiac1 mtiac2 mtiac3 mtiac4 mticcr mticdbdr mtlr mtpid mtpit mtpvr mtsgr.
B-26 PPC405 Core User’s Manual not RA, RS Complement register . (RA) ←¬ (RS) Extended mnemonic f or nor RA,RS,RS 9-139 not. Extended mnemonic f or nor . RA,RS,RS CR[CR0] rotl w RA, RS, RB Rotate left. (RA) ← RO TL((RS), (RB) 27:31 ) Extended mnemonic f or rlwnm RA,RS,RB,0,31 9-150 rotl w .
Instructions by Category B-27 sub R T , RA, RB Subtract (RB) from (RA). (R T) ←¬ (RB) + (RA) + 1. Extended mnemonic f or subf RT ,RB,RA 9-176 sub. Extended mnemonic f or subf. R T ,RB,RA CR[CR0] subo Extended mnemonic f or subfo R T ,RB,RA XER[SO , O V] subo.
B-28 PPC405 Core User’s Manual tweqi RA, IM T rap if (RA) equal to EXTS(IM). Extended mnemonic f or twi 4,RA,IM 9-190 twgei T rap if (RA) greater than or equal to EXTS(IM). Extended mnemonic f or twi 12,RA,IM twgti T rap if (RA) greater than EXTS(IM).
Instructions by Category B-29 B.5 Storage Reference Instructions The PPC405 uses load and store instructions to transf er data between memor y and the general pur pose registers.
B-30 PPC405 Core User’s Manual lhzu R T , D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad left with zeroes , (R T) ← 16 0 || MS(EA,2). Update the base address, (RA) ← EA. 9-80 lhzux R T , RA, RB Load halfword from EA = (RA|0) + (RB) and pad left with zeroes , (R T) ← 16 0 || MS(EA,2).
Instructions by Category B-31 lwzu R T , D(RA) Load word from EA = (RA|0) + EXTS(D) and place in RT , (R T) ← MS(EA,4). Update the base address, (RA) ← EA. 9-92 lwzux R T , RA, RB Load word from EA = (RA|0) + (RB) and place in RT , (R T) ← MS(EA,4).
B-32 PPC405 Core User’s Manual stswi RS , RA, NB Store consecutiv e bytes in memory star ting at EA=(RA|0). Number of bytes n = 32 if NB = 0, else n =N B . Bytes are unstack ed from CEIL( n /4) consecutive registers star ting with RS. GPR(0) is consecutive to GPR(31).
Instructions by Category B-33 B.6 Arithmetic and Logical Instructions T able B-7 lists the arithmetic and logical instr uctions. Arithmetic operations are perf or med on integer or ordinal operands stored in registers.
B-34 PPC405 Core User’s Manual addme R T , RA Add XER[CA], (RA), (-1). Place result in R T . Place carr y-out in XER[CA]. 9-13 addme. CR[CR0] addmeo XER[SO , O V] addmeo. CR[CR0] XER[SO , O V] addze R T , RA Add XER[CA] to (RA). Place result in R T .
Instructions by Category B-35 extsh RA, RS Extend the sign of halfword (RS) 16:31 . Place the result in RA. 9-64 extsh. CR[CR0] mulhw R T , RA, RB Multiply (RA) and (RB), signed. Place hi-order result in R T . prod 0:63 ← (RA) × (RB) (signed). (R T) ← prod 0:31.
B-36 PPC405 Core User’s Manual subf R T , RA, RB Subtract (RA) from (RB). (R T) ←¬ (RA) + (RB) + 1. 9-176 subf. CR[CR0] subfo XER[SO , OV] subfo. CR[CR0] XER[SO , O V] subfc R T , RA, RB Subtract (RA) from (RB). (R T) ←¬ (RA) + (RB) + 1. Place carr y-out in XER[CA].
Instructions by Category B-37 B.7 Condition Register Logical Instructions CR logical instructions combine the results of sev eral comparisons without incurring the ov erhead of conditional branching. These instructions can significantly improv e code perf ormance if multiple conditions are tested bef ore making a branch decision.
B-38 PPC405 Core User’s Manual B.8 Branch Instructions The architecture provides conditional and unconditional branches to an y storage location. The conditional branch instructions test condition codes set previously and br anch accordingly .
Instructions by Category B-39 B.9 Comparison Instructions Comparison instr uctions perf or m arithmetic and logical compar isons between two operands and set one of the eight condition code register fields based on the outcome of the comparison. T able B-10 shows the comparison instructions suppor ted by the PPC405 core.
B-40 PPC405 Core User’s Manual B.10 Rotate and Shift Instructions Rotate and shift instructions rotate and shift operands which are stored in the general pur pose registers. Rotate instructions can also mask rotated operands . T able B-11 shows the PPC405 rotate and shift instructions.
Instructions by Category B-41 B.11 Cache Control Instructions Cache control instructions allow the user to indirectly control the contents of the data and instruction caches. The user ma y fill, flush, in v alidate and zero b loc ks (16-byte lines) in the data cache .
B-42 PPC405 Core User’s Manual B.12 Interrupt Control Instructions The interrupt control instr uctions allow the user to mov e data betw een general purpose registers and the machine state register , return from interrupts and enable or disable maskab le e xternal interr upts.
Instructions by Category B-43 tlbre R T , RA,WS If WS = 0: Load TLBHI por tion of the selected TLB entr y into RT . Load the PID register with the contents of the TID field of the selected TLB entr y . (R T) ← TLBHI[(RA)] (PID) ← TLB[(RA)] TID If WS = 1: Load TLBLO por tion of the selected TLB entr y into RT .
B-44 PPC405 Core User’s Manual B.14 Processor Management Instructions The processor management instructions mov e data between GPRs and SPRs and DCRs in the PPC405 core; these instructions also provide traps , system calls and synchronization controls.
Instructions by Category B-45 twi T O , RA, IM T rap e xception is generated if , comparing (RA) with EXTS(IM), any condition specified b y T O is true.
B-46 PPC405 Core User’s Manual.
Code Optimization and Instruction Timings C-1 Appendix C. Code Optimization and Instruction Timings The code optimization guidelines in “Code Optimization Guidelines” and the inf or mation describ.
C-2 PPC405 Core User’s Manual Because this method adds interrupt context s witching time to the e x ecution time of libr ar y routines that would ha v e been called directly by the pref erred method, it is not pref erred. Ho we v er , this method suppor ts code that contains P ow erPC floating-point instructions.
Code Optimization and Instruction Timings C-3 Align branch targets that are unlik ely to be hit by “f all-through” code on cache line boundaries (such as the address of functions such as strcp y ), to minimize the n umber of unused instructions in cache line fills.
C-4 PPC405 Core User’s Manual Instruction timings for br anch instructions follo w: • A branch kno wn not taken (BKNT) e x ecutes in one cloc k cycle. By definition a BKNT does not have address or condition dependencies. • A branch kno wn taken (BKT) b y definition has no condition dependencies, b ut can ha v e address dependencies.
Code Optimization and Instruction Timings C-5 T able C-2 summarizes the multiply and MA C instruction timings. In the tab le, the syntax “[ o ]” indicates that the instruction has an “o” form that updates XER[SO ,O V], and a “non-o” f orm.
C-6 PPC405 Core User’s Manual C.2.5 Scalar Store Instructions Cachable stores that miss in the DCU , and noncachable stores, are queued in the data cache so that the store appears to e x ecute in a single cycle if operand-aligned. Under cer tain conditions, the DCU can pipeline up to three store instructions.
Code Optimization and Instruction Timings C-7 C.2.8 Loads and Store Misses Cachable stores that miss in the DCU , and noncachable stores, are queued internally in the DCU so that the store instruction appears to ex ecute in one cycle . Under cer tain conditions, the DCU can pipeline up to three store instructions.
C-8 PPC405 Core User’s Manual.
Index X-1 Index Index A AA field conditional branches 2-24 unconditional branches 2-24 access protection cache instructions 7-16 string instructions 7-17 virtual mode 7-13 add 9-6 add. 9-6 addc 9-7 addc. 9-7 addco 9-7 addco. 9-7 adde 9-8 adde. 9-8 addeo 9-8 addeo.
X-2 PPC405 Core User’s Manual bfa 9-22 bfctr 9-27 bfctrl 9-27 bfl 9-22 bfla 9-22 bflr 9-32 bflrl 9-32 bge 9-23 bgea 9-23 bgectrl 9-27 bgel 9-23 bgela 9-23 bgelr 9-32 bgelrl 9-32 bgrctr 9-27 bgt 9-23.
Index X-3 bunl 9-25 bunla 9-25 bunlr 9-33 bunlrl 9-33 byte ordering big endian, defined 2-18 little endian defined 2-18 supported 2-19 overview 2-17 byte reversal during load/store access 2-21 byte-re.
X-4 PPC405 Core User’s Manual data TLB. See DTLB data types illustrated 2-16 summarized 1-8 DBCR 8-4 DBCR0 10-11 , 10-13 DBCR0 (Debug Control Register 0) resets 3-1 DBSR 8-7 , 10-15 dcba does not ca.
Index X-5 when controlled by TLB 7-6 engineering note ESR bits 5-13 eqv 9-62 eqv. 9-62 ESR 10-23 ESR (Exception Status Register) usage for program interrupts 5-20 ESR (Exception Syndrome Register) cle.
X-6 PPC405 Core User’s Manual bnea 9-24 bnectrl 9-28 bnel 9-24 bnela 9-24 bnelr 9-32 bnelrl 9-32 bng 9-24 bnga 9-24 bngctr 9-28 bngctrl 9-28 bngl 9-24 bnglr 9-32 bnglrl 9-32 bnl 9-24 bnla 9-24 bnlct.
Index X-7 rotlw 9-150 rotlw. 9-150 rotlwi 9-148 rotlwi. 9-148 rotrwi 9-148 rotrwi. 9-148 slwi 9-148 slwi. 9-148 srwi 9-149 srwi. 9-149 sub 9-176 sub. 9-176 subc 9-177 subc. 9-177 subco 9-177 subco. 9-177 subi 9-9 subic 9-10 subic. 9-11 subis 9-12 subo 9-176 subo.
X-8 PPC405 Core User’s Manual instruction flow, illustrated 4-4 instructions 4-9 synchronization 4-6 synonyms 4-5 imprecise interrupts 5-1 initialization code example 3-5 of processor 3-3 requirements 3-4 sequence 3-4 inslwi 9-146 inslwi. 9-146 insrwi 9-146 insrwi.
Index X-9 maclhw 9-103 maclhws 9-104 , 9-138 maclhwu 9-106 mcrf 9-107 mcrxr 9-108 mfcr 9-109 mfdcr 9-110 mfmsr 9-111 mfspr 9-112 mtcrf 9-116 mtdcr 9-117 mtspr 9-119 mulchw 9-121 mulchwu 9-122 mulhhw 9-123 mulhhwu 9-124 mulhwu 9-126 mulhwu. 9-126 mullhw 9-127 mullhwu 9-128 mulli 9-129 mullw 9-130 mullw.
X-10 PPC405 Core User’s Manual from little endian storage 2-20 instruction fields A-41 instruction formats 9-2 , A-41 diagrams A-43 instruction forms A-41 , A-43 instruction queue illustrated 2-24 r.
Index X-11 ITLB (instruction translation lookaside buffer) accesses 7-7 consistency 7-7 defined 7-6 miss interrupts 5-25 , 7-11 programming note 7-8 L lbz 9-71 lbzu 9-72 lbzx 9-74 lha 9-75 lhau 9-76 lhax 9-78 lhbrx 9-79 lhz 9-80 lhzu 9-81 lhzux 9-82 lhzx 9-83 li 9-9 Link Register.
X-12 PPC405 Core User’s Manual mtspr 9-119 mulchw 9-121 mulchwu 9-122 mulhhw 9-123 mulhhwu 9-124 mulhwu 9-126 mulhwu. 9-126 mullhw 9-127 mullhwu 9-128 mulli 9-129 mullw 9-130 mullw. 9-130 mullwo 9-130 mullwo. 9-130 N nand 9-131 nand. 9-131 neg 9-132 neg.
Index X-13 storage attribute control 7-17 register set summary 1-9 registers categories 2-2 , 10-1 CCR0 10-6 CR 10-1 , 10-8 CTR 10-9 DAC1 8-9 DAC1–DAC2 8-9 , 10-10 DBCR 8-4 DBCR0 10-11 , 10-13 DBSR .
X-14 PPC405 Core User’s Manual listed, with page references 2-6 overview 2-5 privileged and non-privileged 2-5 privileged, instructions for reading 2-32 summary 1-9 sraw 9-153 sraw. 9-153 srawi 9-154 srawi. 9-154 SRR0 10-42 SRR0-1 (Save/Restore Registers 0-1) illustrated 5-9 SRR1 10-43 SRR2 10-44 SRR3 10-45 srw 9-155 srw.
Index X-15 subic. 9-11 subis 9-12 subo 9-176 subo. 9-176 supervisor state. See privileged mode sync 9-182 storage synchronization 2-35 synchronization context 2-33 execution, defined 2-35 ICU 4-6 refe.
X-16 PPC405 Core User’s Manual USPRG0 2-10 , 10-52 UTLB (unified translation lookaside buffer) access control fields 7-5 entry format, illustrated 7-3 EPN field 7-3 EX field 7-5 field categories 7-3.
Preliminary.
© Inter national Business Machines Cor poration 1996, 2001 Printed in the United States of America 12/3/01 All Rights Reserved The information contained in this document is subject to change without notice.
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