Instruction/ maintenance manual of the product DC71XX HP (Hewlett-Packard)
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T ec hnical Ref erence Guide HP Co mpaq dc71xx and dx61xx Ser ies Bu siness De sktop C ompu ter s Doc ument P ar t Number: 3 618 3 4 -00 2 Januar y 2005 This document provides information on the design, archite cture, function, and capabilities of the HP Compaq dc 71xx and dx61xx Series Business Desktop Computers.
© Copyright 2005 He wlett-Packard De velo pment Company , L.P . The information contained herein is subject to change without notice. Microsoft, MS-DOS, W indows, and W indo ws NT are trademar ks of Microsoft Corporation in the U.S. and other countries.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 iii Cont ents 1 Introduction 1.1 About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1.1 Online Viewing . . . .
iv 3 6183 4 -00 2 T echni cal Re fer ence Guide Conte nt s 3.2.2 Processor Upgrading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 3.3 Memory Subsystem . . . . . . . . . . . . . . . . .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 v Con tents 5.5.4 Parallel Interface Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 5 5.5.5 Parallel Interface Connector . . . . . . . . . . . . . .
v i 3 6183 4 -00 2 T echni cal Re fer ence Guide Conte nt s 8 BIOS ROM 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 8.2 ROM Flashing . . . . . .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 1-1 1 Introduc tion 1.1 A b o u t t h i s G u i d e This guide pro vides technical information about HP Compaq dx71xx and dc61 xx series personal computers that feature the Intel Pentium 4 proces sor and the Intel 915G ch ipset.
1-2 3 618 34-002 T echni cal Ref erence Gui de Intr oduction 1 .3 Model Numberin g C onv en tion The model numbering con v ention or HP systems is as follo ws:.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 1-3 Intr oducti on 1 .4 Serial Number The unit's serial number is located on a sticker pl aced on the e xterior cabinet. The serial number is also written into firmwa re and may be read with HP Diagnostics or Insight Manager utilities.
1-4 3 618 34-002 T echni cal Ref erence Gui de Intr oduction 1 .6 Comm on Ac ron y ms and Ab bre viations T able 1-1 lists the acronyms and ab brev iations used in this guide.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 1-5 Intr oducti on Ch Chan nel, chapter cm centimeter CMC cache/me mory controller CMOS complimentary metal-ox ide semi conductor (conf igur ation memory) Cntlr contr oller Cntrl con trol codec 1. coder/deco der 2 .
1-6 3 618 34-002 T echni cal Ref erence Gui de Intr oduction E S CD Extended S y stem Conf igur ation Data (f ormat) EV Env ir onmental V ariable (data) ExCA Exc hangeable Car d Ar chitec ture FIFO fi.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 1-7 Intr oducti on Kb/KB kilobits/kilobytes (x 102 4 bits/ x 10 2 4 bytes) Kb/s kilobits per second kg ki l o g ra m KHz kilohe rtz kV kilov olt lb pound L.
1-8 3 618 34-002 T echni cal Ref erence Gui de Intr oduction PC P erso n al c o mp u te r PCA Print ed circ ui t asse mbly PCI peripher al component inte rconnect PCI-E PCI Expr ess PCM pulse code mod.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 1-9 Intr oducti on SIMD Single instruc tion multiple dat a SIMM single in -line memory module SMAR T Self Monitor Anal ysis R eport T echn ology SMI s yste.
1-10 3 6183 4 -00 2 T echni cal Ref erence Gui de Intr oduction VDC V olts dir ect c urre nt VE S A Vi deo Electr onic St andards As soc iation V G A video gr aphics adapter VLSI v ery large scale int.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-1 2 Sys t e m O ve r v i ew 2. 1 Introduc tion The HP Compaq dc71x x and dx61xx Series Business Desktop Computers (F igure 2-1) deli ver an outstanding combination of ma nageability , serviceab ility , and compatibility for enterprise en vironments.
2-2 3 618 34-002 T echni cal Ref erence Gui de S ystem Ov ervie w 2.2 Feat ures An d O pti ons This section describes the standard features. 2.2. 1 Stan d ard F ea tures The follo wing standard featur.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-3 S ystem Ov ervie w T able 2-1 shows the dif ferences in features between the dif ferent PC series based on form factor: NO TE: [1] Supported on sy stem board . Requires opti onal cable/brack et assembly .
2-4 3 618 34-002 T echni cal Ref erence Gui de S ystem Ov ervie w 2.3 Mechanical Design This guide cov ers six form factors: ■ Ultra Slim Desktop (USDT)—V ery slim design that can be used in a tradition desktop (horizontal) orientation or as a small tower mounted in the supplied tower stand.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-5 S ystem Ov ervie w 2.3. 1 C ab ine t Lay outs Fr ont Vie ws Figure 2-2 shows the front panel compone nts of the Ultra Slim Desktop (USDT) format factor .
2-6 3 618 34-002 T echni cal Ref erence Gui de S ystem Ov ervie w Figure 2-3 shows the front panel compo n ents of the Small Form F actor (SFF). F igur e 2 -3 .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-7 S ystem Ov ervie w Figure 2-4 shows the front panel compone nts of the Slim T o wer (ST) form factor .
2-8 3 618 34-002 T echni cal Ref erence Gui de S ystem Ov ervie w Figure 2-5 shows the front panel components of the microtower (uT) form f actor . F igur e 2 -5 .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-9 S ystem Ov ervie w Figure 2-6 shows the front panel compone nts of the Con vertable Minito wer (CMT) form f actor .
2-10 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Rear Vi ew s Figure 2-7 sho ws the rear view of the USDT form factor . F igur e 2 -7 .
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-11 S ystem Ov ervie w Figure 2-8 sho ws the rear views of the SF F form factor . T wo configurations are a v ailable: ■ W ithout cardcage - Accepts two half-height PCI 2.3 cards, two half-height PCI Express cards ■ W ith card cage - Accep ts two full-height PCI 2.
2-12 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Figure 2-9 shows the rear vie ws of the ST form factor . T wo conf igurations are av ailable: ■ W ithout cardcage - Accepts two half-height PCI 2.3 cards, two half-height PCI Express cards ■ W ith card cage - Accep ts two full-height PCI 2.
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-13 S ystem Ov ervie w Figure 2-10 sho ws the rear view of the MT form factor . NO TE: [1] S witch not pr esent on SK Us that featur e auto -ranging po wer supply .
2-14 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Figure 2-11 sho ws the rear view of the CMT form factor . F igur e 2 -11. HP Compaq dc710 0 CMT , R ear V ie w Item Descripti on It.
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-15 S ystem Ov ervie w 2.3.2 Cha s sis La y outs This section describes the internal layouts of th e chassis. For detailed information on servicing the chassis refer to the multimedia training and/ or the maintenance and service guide for these systems.
2-16 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Small Fo rm Factor / Slim T ow er Chassis The chassis layouts for the Small Fo rm Factor (SFF) used for the HP Compaq dc7100 models and the Slim T ower (ST) used for the HP Co mapq dx6100 models are sho wn in Figure 2-13 .
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-17 S ystem Ov ervie w Mic roto wer Cha ssis Figure 2-14 sho ws the layout for the Microtower (MT) chassis used for the HP Comp aq dx6100 models. Features include: ■ Externally accessible driv e bay assembly .
2-18 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Conv ertibl e Minitow er Figure 2-15 sho ws the layout for the Con vertib le Minito wer (CMT) chassis in the minito wer confi guration used for HP Compaq dc7100 models.
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-19 S ystem Ov ervie w 2.3. 3 Board La y outs Figures 2-16 through 2 -18 show th e system and expansio n boards for these systems.
2-20 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w NO TE: See SFF and ST r ear chassis illustr ations for externally acces sible I/O connectors.
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-21 S ystem Ov ervie w NO TE S: See MT and CMT rear c hassis illustrations f or externall y accessible I/O conn ectors. [1] Applicable to CMT chas sis only . [2] Not inc luded on MT s yste m boards . F igur e 2 -18.
2-2 2 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w 2.4 Sy ste m Arc hit ec ture The system s cov ered in this guide fe ature an ar chitecture based on the Intel Pentium 4 processor and the Intel 915G ch ipset (Figure 2-11).
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-2 3 S ystem Ov ervie w F igur e 2 -19 Sy st em Ar chit ectur e , Bloc k diagr am P arallel I/F [ 1] Pe n t i u m 4 Processor 915G/GV Chipset 915 [2] 82801 GMCH SDRAM Cntlr PCI Exp . PEG I/F [1] PCI Express ICH6 SA T A I/F USB I/F Ch A DD R/DDR2 SDRAM Ch B DDR/DDR2 SDRAM LPC47B397 I/O Cntlr .
2-2 4 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w 2.4. 1 Intel P e ntium 4 Processor The models cov ered in this guide feature the Intel Pentium 4 processor wit h Hyper-Threading technology .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-2 5 S ystem Ov ervie w 2.4.2 Chips et The chipset consists of a Graphics Memory Controller Hub (G MCH), an enhanced I/O controller hub (ICH), and a f irmware hub (FWH). T able 2- 3 compares the functio ns p rov i de d by t he chipsets.
2-2 6 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w 2.4.3 Suppor t Components Input/output functions not pro vided by the chip set are handled by other support components. Some of these components also provide “house k eeping” and variou s other functions as well.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-2 7 S ystem Ov ervie w 2.4.5 Ma ss S torag e All models support at least two mass storage de vices, with one being e xternally accessible for remo vabl e media. These systems provide one, tw o, or four SA T A interfaces and one P A T A interface.
2-2 8 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w 2.4.9 Gra phi cs Su bsy stem These systems use the 82915G o r 82915GV GMCH component that integrates an Intel graphics controller that can driv e an ex ternal VGA monitor . The integr ated graphics controller (IGC) features a 333-MHz core processor and a 400-MHz RAMD A C.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-2 9 S ystem Ov ervie w 2.5 Spec ifi ca tions This section includes the en vironmental, electrica l, and physical specif ic ations f or the systems cov ered in this guide. Where prov ided, metric statistics are giv en in parenthesis.
2-30 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w NO TE S: [1] S yst em we ight may v ary depending on installed dri ves/per ipherals . [2] Witho ut MultiBay de vi ce installed. [3] Minito wer conf igur ation . F or desktop confi guratio n, s wap Hei ght and Width dimensi ons.
T ec hnical Ref ere nce Guide 3 6183 4 -002 2-31 S ystem Ov ervie w T able 2-9 Diskette Driv e Spec ifi cations P aramet er Mea suremen t Media T ype 3 .
2-3 2 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w Ta b l e 2 -1 0 Optical Drive Specifi cations P arameter 48x CD-R OM 48/24/2 8x CD-R W Driv e Interf ace T ype IDE IDE Media T ype.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 2-3 3 S ystem Ov ervie w Ta b l e 2 -1 1 Hard Drive Specifi cations P ar amet er 40 GB 8 0 GB 1 6 0 GB D riv e S ize 3.
2-34 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Ov ervie w.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 3-1 3 Pr ocessor/Memory Subsy stem 3. 1 Introduction This chapter describes the pr ocessor/memory subsystem.
3-2 3 618 34-002 T echni cal Ref erence Gui de Processor /M emor y Subsystem 3.2 P entium 4 Proce ssor These systems each feature an Intel Pentium 4 processor in a FC-LGA775 package m ounted with a passiv e heat sink in a zero-insertion force sock et.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 3-3 Processor /Me mor y S ubsystem Figure 3-2 illustrates the internal ar ch itecture of the Intel Pentium 4 processor .
3-4 3 618 34-002 T echni cal Ref erence Gui de Processor /M emor y Subsystem 3.3 M em o r y S u bsyst em The dx6100 and dc7100 models supp ort PC2700 or PC3200 DDR memory and co me standard with PC3200 DIMMs installed. The dx61 20 models suppo rt PC2-4300 DDR2 me mory only .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 3-5 Processor /Me mor y S ubsystem T able 3-1 sho ws suggested memory co nfigurations for these systems. NO TE: T able 3-1 does not list al l possible conf igurations. Balanced -capacity , dual-channel loading yields best performance.
3-6 3 618 34-002 T echni cal Ref erence Gui de Processor /M emor y Subsystem The SPD address map is shown in T able 3-2. NO TE S: [1] Progr ammed as 128 byt es by the DIMM OEM [2] Must be progr ammed to 2 5 6 bytes .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 3-7 Processor /Me mor y S ubsystem F igur e 3-3 show s the sys tem memory map. ✎ All locations in memory are cacheable. Base memo ry is always mapp ed to DRAM. The next 128 KB fi xed memory area can, thro ugh the north bridge, be mapped to DRAM or to PCI space.
3-8 3 618 34-002 T echni cal Ref erence Gui de Processor /M emor y Subsystem.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-1 4 S ystem Sup port 4. 1 Introduc tion This chapter cov ers subjects dealing with basic system architecture and covers the follo wing topics: ■ PCI b us overvie w (4.2), page 4-1 ■ System resources (4.
4-2 3 618 34-002 T echni cal Ref erence Gui de S ystem Support F igur e 4 -1. PCI Bus De vi ces and F unctions 4.2. 1 P CI 2.3 Bus Op eration The PCI 2.3 b us consists of a 32-bit path (AD31-00 lines) that uses a multiplex ed scheme for handling both address and data tran sfers.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-3 S ystem Support Configura tion Cycles De vices on the PCI bus must comply with PCI prot ocol that allo ws configuration of that device by softw are. In this system, configuration me chanism #1 (as described in the PCI Local Bus specification Re v .
4-4 3 618 34-002 T echni cal Ref erence Gui de S ystem Support T able 4-1 shows the standard configuration of de vice numbers and IDSEL conn ections for components and slots residing on a PCI 2.3 bus. NO TE S: [1] Not used in these sy stems. [2] SFF , S T , MT , & CMT for m factor s only .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-5 S ystem Support The reg ister index (CF 8h, bits <7..2>) identif ies the 32-bit location w ithin the configuration space of the PCI de vice to be accessed.
4-6 3 618 34-002 T echni cal Ref erence Gui de S ystem Support NO TE: [1]SFF , S T , MT , and CMT for m factor s only . [2] CMT for m factor w ith P CI expansi on board PCI b us arbitration is bas ed on a round-robin sc heme that complies with the fairness algorithm specified b y the PCI specification.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-7 S ystem Support Link La yer The link layer provides data inte grity by adding a sequence information pref ix and a CRC suff ix to the packet created b y the transaction layer . Flow-control methods ensure that a pack et will only be transferred if the recei ving de vice is re ady to accomodate it.
4-8 3 618 34-002 T echni cal Ref erence Gui de S ystem Support For a PCI Express x16 transfer , a lane will be re-used ev ery17th byte of a transfer . The mux-demux process pro vided by th e physical laye r is transparent to th e other layers and to software/dri vers.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-9 S ystem Support 4.2.6 PCI Connectors PCI 2. 3 Connec tor F igur e 4 - 5 . PCI 2 .3 Bus Connec tor (3 2 -Bit, 5 . 0 -volt T ype) Ta b l e 4 - 5 . PCI 2.3 Bus Conn ector Pinou t Pin B Sign al A Signal Pin B Sign al A Signal Pin B Signal A Signal 0 1 - 1 2 V D C T RST- 22 G N D A D 28 43 + 3.
4-10 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support PCI Express Connectors F igur e 4 -6. P CI Expres s Bus Connec tors Ta b l e 4 - 6 . PCI Express Bus Connec tor Pinout Pin B Sign al A.
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-11 S ystem Support 4.3 S ystem R esources This section describes the a v ailability and basic control of major subsystems, otherwise kno wn as resource allocation or simply “s ystem resources.
4-12 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support 8259 M o d e The 8259 mode han dles interrupts IRQ0-IRQ15 in the legac y (A T -system) method using 8259-equiv alent logic. T able 4-7 lists the standa rd source configuration for maskable interrupt s and their priorities in 8259 mode.
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-13 S ystem Support APIC Mode The Adv anced Pro grammable Inte rrupt Controller (APIC) mode pro vides enhanced interrupt processing with the follo wing adv.
4-14 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support Maskable Interrupt processing is controlled and monitored th rough standard A T -type I/O-mapped registers. These re gisters are listed in T able 4-8. The initialization and operation of the interrupt control regist ers follows standard A T -type protocol.
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-15 S ystem Support The NMI Status Register at I/O port 061h contains NMI source and status data as follows: NMI Status Register 61h F unctions no t relate.
4-16 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support 4.3. 2 Direct Memor y Access Direct Memory Access (DMA) is a method by wh ich a device accesses system memory without in v olving the microprocessor .
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-17 S ystem Support DMA P age Regis ters The DMA page register contains the eight most si gnificant bits of the 24-bit address and works in conjunction with the DMA controllers to def ine the complete (24-bit) address for the DMA channels.
4-18 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support The remaining address lines are in an undefined state during the refresh c ycle. The refresh operations are driv en by a 69.799-KHz clock genera ted by Interv al T imer 1, Counter 1. The refresh rate is 128 refre sh c ycles in 2.
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-19 S ystem Support 4.4 Real- Time C loc k an d Confi guration Mem or y The Real-time clock (R TC) and conf iguration me mory (also referred to as “CMO S”) functions are provided b y the 82801 component and is MC 146818-compatible.
4-20 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support 4.4.2 CMOS Archiv e and Restore During the boot sequence the BIOS sa ves a copy of NVRAM (CM OS contents, password(s) and other system v ariables) in a portion of the flas h R OM.
T ec hnical Ref ere nce Guide 3 6183 4 -002 4-21 S ystem Support 4.4.3 Stand ard CMOS Locations T able 4-12 describes standard conf iguration me mory locat ions 0Ah-3Fh. These locations are accessible through using OUT/IN as sembly language instructions using p ort 70/71h or BIOS function INT15, AX=E823h.
4-2 2 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support Po we r - O n / S e t u p Pa s swo rd These systems inclu de a power -on and setup pass words, which may be enab led or disabled (cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82 801 ICH6 that is checked during POST .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-2 3 S ystem Support Level 0— Co ver remov al indication is essentially disabled at this le vel. During POST , status bit is cleared and no oth er action is taken b y BIOS.
4-2 4 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support 4.5 .3 S y stem Status These systems provide a visual indication of sy stem boot and R OM flash status through the ke yboard LEDs and operationa l status using bi-c olored po wer and hard dri v e activ ity LEDs as indicated in T ables 4-13 and 4-14 respecti vely .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-25 S ystem Support 4.5 .4 Thermal Sensing and Coo ling All systems feature a variable-sp eed fan mounted as part of the processor heatsi nk assembly . All systems also provide or suppor t an auxiliary chassis fan.
4-2 6 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support 4.6 Register M ap an d Miscell aneous Func tions This section contains the syst em I/O map and information on general-purpose functions of the ICH6 and I/O controller . 4.6. 1 S ystem I/O Map T able 4-15 lists the f ixed addresses of the input/output (I/O) ports.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 4-2 7 S ystem Support 4.6.2 LPC4 7B3 9 7 I/O Controller Func tions The LPC47B397 I/O controller cont ains various functions such as the ke yboard/m ouse interfaces, diskette interf ace, seri al interfaces, and parallel interf ace.
4-2 8 3 6183 4 -00 2 T echni cal Ref erence Gui de S ystem Support The conf iguration re gisters are accessed thro ugh I/O regi sters 2Eh (index) and 2Fh (data) after the conf iguration phase has been activ ated b y wr iting 55h to I/O port 2Eh.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-1 5 Inp u t/O utp ut In ter faces 5 . 1 Introduc tion This chapter describes the standard (i.e., system board) interfaces that pro vide input and output (I/O) porting of data and specif ically discusses in terfaces that are controlled through I/O-mapped registers.
5-2 3 618 34-002 T echni cal Ref erence Gui de Input/Outpu t Interface s ID E Confi guration Registers The IDE controller is conf igured as a PCI de vice with b us mastering capability . The PCI confi guration registers for the IDE controller fu nction (PCI device #3 1, function #1) are listed in T able 5-1.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-3 Input/Outpu t Interface s IDE Bus Master Contr ol Re gister s The IDE interface can perform PCI b us master operations using the re gisters listed in T able 5-2.
5-4 3 618 34-002 T echni cal Ref erence Gui de Input/Outpu t Interface s NO TE S: [1] On U A T A/3 3 and higher modes , re-defined a s ST OP . [2] On U A T A/3 3 and higher mode reads, r e -def ined as DMARD Y -. On U A T A/3 3 and higher mode wr ites, r e -defined as S TROBE .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-5 Input/Outpu t Interface s SA T A Interfaces These systems provide one, tw o, or four serial A T A (SA T A) interfaces that can pro vide certain adv antages ov er leg acy EIDE (P A T A) interface including: ■ Higher transfer rates: up to 1.
5-6 3 618 34-002 T echni cal Ref erence Gui de Input/Outpu t Interface s S A T A Bus Master Co ntr ol R egist er s The SA T A interf ace can perform PCI b us master operations using the registers listed in T able 5-5.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-7 Input/Outpu t Interface s 5 .3 Disk et te Driv e Interface The diskette dri ve interface in th ese systems support one diskette dri ve connected to a standard 34-pin diskette dri ve connector . Selected models come standard with a 3.
5-8 3 618 34-002 T echni cal Ref erence Gui de Input/Outpu t Interface s For detailed conf iguration re gister information re fer to the SMSC data sheet for the LPC47B397 I/O component.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-9 Input/Outpu t Interface s Disk ette Driv e Interface C ontrol The BIOS functi on INT 13 pro vides basic control of the diskette dri ve interf ace. The diskette driv e interface can be controlled b y software through th e LPC47B397's I/O-mapped re gisters listed in T able 5-8.
5-10 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s NO TE: T he most r ecently w ritten data r ate value to e ither DRSR or CCR w ill be in eff ect.
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-11 Input/Outpu t Interface s 5 .3.2 Disk ette Drive Connector This system uses a standard 34-pin connector (re fer to Figure 5-3 and T able 5-9 fo r the pinout) for diskette dri ves. Dri ve po wer is supplied through a separate connecto r .
5-12 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5 .4 Serial In terface Systems cov ered in this guide ma y include one RS-23 2-C type seri al interface to transmi t and receiv e asynchronous serial data with external de vices.
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-13 Input/Outpu t Interface s The serial interface configuration re gist ers are listed in the follo wing table: Seri al Inter face C ontrol The BIOS function INT 14 provides basic control of the serial interface.
5-14 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5. 5 Par a l l e l I n t e r f a c e Systems cov ered in this guide may include a para llel interface for connection to a peripheral de vice with a compatible interface, the most common being a printer .
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-15 Input/Outpu t Interface s 5. 5. 3 Ex t e n d e d C a p a b i l i t i e s Por t M o d e The Extended Capabilities Port (ECP) mode, like EPP , also uses a hardware protocol-based design that supports transfe rs up to 2 MB/s.
5-16 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s P aral le l In ter fa ce C on tro l The BIOS functi on INT 17 pro vid es simplified control of the pa rallel interface. Basic functions such as initialization, character printing, and pr inter status are pro vide by subfuncti ons of INT 17.
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-17 Input/Outpu t Interface s 5. 5. 5 P a r a l l e l I n t e r f a c e C o n n e c t o r Figure 5-5 and T able 5-15 show th e connector and pinout of the parallel interf ace connector . Note that some signals are redef ined depending on the port's operational mode.
5-18 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5 .6 K e yboar d/P ointin g De vice Interface The keyboard/pointing device interf ace function is provided by the LPC47B397 .
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-19 Input/Outpu t Interface s T able 5-16 lists and describes commands that ca n be issued by the 8042 to the keyb oard. T able 5 - 1 6. 8042- T o -Ke yboard Comman ds Comman d V alue Description Set/R eset St atus Indicators EDh Enables LED indi cators.
5-20 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s Note: [1] Used in Mode 3 only . 5 .6.2 P ointing De vice Interface O pera ting The pointing de vice (typically a mouse) co nnects to a 6-pin DIN-type connector that is identical to the ke yboard connector both p hysically and electrically .
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-21 Input/Outpu t Interface s The keyboard interface configuration regi sters are listed in the follo wing table: 804 2 C ontro l The BIOS function INT 16 is ty pically used for controlling in teraction with the k eyboard.
5-2 2 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s I/O P ort 64h I/O port 64h is used for reading the status re gi ster and for writing commands.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-2 3 Input/Outpu t Interface s A9h T est the clock and data l ines of the pointing d ev ice interface and pla ce test results in the output buffe r .
5-2 4 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5 .6.4 K e y board/P ointing De vice Interface Connec tor The legac y-light model provides separate PS/2 connecto rs for the keyboard and pointing device. Both connectors are identical both physically and electrically .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-25 Input/Outpu t Interface s 5 .7 Univ ersal Serial B us Inter face The Univ ersal Serial Bus (USB) interface pro vides asynchronous /isochronous da ta transfers with compatible pe ripherals such as keyboard s, pr inters, or modems.
5-2 6 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5. 7 . 1 U S B D a t a Fo r m a t s The USB I/F uses non-return-to-ze ro in verted (NRZI) encoding for data transmissions, in which a 1 is represented by no change (between bit tim es) in signal le vel and a 0 is represented by a change in signal le vel.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-2 7 Input/Outpu t Interface s 5. 7 . 2 U S B Pr o g r a m m i n g Programming the USB interface cons ists of conf iguration, which typically occurs during POST , and control, which occurs at runtime.
5-2 8 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s USB Co ntrol The USB is contr olled through I/O re gisters as listed in table 5-21. 5. 7 . 3 U S B C o n n e c t o r These systems provide type-A USB ports as sho wn in Figure 5-10 below .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-29 Input/Outpu t Interface s 5. 7 . 4 U S B C a b l e D a t a The recommended cable length between the host an d the USB device should be no longer than sixteen feet for full-channel (12 MB/s) opera tion, depend ing on cable specification (see follo wing table).
5-30 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5. 8 A u d i o Su bs ys t e m A block diagram of the audi o subsystem is sho wn in Figure 5-11.
T ec hnical Ref ere nce Guide 3 6183 4 -002 5-31 Input/Outpu t Interface s 5 .8. 1 AC9 7 Au dio Controller The A C97 Audio Controller is a PCI device that is inte grated into the 82801 ICH component a.
5-3 2 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5 .8.3 Audio Codec The audio codec p rovides pulse cod e modulation (PCM) coding and decoding of audio information as well as the selectio n and/or mixing of analog chann els.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-33 Input/Outpu t Interface s 5 .8.4 Audio Pr ogramming Audio subsystem p rogramming con sists configuration, typically a ccomplished du ring POST , and control, which occurs du ring runtime.
5-34 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s Audio Con trol The audio subsystem is co ntrolled through a set of indexed registers that physically reside in the audio codec . Th e register ad dresses are decoded by the audio controller and forw arded to the audio codec o ver the A C97 Link Bus pre viously described.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-35 Input/Outpu t Interface s 5 .8.5 Audio Spec ifica tions The specif ications for the integrated A C97 audio subsystem are liste d in T able 5-26.
5-3 6 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5 .9 Net work Interface C ontroll er These systems prov ide 10/100/1000 Mbps netwo rk support through a Broadcom BCM5751 network interface controller (NIC ), a PHY component, and a RJ-45 jack with integral status LEDs.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-3 7 Input/Outpu t Interface s 5. 9 . 1 W a ke - O n -L A N S u p p o r t The NIC supports the W ired-for -Management (WfM) standard of W ake-On-LAN (WOL).
5-38 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s 5. 9 . 4 N I C P ro g r a m m i n g Programming the NIC consists of conf iguration, which occurs du ring POST , and control, which occurs at runtime. The Broadcom BCM5782 is con figured as a PCI de vice an d controlled through registers mapped in v ariable I/O space.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 5-39 Input/Outpu t Interface s 5 .9 .6 NIC Spec ifications T able 5 - 2 7 . NIC Spec ifications P arameter Modes Su pported 10BA SE - T half duple x @ 10 M.
5-40 3 6183 4 -00 2 T echni cal Ref erence Gui de Input/Outpu t Interface s.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 6-1 6 Integrated G ra phi c s Subsy stem 6. 1 Introduction This chapter describes graphics subsystem th at is inte grated into the 82915G/GV GMCH component. This graphics subsystem emplo ys the use of system memory to provide ef f icient, economical 2D and 3D performance.
6-2 3 618 34-002 T echni cal Ref erence Gui de Integr ated Graphi cs Subs y stem 6.2 F unc tional Desc ription The Intel 915G/GV GMCH componen t includes an integrated graphics controller (IGC). (Figure 6-1). The IGC can directly dri ve an e xternal, anal og multi-scan monitor at resolutions up to and including 2048 x 1536 pixels.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 6-3 Integr ated Gr aphics Su bsy ste m The graphics controller integrated into the 82 915 G/GV GMCH componen t includes 2D and 3D accelerator engines working with a deeply-pipelined pre-proces sor . Hardw are cursor and ov erlay generators are also included as well as a lega c y VGA processor core.
6-4 3 618 34-002 T echni cal Ref erence Gui de Integr ated Graphi cs Subs y stem 6.2 . 1 Video Memor y Alloca tion Reporting The IGC does not hav e local memory at its dispos al but instead uses a portion of system memory allocated for frame buf fer ing and te xturing.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 6-5 Integr ated Gr aphics Su bsy ste m 6. 3 Dis pl ay Modes The IGC supports most standard display modes for 2D video displ ays up to and including 2048 x 1536 @ 85 Hz , and 3D display modes up to 1600 x 12 00 @ 85 Hz.
6-6 3 618 34-002 T echni cal Ref erence Gui de Integr ated Graphi cs Subs y stem 6.5 V GA Monitor Connec tor These systems includes a standard V GA connector (Figure 6-3) for attaching an analog monitor: F igur e 6 3. V G A Monitor C onnector , (F emale DB-15 , as vie w ed fr om rear ).
T ec hnical Ref er ence Guide 3 6183 4 -00 2 7-1 7 P o w er an d Sign al Distrib ution 7 . 1 Introduction This chapter describes the po wer supply and method of general p ower and sig nal distributio n. T opics cov ered in this chapter include: ■ Po wer supply as sembly/control (7.
7-2 3 618 34-002 T echni cal Ref erence Gui de P o w er and Signal Distribution 7 . 2. 1 P o w e r Suppl y Assembl y These systems feature power supplies with po wer factor-correction logic.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 7-3 P o w er and Signal Distribution NO TES: T otal continuous power should not ex ceed 300 watts. Total cont inuous pow er (ex cluding 5 V aux output) should not exceed 2 90 wat ts [1] Minimum loading require ments must be met at all times to ensure normal oper ation and specif ication compliance .
7-4 3 618 34-002 T echni cal Ref erence Gui de P o w er and Signal Distribution 7. 2 . 2 P o w e r C o n t r o l The po wer supply assembly is controlled digitally b y the PS On signal (Figure 7-1). When PS On is asserted, the Po wer Supply Assembly is activ ated and all voltage outp uts are produced.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 7-5 P o w er and Signal Distribution P o w er LED Indications A dual-color LED lo cated on the front panel (bez el) is used to indic ate system power status.
7-6 3 618 34-002 T echni cal Ref erence Gui de P o w er and Signal Distribution The wake up sequence for each ev ent occurs as follo ws: Wa k e - O n - L A N The network interface controller (NIC) can.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 7-7 P o w er and Signal Distribution 7 .2. 3 P o w e r Manageme nt These systems include po wer management func tions designed to conserv e energy . These functions are provided b y a combination of hardware, firmware (BIOS) and soft ware.
7-8 3 618 34-002 T echni cal Ref erence Gui de P o w er and Signal Distribution 7. 3 P o w e r D i s t r i b u t i o n 7 . 3. 1 3.3/5/1 2 VDC Dis tribution The po wer supply assembly includ es a multi-connector cable assembly that routes +3.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 7-9 P o w er and Signal Distribution Figure 7-3 sho ws the power supply cabling for the SFF/ST systems. Conn ectors not sho wn t o scale .
7-10 3 6183 4 -00 2 T echni cal Ref erence Gui de P o w er and Signal Distribution Figure 7-4 sho ws the power supply cabling for the microto wer systems.
T ec hnical Ref ere nce Guide 3 6183 4 -002 7-11 P o w er and Signal Distribution Figure 7-4 shows the po wer supply cablin g for the con vertible minito wer systems.
7-12 3 6183 4 -00 2 T echni cal Ref erence Gui de P o w er and Signal Distribution 7 .3 .2 Lo w V olta g e Production/Dis tribu tion Auxiliary v oltages less than 5 volts and al l volt ages less than 3.3 v olts are produced through regulator circuitry (Figure 7- 6) on the system board.
T ec hnical Ref ere nce Guide 3 6183 4 -002 7-13 P o w er and Signal Distribution 7 .4 Si gnal Distrib ution Figures 7-7 through 7-9 show general signal distribution between the main subassem blies of the system units. NO TE S: See F igur e 7 -10 for header pinout .
7-14 3 6183 4 -00 2 T echni cal Ref erence Gui de P o w er and Signal Distribution NO TE S: See F igur e 7 - 7 for header pinout . F igur e 7 -8. SFF / ST F or m F actor Signal Distr ibution Di agram P8 +12 VccP Power LED P1 Power P6 P5 P3 Supply Assembly +3.
T ec hnical Ref ere nce Guide 3 6183 4 -002 7-15 P o w er and Signal Distribution F igur e 7 -9 . MT / CMT For m F actor Signal Distr ibution Di agram P8 +12 VccP Power LED IDE I/F .
7-16 3 6183 4 -00 2 T echni cal Ref erence Gui de P o w er and Signal Distribution NO TE: No polar ity consideratio n requir ed for connec tion to speak er header P6 .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 8-1 8 BIO S R O M 8. 1 Introduc tion The Basic Input/Output System (BIOS) of the computer is a collectio n of mach ine langua ge programs stored as firmw are in read-only memory (R OM).
8-2 3 618 34-002 T echni cal Ref erence Gui de BIO S ROM This chapter includes the follo wing topics: ■ R OM flashing (8.2), page 8-2 ■ Boot functions (8.3), page 8-3 ■ Setup utility (8.4) , page 8-6 ■ Client management functions (8. 5), page 8-17 ■ PnP support (8.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 8-3 BIOS R OM 8.2.2 C han gea bl e Sp la sh Sc reen ✎ A corrupted splash screen may be restored by the user with the R OMP A Q softw are. Depending on the system, changing (customizing) the splash screen may only be a vailable with asistance from HP .
8-4 3 618 34-002 T echni cal Ref erence Gui de BIO S ROM 8.3. 2 Ne twork Boot (F1 2) Sup por t The BIOS support s booting the sy stem to a network serv er . The fu nction is accessed by pressing the F12 ke y when prompted at th e lower righ t hand corner of the display during POST .
T ec hnical Ref er ence Guide 3 6183 4 -00 2 8-5 BIOS R OM 8.3 .4 Boot Error Codes The BIOS provides visual and audible indications of a failed system boot by using the LEDS on the PS/2 ke yboard and the system board speaker . The error conditions are listed in the fol lowing table.
8-6 3 618 34-002 T echni cal Ref erence Gui de BIO S ROM 8.4 Setup Utilit y The Setup utility (stored in R OM) allo ws the user to configure syst em functions in volving security , power management, and system resources. The Setup utility is R OM-based and in voked when the F1 0 key is pressed and held during the compu ter boot cycle.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 8-7 BIOS R OM Fi l e (continued) Sav e Changes and Ex it Sav es c hanges to s y stem conf igur ation or defa ult settings and e xits Compu ter S etu p. Sto rag e D evice Conf igur ation L ists all installed BIO S -contr olled stor age de vi ces .
8-8 3 618 34-002 T echni cal Ref erence Gui de BIO S ROM Tr a n s l a t i o n Pa r a m e t e r s (A T A disks only ) ✎ This feature appears only when User translation mode is selected.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 8-9 BIOS R OM Secondary SA T A Controller Allo ws y ou to e nable or disable the S econdar y S A T A contr oller .
8-10 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM Smart Co ver Allow s y ou to: • Lo ck / u n l oc k t h e Cove r Lock. • Set the Co ve r Remo val Sensor to Dis able/Notify User/Setup Pa s s w o r d . ✎ Notify User alerts the user that the sens or has detected that the cover has been removed.
T ec hnical Ref ere nce Guide 3 6183 4 -002 8-11 BIOS R OM Dr iv eL ock S ec urity Allo ws yo u to as sign o r modify a mast er or u ser pa ss wor d for MultiBay har d dri ve s. When this featur e is enabled, the user is pr ompted to pro v ide one of the Dri v eLock pas sw or ds during PO S T .
8-12 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM Restor e M aster Boot Recor d* Re stor es the bac kup Ma ster Boot Recor d to the c urr ent boot able disk. ✎ Only appears if all o f the following conditions are true: MBR Security is enabled.
T ec hnical Ref ere nce Guide 3 6183 4 -002 8-13 BIOS R OM Advan c ed * *F or adv anced users on ly P ower - On Options Allows y ou to set: • PO S T mode (QuickBoot , FullBoot , or F ullBoot ev ery 1-30 day s) . • PO S T mes sages (ena ble/disable).
8-14 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM Advan c ed * (continued) *F or adv anced users on ly Po w e r - O n O p t i o n s (continued) Allo ws y ou to set: (continued) • A CPI/U SB Buffer s @ T op o f Memory (enable/disable). Enabling this featur e places USB memory buffer s at the top of me mory .
T ec hnical Ref ere nce Guide 3 6183 4 -002 8-15 BIOS R OM Advan c ed * (continued) *F or adv anced users on ly Dev ice opti ons Allow s y ou to set: • Pri nter mode (bi-dir ec tional , EPP & E CP , output onl y) . • Num Lo ck state at po w er-on (o ff/on) .
8-16 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM 8. 5 Client Ma nagement Fu nction s T able 8-4 provides a partial list of the client management BIOS functions supported b y the systems cov ered in this guide. These functions , designed to support intelligent manageability applications, are Compaq-specif i c unless otherw ise indicated.
T ec hnical Ref ere nce Guide 3 6183 4 -002 8-17 BIOS R OM 8.5 . 1 Sy stem ID and ROM T ype Diagnostic applications can use the INT 15, AX= E800h BIOS functio n to identify the type of system. This function will return the system ID in the BX re gister .
8-18 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM 8.6 PnP Sup port The BIOS includes Plug 'n Play (PnP) suppor t for PnP version 1.0A. T able 8-6 lists the PnP functions supported. The BIOS call INT 15, AX=E841h, BH=01h can be used by an application to retrie ve the def ault settings of PnP de vices for the user .
T ec hnical Ref ere nce Guide 3 6183 4 -002 8-19 BIOS R OM 8.6. 1 SMB I OS In support of the DMI specif ication the PnP func tions 50h and 51h are used to retrie ve the SMBIOS data. Function 50h retrie ves the number of structures, size of the lar gest structure, and SMBIOS v ersion.
8-20 3 6183 4 -00 2 T echni cal Ref erence Gui de BIO S ROM.
T ec hnical Ref er ence Guide 3 618 34 -00 2 A-1 A Err or Mess a g es and C odes A. 1 Introduc tion This appendix lists the error co des and a brief d escription of the probable cause of the error . ✎ Errors listed in this appendix are applicable only for systems running HP/Compaq BIOS .
A-2 3 6183 4 -00 2 Tec hnical R efer ence Guide Err or Messages and C odes A.3 P ow er- O n Self T e st (POS T) M essag es Ta b l e A -2 . P o w er- On Self T est (PO ST) Me ssages Erro r Message Probable Cause Inv alid Electronic Ser ial Number Chassis serial number is corrupt .
T ec hnical Ref er ence Guide 3 618 34 -00 2 A-3 Err or Mess ages and C odes 512 -Cha ssis F an Not Detect ed Chassis f an is not connected . 514 -CPU or Chas sis Fan not detec ted. CPU f an is not connected o r may hav e malfunc tioned . 601-Disk ette C ontr oller Err or Diskette dr iv e r emo ved since pr ev iou s boot .
A-4 3 6183 4 -00 2 Tec hnical R efer ence Guide Err or Messages and C odes 17 9 4 -Inaccessible de vi ces attached to SA T A 1 and/or S A T A 3 (for sy stems w ith 4 SA T A ports) A dev ice is attac hed to SA T A 1 and/or SA T A 3 .
T ec hnical Ref er ence Guide 3 618 34 -00 2 A-5 Err or Mess ages and C odes A.4 S y ste m Er r or Me ssages ( 1 xx - xx) NO TE S: [1] 10 2 message code may be caused b y one of a vari ety of processor -re lated problems that may be sol ved by r eplacing the proces sor , although sy stem board r eplacement may be needed.
A-6 3 6183 4 -00 2 Tec hnical R efer ence Guide Err or Messages and C odes A.5 Memory Err or Me ssages (2xx - xx) Ta b l e A - 4 . Memo ry Err or Me ssages Message Probable Cause 200 -04 Real memory s.
T ec hnical Ref er ence Guide 3 618 34 -00 2 A-7 Err or Mess ages and C odes A. 6 K e yboard Er ror Messa g es (30x - xx) 211-0 2 Er ror w hile sav ing memory during r andom memor y pattern test 211-0.
A-8 3 6183 4 -00 2 Tec hnical R efer ence Guide Err or Messages and C odes A. 7 Printer Error Messa ges (4xx - xx) A. 8 Video (G rap hic s) Error Messa g es (5 xx - xx) See T able A-14 fo r additional video (gr aphics) mes sages.
T ec hnical Ref er ence Guide 3 618 34 -00 2 A-9 Err or Mess ages and C odes A .9 Disk ette Driv e Error Messa g es (6xx - xx) 600-xx = Disk ette dr iv e ID test 609- xx = Disk ette dri ve r es et contr oller te st 601- xx = Diskette dr iv e for mat 610 -xx = Disk ette dri ve c hange line test 60 2 -xx = Disk ette r ead tes t 611-xx = Pri .
A-10 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes A. 1 0 Serial Inter face Error Messa g es ( 1 1xx - xx) Ta b l e A - 9. Serial Inter face Err or Messag es Message Pro bable Cause Message Pr obable Cause 1101-01 U ART DLAB bit failure 1101-13 UAR T cntrl .
T ec hnical Ref erence Gui de 3618 3 4 -002 A-11 Err or Mess ages and C odes A. 1 1 Mo dem Com mun icat io ns Er r or Me ssage s ( 1 2xx - x x) Ta b l e A -1 0.
A-12 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes NO TE S: [1] Local loopback mode [4] Modem auto originate test [2] Analog loopback originate mode [5] Modem auto ans wer t est [3] Analog loopback answ er mode [6] Modem direct connect t est A.
T ec hnical Ref erence Gui de 3618 3 4 -002 A-13 Err or Mess ages and C odes A . 1 3 H ard Driv e Error Messa g es ( 1 7xx - xx) T able A- 1 2 Hard Drive Error Mess ag es Message Pro bable Cause Message Probable Cause 17xx-01 Exceeded max . soft err or limit 17xx -51 Failed I/O r ead test 17xx-0 2 Ex ceeded max.
A-14 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes NO TE: xx = 00, Hard dr iv e ID test xx = 19 , Hard dr iv e pow er mode test xx = 01, Hard dr iv e format te st xx = 20, SM.
T ec hnical Ref erence Gui de 3618 3 4 -002 A-15 Err or Mess ages and C odes A . 1 4 H ard Driv e Error Messa g es ( 1 9xx - xx) 1900-xx = T ape ID test f ailed 19 04 -xx = T ape BO T/E O T test faile.
A-16 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes A. 1 5 Video (G raphi c s) Error Messag es (24xx - xx) A. 1 6 Audio Err or Messa g es ( 3 206 - xx) T able A- 1 4 Video (Gr.
T ec hnical Ref erence Gui de 3618 3 4 -002 A-17 Err or Mess ages and C odes A. 1 7 D VD/CD-ROM Er ror Messa ges ( 33xx - xx) A. 1 8 Ne t w ork Inter face Err or M essa ges (60xx - xx) Ta b l e A -1 6.
A-18 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes A. 1 9 SC S I Interface Error Messag es (6 5xx - xx, 6 6xx - xx, 6 7xx - xx) n = 5, Har d dri ve = 6, CD-ROM dr ive = 7 , T.
T ec hnical Ref erence Gui de 3618 3 4 -002 A-19 Err or Mess ages and C odes A.20 P ointing De vice Interface Erro r Messa g es ( 8 6 01-x x ) Ta b l e A -1 9 P ointi ng De vice I nterface E rror Mess.
A-20 3 6183 4 -00 2 T echni cal Ref erence Gui de Err or Messages and C odes.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 B-1 B ASCII C harac ter Set B. 1 In troduction This appendix lists, in T able B-1, the 256-char acter AS CII code set in cluding the decimal and hexadecimal v alues .
B-2 3 6183 4 -00 2 Tec hnical R efer ence Guide AS CII Char acter Set 18 12 × 50 32 2 8 2 5 2 R 114 72 r 19 13 !! 51 3 3 3 8 3 5 3 S 115 7 3 s 20 14 ¶ 5 2 34 4 84 5 4 T 116 7 4 t 21 15 § 53 3 5 5 8.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 B-3 AS CII Char acter Set NO TE S: [1] S ymbol no t display ed. Keys t ro ke G u i d e : Dec # Key s t ro k e ( s ) 0C t r l 2 1-2 6 Ctrl A t hru Z res pe .
B-4 3 6183 4 -00 2 Tec hnical R efer ence Guide AS CII Char acter Set.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 C-1 C Key b o a r d C . 1 In troduction This appendix describes the HP ke yboard that is included as stan dard with the system unit.
C-2 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd F igur e C-1. K ey str ok e Proces sing Elements, Block Diagr am When the system is turned on, the keyboard pr ocessor generates a Po wer-On Reset (POR) signal after a period of 150 ms to 2 seconds.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 C-3 Key b o a r d C . 2. 1 PS/ 2-T yp e Ke yboard T ra ns mi s si o ns The PS/2-type ke yboard sends two main types of da ta to the system; comman ds (or responses to system commands) and ke ystroke scan codes.
C-4 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd C .2.2 USB-T ype K e y board T ransmissions The USB-type keyboard sends es sentially the same information to the system that the PS/2 ke ybo.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 C-5 Key b o a r d C.2. 3. 2 W indo w s Enhanc ed K e y boar ds F igur e C-5 . U . S. English W indo ws (101W -K e y) K ey board K e y P ositions F igur e C-6.
C-6 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd C .2.3.3 Ea sy Acces s K e yboard The Easy Access keyboard is a W indo ws Enhanced -type ke yboard that includes special buttons allo wing quick in ternet navigation. The Easy Access Ke yboard uses the PS/2 -type connection.
T ec hnical Ref er ence Guide 3 6183 4 -00 2 C-7 Key b o a r d C.2 . 4 K e y s All ke ys generate a Make code (when pressed) and a Break co de (when released ) with the exception of the Pau s e key (p os.
C-8 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd Alt —The Alt key s (pos. 93/95) can be used in conju n ction with the same keys a v ailable for use with the Ctr l k eys with the e xception that position 14 ( Sy s R q ) is av ailable instead of position 16 ( Break ).
T ec hnical Ref er ence Guide 3 6183 4 -00 2 C-9 Key b o a r d C .2.4.4 Ea sy Access K e y strok es The Easy Access ke yboards(Figures C-7) include additional ke ys (also re ferred to as b uttons) used to streamline internet access and navigation.
C-10 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd C .2.5 K e yboard Comm ands T able C-1 lists the commands that the ke yboard can send to the system (specifically , to the 8042-type logic). Note: [1] Mod es 2 and 3 . [2] Mode 1 only . Ta b l e C - 1 .
T ec hnical Ref ere nce Guide 3 6183 4 -002 C-11 Key b o a r d C.2 . 6 Sc an Co de s The scan codes generated b y the ke yboard processo r are determined b y the mode the keyboard is operating in. ■ Mode 1: In Mode 1 operation, the k eyboard generates scan codes compatible with 8088-/8086-based systems.
C-12 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd 14 Print Sc rn E0 2A E0 3 7/E0 B7 E0 AA E0 3 7/E0 B7 [1] [2] 54/ 84 [ 3 ] E0 2A E0 7C/E0 F0 7C E0 F0 12 E0 7C/E0 F0 7C [1] [2] 84/ F0 84 [ .
T ec hnical Ref ere nce Guide 3 6183 4 -002 C-13 Key b o a r d 35 Num Lo ck 45 /C 5 77 /F 0 77 7 6 /n a 36 / E0 35 / E 0 B 5 E0 AA E0 3 5/E0 B5 E0 2A [1] E0 4A/E0 F0 4A E0 F0 12 E0 4A/E0 F0 4A E0 12 [.
C-14 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd 5 8 + 4E/CE [6] 7 9/F0 7 9 [6] 7C/F0 7C 5 9 Ca ps Loc k 3A/B A 5 8/F0 5 8 14/F0 14 60 A 1E/9E 1C/F0 1C 1C/F0 1C 61 S 1F/9F 1B/F0 1B 1B/F0 1.
T ec hnical Ref ere nce Guide 3 6183 4 -002 C-15 Key b o a r d 8 5 / 35/B5 4A/F0 4A 4A/F0 4A 86 S h i f t ( ri g h t ) 36 / B 6 59 / F 0 59 59 / F 0 59 87 E 0 4 8 / E 0 C 8 E0 AA E0 48/E0 C8 E0 2A [4].
C-16 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd All codes assume Shift, C trl, and Al t key s inactiv e unless otherwise noted . NA = Not applicable [1] Shift (left) k ey act iv e. [2] Ctr l ke y acti ve . [3] Alt k ey acti ve . [4] Left Shift k ey ac tiv e.
T ec hnical Ref ere nce Guide 3 6183 4 -002 C-17 Key b o a r d C. 3 Co n ne ct o r s T wo types o f keyboard interfaces may be used in HP/Compaq systems: PS/2-type and US B-type. System units that provide a PS/2 connector will ship with a PS/2-type ke yboard but may also support simultaneous connection of a USB keyboard.
C-18 3 618 34-002 T echni cal Re fer ence Guide Key b o a rd.
T ec hnical Ref er ence Guide 3618 3 4 -002 Index–1 Ind e x Numerics 8259 Mode 4-12 A AC97 Audio Controller 5-31 Advanced Digital Display (ADD2) 6-22 advanced, Computer Setup heading 7-13 APIC Mode .
Index– 2 3 6183 4 -00 2 T echnical R ef erence Gui de Index S SATA 4-1 SATA Connector 4-6 SDVO 6-2 security Computer Setup heading 9 serial interface 5-12 Serial Interface Connector 5-12 serial numb.
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