Instruction/ maintenance manual of the product HD6433690G Hitachi
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Hitachi Single-Chip Microcomputer H8/3694 Series H8/36 94 HD64336 94G, HD643 3694 H8/36 93 HD64336 93G, HD643 3693 H8/36 92 HD64336 92G, HD643 3692 H8/36 91 HD64336 91G, HD643 3691 H8/36 90 HD64336 90G, HD643 3690 H8/36 94F-ZTA T TM HD64F3 694G, H D64F3694 Hardware Manual ADE-602-252 Rev.
Rev. 1.0, 0 7/01, page ii of xxi v.
Rev. 1.0, 0 7/01, Page iii of xxiv Cautions 1. Hitachi neither warrant s nor grant s licenses of any ri ghts of Hit achi’s or any t hird party’s patent, copyright , trademark, o r other inte llectual property rights for information c ontained in this document.
Rev. 1.0, 0 7/01, page iv of xxiv.
Rev. 1.0, 0 7/01, Page v of xxiv Preface The H8/3694 Seri es is a singl e-chip microcomputer ma de up of the high-speed H8/3 00H CPU as its core, and the peripheral functions req uired to configure a system. T he H8/300H CPU has an instruction set th at is compatible with the H8/300 CPU.
Rev. 1.0, 0 7/01, page vi of xxiv 5. When the E10T is used, address breaks can be set as available to t he user, or for use by the E10T. If address breaks are set as bein g used by the E10T, the add ress break control registers must not be accessed. 6.
Rev. 1.0, 0 7/01, Page vii of xxiv Contents Section 1 Overview........................................................................................................... ......... 1 1.1 Overview ........................................................
Rev. 1.0, 0 7/01, page viii of xxiv 3.4.1 External Interrupts ............................................................................................... 50 3.4.2 Internal Interrupts ................................................................
Rev. 1.0, 0 7/01, Page ix of xxiv 6.4 Direct Transition ........................................................................................................... .... 78 6.4.1 Direct transition from the active mo de to the subactive mode ...........
Rev. 1.0, 0 7/01, page x of xxiv 9.1.4 Port Pull-Up Control Regis ter 1(PUCR1) ............................................................ 114 9.1.5 Pin Functions .......................................................................................
Rev. 1.0, 0 7/01, Page xi of xxiv 11.3.5 Timer Control Register V1(TC RV1) ................................................................... 143 11.4 Operation..........................................................................................
Rev. 1.0, 0 7/01, page xi i of xxiv Section 14 Serial Communication Interface3 (SCI3) ........................................ 181 14.1 Features ..........................................................................................................
Rev. 1.0, 0 7/01, Page xiii of xxiv 15.3.6 Slave Address Regis ter (SAR) ............................................................................. 232 15.3.7 I 2 C B us Transmit Data Register (IC DRT) ..............................................
Rev. 1.0, 0 7/01, page xi v of xxiv Section 18 Power Supply Circuit ...................................................................... 273 18.1 W hen Using the Internal Power Supply St ep-Down Circuit ............................................. 273 18.
Rev. 1.0, 0 7/01, Page xv of xxiv Figures of Contents Section 1 Overview Figure 1- 1 Internal Block Diagram of H8/3694 Series of t he F-Z T AT TM and Mas k-ROM Versions ..................................................................................
Rev. 1.0, 0 7/01, page xvi of xxiv Figure 5-5 Ty pical Connection to Ceramic Oscillator .................................................................. 65 Figure 5-6 Ex ample of External Clock In put ................................................
Rev. 1.0, 0 7/01, Page xvii of xxiv Figure 11-8 C lear Timing by TMRIV Inpu t ............................................................................... 146 Figure 11-9 Puls e Output Example .......................................................
Rev. 1.0, 0 7/01, page xviii of xxi v Figure 14- 3 Relation ship betw een Output Clock and Trans fer Data Phas e (A synchronous Mode)(Example with 8-Bit Data, Parity , T w o Stop Bits).............. 195 Figure 14-4 Sam ple SCI Initialization Flowchart .
Rev. 1.0, 0 7/01, Page xix of xxiv Figure 15-17 Sam ple Flowchart for Master Transmit Mode ...................................................... 246 Figure 15-18 Sam ple Flowchart for Master Receive Mode ..............................................
Rev. 1.0, 0 7/01, page xx of xxi v Figure B.11 Port 7 Bl ock Diagram (P76) ................................................................................... 359 Figure B.12 Port 7 Bl ock Diagram (P75) ................................................
Rev. 1.0, 0 7/01, Page xxi of xxiv Tables of Contents Section 1 Overview Table 1-1 Pin Functions ......................................................................................................... ....... 4 Section 2 CPU Table 2-1 Operation Notation.
Rev. 1.0, 0 7/01, page xxii of xxiv Table 7-7 Command Sequ ence in Programmer Mode ................................................................ 96 Table 7-8 AC Characteristics in Transition to Memory Read Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V , T a = 25°C ± 5°C).
Rev. 1.0, 0 7/01, Page xxiii of xxiv Section 16 A/D Converter Table 16-1 Pin Configuration .................................................................................................. 25 5 Table 16-2 Analog Input Channels and Corresponding ADDR Re gisters .
Rev. 1.0, 0 7/01, page xxiv of xxiv.
Rev. 1.0, 0 7/01, page 1 of 372 Section 1 Overview 1.1 Overview • High-speed H8/300H central processing u nit with an internal 16-bit architecture Upward-compatible with H8/300 and H8 /300H CPUs.
Rev. 1.0, 0 7/01, page 2 of 372 1.2 Internal Block Diagram P10/TMOW P11 P12 P14/ P15/ P16/ P17/ /TRGV P50/ P51/ P52/ P53/ P54/ P55/ / P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB.
Rev. 1.0, 0 7/01, page 3 of 372 1.3 Pin Arran gement NC NC AV CC X2 X1 V CL TEST V SS OSC2 OSC1 V CC P50/ P51/ NC NC 1 2 3 4 5 6 7 8 9 1 01 11 2 1 31 41 5 1 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35.
Rev. 1.0, 0 7/01, page 4 of 372 AVcc X2 X1 V CL TEST V SS OSC2 OSC1 Vcc P50/ P51/ 123 4 5 678 9 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 P22/TXD P21/RXD P20/SCK3 P87 P86 P85 P84/FTIOD P83/FTIOC.
Rev. 1.0, 0 7/01, page 5 of 372 1.4 Pin Functions Table 1-1 Pin Functions Pin No. Type Symbol FP-64E FP-64A FP-48F I/O Functions Power source V CC 12 10 Input Power suppl y pin. Conne ct this pin to the system pow er suppl y. pins V SS 9 7 Input Ground pin.
Rev. 1.0, 0 7/01, page 6 of 372 Pin No. Type Symbol FP-64E FP-64A FP-48F I/O Functions Timer W FTCI 36 26 Input External event input pin. FTIOA to FTIOD 37 to 40 27 to 30 I/O Output compare output/ inpu t capture in put/ PWM output pin I 2 C bus inerface SDA 26 20 I/O IIC data I/O pin.
Rev. 1.0, 0 7/01, page 7 of 372 Section 2 CPU This LSI has an H8 /3 00H CPU with an intern al 32-bit architecture that is up word-compatib le with the H8/300CPU, and su pports only normal mode, whic h has a 64-kbyte ad dress space.
Rev. 1.0, 0 7/01, page 8 of 372 2.1 Address S pace and Memory Map The address space of this LSI is 64 kbytes, which inclu des the program area and the data area.
Rev. 1.0, 0 7/01, page 9 of 372 Interrupt vector On-chip ROM (16 kbytes) On-chip RAM (512 bytes) Internal I/O register H'0000 H'0033 H'0034 H'3FFF H'FF7F H'FF80 H'FF.
Rev. 1.0, 0 7/01, page 10 of 372 2.2 Register Configuration The H8/300H CPU has the internal regis ters shown in fi gure 2-2. There are two types of re gisters; general registers and control registers. The control re gisters are a 24-bit program cou nter (PC), and an 8-b it con d ition code reg ister ( CCR).
Rev. 1.0, 0 7/01, page 11 of 372 2.2.1 General Registers The H8/300H CPU has eight 32-bit general regist ers. These general re gisters are all funct ionally identical and can be used as both ad dress registers and data registers. When a general register is used as a data register, it can be accessed as a 32 -bit, 16-bit, or 8-bit register.
Rev. 1.0, 0 7/01, page 12 of 372 SP (ER7) F ree area Stack area Figure 2-4 Rela tionship b etween Stack Poin ter and Stack Area 2.2.2 Program Cou nter (PC) This 24-bit cou n ter indicates the address of the nex t instruction th e CPU will execute.
Rev. 1.0, 0 7/01, page 13 of 372 Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks int errupts ot her than NMI wh en set to 1. NMI is acce pted regar dless of t he I bit sett ing. The I bit is set to 1 at th e start of an except ion- handling sequence .
Rev. 1.0, 0 7/01, page 14 of 372 2.3 Data Formats The H8/300H CPU can proces s 1-bit, 4-bit (BCD), 8-bit (byte), 16-bi t (word), a nd 32-bit (longword) data. B it-manipulation instructions operate on 1-bit data by acces sing bit n (n = 0, 1, 2, …, 7) of byte operand data.
Rev. 1.0, 0 7/01, page 15 of 372 15 0 MSB LSB 15 0 MSB LSB 31 16 MSB 15 0 LSB ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General .
Rev. 1.0, 0 7/01, page 16 of 372 2.3.2 Mem ory Data Formats Figure 2-6 shows the data formats in memory. The H8/300H CPU can access word data and longword data i n memory, however wo rd or longword data must begi n at an even addres s.
Rev. 1.0, 0 7/01, page 17 of 372 2.4 Instruction Set 2.4.1 Tab le of Instru ctions Classifi ed by Function The H8/300H CPU has 62 instructions. Tables 2-2 to 2-9 summarize the instructions in each functional categ ory. The notat ion used in ta bles 2-2 to 2 -9 is defined bel ow.
Rev. 1.0, 0 7/01, page 18 of 372 Table 2-2 Data Transfer Instructions Instruction Size * Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general reg isters or betw een a ge neral regist er and memory, or moves im mediate dat a to a genera l register.
Rev. 1.0, 0 7/01, page 19 of 372 Table 2-3 Arithmetic Operations In structions (1) Instruction Size * Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addit ion or subtracti on on da.
Rev. 1.0, 0 7/01, page 20 of 372 Table 2-3 Arithmetic Operations In structions (2) Instruction Size * Function DIVXS B/W Rd ÷ Rs → Rd Performs signed d ivision on data in two general regi sters: either 16 bits ÷ 8 bits → 8- bit quotient and 8-bit remai nder or 32 bit s ÷ 16 bits → 16-b it quotient and 16-bit remai nder.
Rev. 1.0, 0 7/01, page 21 of 372 Table 2-4 Logic Operations Instructions Instruction Size * Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a log ical AND op eration on a general regi ster and ano ther general re gister or imm ediate data.
Rev. 1.0, 0 7/01, page 22 of 372 Table 2-6 Bit Manipula tion Inst ructions (1) Instruction Size * Function BSET B 1 → (<bit-No.> of <EAd> ) Sets a speci fied bit in a general re gister or memor y operand to 1. Th e bit number is spec ified by 3- bit immediate data or the l ower three bit s of a general re gister.
Rev. 1.0, 0 7/01, page 23 of 372 Table 2-6 Bit Manipula tion Inst ructions (2) Instruction Size * Function BXOR BIXOR B B C ⊕ (<bit-No.> of <EAd>) → C XORs the carry flag with a s pecified bit i n a general r egister or m emory operand and s tores the result in the carry flag.
Rev. 1.0, 0 7/01, page 24 of 372 Table 2-7 Branch Instructions Instruction Size Function Bcc * — Branches to a specified address if a specifi ed condition is true.
Rev. 1.0, 0 7/01, page 25 of 372 Table 2-8 System Control Instructions Instruction Size * Function TRAPA — Starts trap-instr uction ex ception han dling. RTE — Returns from an except ion-handli ng routine. SLEEP — Causes a transiti on to a power-d own state.
Rev. 1.0, 0 7/01, page 26 of 372 Table 2-9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4 L Until R 4L = 0 else ne xt; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R 4 = 0 else ne xt; Transfers a da ta block.
Rev. 1.0, 0 7/01, page 27 of 372 • Operation Field Indicates the fu nction of the ins truction, the a ddressing mo de, and the operatio n to be carried out on the ope rand. The operati on field always includes the fi rst four bits of the instruct ion.
Rev. 1.0, 0 7/01, page 28 of 372 2.5 Addressing M odesand Effec tive Address C alculation The following des cribes the H8/3 00H CPU. In this LSI, t he upper eight bits are i gnored in the generated 24-bit address, s o the effective addres s is 16 bits .
Rev. 1.0, 0 7/01, page 29 of 372 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement c ontained in the instruction is added to an a ddress register (ERn) specified by the register field of the instructio n, and the lower 24 bits of the sum t he address of a memory operand.
Rev. 1.0, 0 7/01, page 30 of 372 The instruction c ontains 8-bit (#x x:8), 16-bit (#x x:16), or 32-bit (#xx:32 ) immediate data as an operand. The ADDS, SUBS, INC, and DEC in structions contain immediate data imp licitly . So me bit manipulation ins tructions contain 3-bit i mmediate data i n the instructi on code, specifyi ng a bit number.
Rev. 1.0, 0 7/01, page 31 of 372 Table 2-12 Effective Address Calculation (1) No 1 r op 31 0 23 2 3 Register indirect with displacement @(d:16,ERn) or @(d:24,ERn) 4 r op disp r op rm op rn 31 0 0 r op.
Rev. 1.0, 0 7/01, page 32 of 372 Table 2-12 Ef fective Address Calculation ( 2) No 5 op 23 0 abs @aa:8 7 H'FFFF op 23 0 @aa:16 @aa:24 abs 15 16 23 0 op abs 6 op IMM #xx:8/#xx:16/#xx:32 8 Addressi.
Rev. 1.0, 0 7/01, page 33 of 372 2.6 Basic Bus Cycle CPU operation i s synchronized b y a system clock ( ø) or a subclock ( ø SUB ). The period from a ris ing edge of ø or ø SUB to the next risi ng edge is call ed one state. A bus c ycle consists of two states or three states.
Rev. 1.0, 0 7/01, page 34 of 372 2.6.2 On-Chip Peripheral Modules On-chip peripheral mod ules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description o n the data bus widt h and number of accessing states of each register, refer to section 19, Inter nal I/O Registers.
Rev. 1.0, 0 7/01, page 35 of 372 2.7 CPU States There are four C PU states: the reset state, program execution state, program halt state, and exception-handling state. The pr ogram execution state includes active mode and subactive mode. For the program halt state there are a sleep m ode, standby mode, a nd sub-sleep mode.
Rev. 1.0, 0 7/01, page 36 of 372 Reset state Program halt state Exception-handling state Program execution state Reset cleared SLEEP instruction executed Reset occurs Interrupt source Reset occurs Interrupt source Exception- handling complete Reset occurs Figure 2-12 S tate Transiti ons 2.
Rev. 1.0, 0 7/01, page 37 of 372 Example 1 : Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the series of this LSI.) Figure 2-13 shows an example of a timer in which two timer registers are assigned to the same address.
Rev. 1.0, 0 7/01, page 38 of 372 • Prior to executing BSET in struction P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High .
Rev. 1.0, 0 7/01, page 39 of 372 • Prior to executing BSET in struction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 The PDR5 value (H'8 0) is written to a work area in memory (RAM0) as well as to PDR5.
Rev. 1.0, 0 7/01, page 40 of 372 • Prior to executing BCLR in struction P57 P56 P55 P54 P53 P52 P51 P50 Input/outp ut Input Input Output Output Output O utput Output Output Pin state Low level High .
Rev. 1.0, 0 7/01, page 41 of 372 • Prior to executing BCLR in struction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 The PCR5 value (H'3 F) is written to a work area in memory (RAM0) as well as to PCR5.
Rev. 1.0, 0 7/01, page 42 of 372.
Rev. 1.0, 0 7/01, page 43 of 372 Section 3 Exception Handling Exception handl ing may be cause d by a reset, a tra p instruction (TRAPA), or inte rrupts. • Reset A reset has t he highest exception pri ority. Exception handl ing starts as soon as the reset is cleared by the RES pin.
Rev. 1.0, 0 7/01, page 44 of 372 Table 3-1 Exception Sources and Vector Address Vector Exception Source s Number Vector Address Priority Reset 0 H'0000 to H'0001 High Reserved f or system us.
Rev. 1.0, 0 7/01, page 45 of 372 Vector Exception Source s Number Vector Address Pr iority IIC2 Transmit dat a empty Transmit end Receive data ful l NACK detect ion Arbitration lo st/Overrun err or St.
Rev. 1.0, 0 7/01, page 46 of 372 Bit B it Name Initial V alue R/W Description 2 IEG2 0 R/W IRQ2 Edge Se lect 0: Falling ed ge of IRQ2 p in input is detected 1: Rising edge of IRQ2 pin input is d etect.
Rev. 1.0, 0 7/01, page 47 of 372 3.2.3 In terrupt Enable Regi ster 1(IENR1) IENR1 enables direct tran sition interrupts, tim er A overflow interrupts, and external p in interrupts.
Rev. 1.0, 0 7/01, page 48 of 372 3.2.4 In terrupt Flag Register 1(I RR1) IRR1 is a status flag register for direct transit ion interrupt s, timer A overfl ow interrupts , and IRQ3 to IRQ0 interrupt reques ts.
Rev. 1.0, 0 7/01, page 49 of 372 3.2.5 Wak eup Interrupt Fl ag Register(IWPR) IWPR is a st atus flag register for WKP5 to WKP0 interru pt requests. Bit B it Name Initial V alue R/W Description 7 6 − − 1 1 − − Reserve d These bits ar e always read as 1, and cannot be modifie d.
Rev. 1.0, 0 7/01, page 50 of 372 3.3 Reset When the RES pin goes lo w, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip pe ripheral modules are initialized by the reset.
Rev. 1.0, 0 7/01, page 51 of 372 WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signa ls to pins WKP 5 to WKP 0. These six interrupts have the same vector addresses , and are detected indivi dually by eit her rising edge sensing or fal ling edge s ensing, depe nding on the set tings of bits WPEG5 to W PEG0 in IEGR2.
Rev. 1.0, 0 7/01, page 52 of 372 3.4.3 Interr upt Handling Seque nce Interrupt s are controll ed by an inter rupt control ler. Interrupt operat ion is desc ribed as follows . 1. If an interrupt occurs while th e NMI or in terrup t enable b it is set to 1 , an interrupt request signal is sent to th e interrupt contro ller.
Rev. 1.0, 0 7/01, page 53 of 372 PC and CCR saved to stack SP (R7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (R7) Even address Prior to start of interrupt exception.
Rev. 1.0, 0 7/01, page 54 of 372 Vector fetch ø Internal address bus Internal read signal Internal write signal (2) Internal data bus (16 bits) Interrupt request signal (9) (1) Internal processing Prefetch instruction of interrupt-handling routine (1) Instruction prefetch address (Instruction is not executed.
Rev. 1.0, 0 7/01, page 55 of 372 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC an d CCR will not be sav ed correctly, leading to a program crash. To prevent th is, all in terrupt requests, including NMI, are disabled immediately after a reset.
Rev. 1.0, 0 7/01, page 56 of 372.
Rev. 1.0, 0 7/01, page 57 of 372 Section 4 Address Break The address brea k simplifies on-board program debugging. It requests an ad dress break inter rupt when th e set break co ndition is sa tisf ied. Th e interru p t request is n o t affec te d by the I b it of CCR.
Rev. 1.0, 0 7/01, page 58 of 372 4.1.1 Address Break Control Register(ABRKCR) ABRKCR s ets address break co nditions. Bit B it Name Initial V alue R/W Description 7 RTINTE 1 R/W RTE Interrupt En able When this bit is 0, the i nterrupt immedi ately after executing R TE is maske d and then o ne instr uction must be executed .
Rev. 1.0, 0 7/01, page 59 of 372 Table 4-1 Access and Data Bus Used Word Access Byte Access Even Address Odd Address Even Address Odd Address ROM space Upper 8 bit s Lower 8 bits Upper 8 bits Upper 8 .
Rev. 1.0, 0 7/01, page 60 of 372 4.1.4 Break Data Registers (BDRH, BDRL) BDR (BDRH, BDRL) i s a 16-bit read/write register that sets the d a ta fo r generating an address break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is co mpared with the lower 8-bit data bus.
Rev. 1.0, 0 7/01, page 61 of 372 MOV instruc- tion 1 prefetch Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A 025C 0260 0262 : * NOP NOP MOV.
Rev. 1.0, 0 7/01, page 62 of 372 RTE instruc- tion prefetch Register setting • ABRKCR = H'10 Program 0258 025A 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP NOP : 039C Address bus φ Inter.
Rev. 1.0, 0 7/01, page 63 of 372 Section 5 Clock Pulse Generators Clock oscillator circu itry (CPG: clock pu lse generator) is provided on -chip, including bo th a system clock pul se generator and a s ubclock puls e generator.
Rev. 1.0, 0 7/01, page 64 of 372 LPM Note : LPM: Low-power mode (standby mode, subactive mode, or subsleep mode) 2 1 OSC OSC Figure 5-2 Block Diagram of the S ystem Clock Generator 5.1.1 Connecting a Crystal Oscilla to r Figure 5- 3 sh ows a typical metho d of connecting a crystal oscillator.
Rev. 1.0, 0 7/01, page 65 of 372 5.1.2 Connecting a Ceramic Oscillato r Figure 5- 5 sh ows a typical metho d of connecting a ceramic oscillator. OSC 1 OSC 2 C 1 C 2 C 1 = 30 pF ±10% C 2 = 30 pF ±10% Figure 5-5 Ty pica l Connection to Ceramic Oscillato r 5.
Rev. 1.0, 0 7/01, page 66 of 372 5.2.1 Connecting a 3 2.768-kH z Crystal Oscillator Clock pulse s can be supplied to the subclock di vider by co nnecting a 32.768 -kHz crystal oscillator, as shown in figure 5-8. Figure 5- 9 sh ows the equivalen t circuit of the 32.
Rev. 1.0, 0 7/01, page 67 of 372 5.3 Prescalers 5.3.1 Prescaler S Prescaler S i s a 13-bit counter using the s ystem clock (ø) as i ts input clock. The divided output is used for the internal cloc k of on-chip periphe ral modules. Prescaler S is initialized to H'0000 by a reset, and st arts counting on ex it from the rese t state.
Rev. 1.0, 0 7/01, page 68 of 372 5.4.2 Notes on Board Design When using a crystal resonator (ceramic resonator ), place the resonator and its load capacitors as close as possible to the OSC 1 and OSC 2 pins .
Rev. 1.0, 0 7/01, page 69 of 372 Section 6 Power-down Modes This LSI has s ix modes of operati on after a res et. These include a normal active mo de and four power-down modes , in which power di ssipation i s significantl y reduced. The mod ule standby mode reduces power dissipation by selectively haltin g on-chip module functio ns.
Rev. 1.0, 0 7/01, page 70 of 372 6.1.1 System Control Regi ster 1(SYSCR1) The SYSCR 1 register controls the power-down modes, as well as SYS CR2. Bit B it Name Initial V alue R/W Description 7 SSBY 0 R/W Software Standby This bit se lects the m ode to trans it after the e xecution o f the SLEEP instruct ion.
Rev. 1.0, 0 7/01, page 71 of 372 Table 6-1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 0 0 8,192 stat es 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 stat es 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 stat es 2.
Rev. 1.0, 0 7/01, page 72 of 372 6.1.2 System Control Regi ster 2(SYSCR2) The SYSCR 2 register controls the power-down modes, as well as SYS CR1. Bit B it Name Initial V alue R/W Description 7 6 5 SMS.
Rev. 1.0, 0 7/01, page 73 of 372 Bit B it Name Initial V alue R/W Description 7 − 0 − Reserve d This bit is always read as 0 and cann ot be modif ied 6 MSTIIC 0 R/W IIC2 Modul e Standby IIC2 enter.
Rev. 1.0, 0 7/01, page 74 of 372 Reset state Standby mode Active mode Sleep mode Subsleep mode Subactive mode Program halt state Program execution state Program halt state SLEEP instruction SLEEP instruction Interrupt Direct transition interrupt Direct transition interrupt Notes: 1.
Rev. 1.0, 0 7/01, page 75 of 372 Table 6- 2 Tra nsition Mode af ter SLEEP Instr uction Ex ecutio n and Tran sition Mo de due to Interrupt DTON SSBY SMSEL LSON Transition Mode aft er SLEEP Instruction .
Rev. 1.0, 0 7/01, page 76 of 372 Table 6-3 Internal State in Each Operating Mode Function Active Mode Sleep Mode Subactive Mode Subsleep Mode Standby Mode System clock osci llat or Functioning Func ti.
Rev. 1.0, 0 7/01, page 77 of 372 When the RES pin goes low, the CPU goes into the reset state and the sleep m ode is cleared. 6.2. 2 Sta ndby Mode In the standby mo de, the clock p ulse generator st ops, so the CPU and o n-chip perip heral modules stop functioni ng.
Rev. 1.0, 0 7/01, page 78 of 372 6.2.4 Subactiv e Mo de The operating fre quency of t he subactive mode is selected from ø W /2, ø W /4, and ø W /8 by the SA1 and SA0 bits in SYSCR2. The operating frequency changes to the s et frequency after SLEEP instruction execution.
Rev. 1.0, 0 7/01, page 79 of 372 Legend tosc: OSC clock cycle time tw: Watch clock cy cle tim e tcyc: System clock (ø) cycle time tsubcyc: Subclock (ø SUB ) cycle time 6.
Rev. 1.0, 0 7/01, page 80 of 372.
Rev. 71, 07/01, page 81 of 3 72 Section 7 ROM The features of the 32-b it flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programmin g/erase methods The flash memo ry is programm ed 128 bytes at a time. Erase is perf ormed in singl e-block units.
Rev. 1.0, 0 7/01, page 82 of 372 H'007F H'0000 H'0001 H'0002 H'00FF H'0080 H'0081 H'0082 H'03FF H'0380 H'0381 H'0382 H'047F H'0400.
Rev. 71, 07/01, page 83 of 3 72 7.2.1 Flash Memory Control Regi ster 1 (FLMCR1) FLMCR1 is a regi ster that makes t he flash memory change t o program mode , program-verify mode, erase mode, or erase-verify m ode. For detail s on regist er setting, refer to section 7.
Rev. 1.0, 0 7/01, page 84 of 372 7.2.2 Flas h Memory Control Regi ster 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/e rasing.
Rev. 71, 07/01, page 85 of 3 72 7.2.4 Flash Memory Power Control Register (FL PWCR) FLPWCR enables or disables a transition to the flash memory power-do wn mode when the LSI switches to subactive mode. The power s upply circ uit can be read i n the subactive mode, although it is part ly halted in the power-d own mode.
Rev. 1.0, 0 7/01, page 86 of 372 7.3 On-Board Programming Modes There are two modes for programmi ng/erasing of the flash memory; boot mode, which enables on- board programmin g/erasing, an d programmer mode, i n which programming/e rasing is perfor med with a PROM programmer.
Rev. 71, 07/01, page 87 of 3 72 4. After matchin g the bit rates, the chip transmits on e H'00 byte to the host to indicate the completion o f bit rate a djustment. The host shoul d confirm that this adjustment e nd indicati on (H'00) has been received n ormally, and transmit one H'55 byte to the chip.
Rev. 1.0, 0 7/01, page 88 of 372 Table 7-2 Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at reset-start. Processing Contents Processing Contents Bit rate adjustment Continuously transmits data H'00 at specified bit rate.
Rev. 71, 07/01, page 89 of 3 72 7.3.2 Programm ing/Erasi ng in User Program Mode On-board program ming/erasing of an individ ual flash memory block can als o be performed in us er program mode by branching t o a user program/eras e control pr ogram. The user mus t set branchi ng conditions and provide on-board means of supplyin g programmi ng data.
Rev. 1.0, 0 7/01, page 90 of 372 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to pr ogram and erase fl ash memory in the on- board programmin g modes.
Rev. 71, 07/01, page 91 of 3 72 START End of programming Set SWE bit in FLMCR1 to 1 Write pulse application subroutine Wait 1 µ s Apply Write Pulse End Sub Set PSU bit in FLMCR1 to 1 WDT enable Disab.
Rev. 1.0, 0 7/01, page 92 of 372 Table 7-4 Reprogra m Data Comput ation Ta ble Program Data Verify Data Reprogram Data Comments 0 0 1 Programming complet ed 0 1 0 Reprogram bit 101 — 1 1 1 Remains i.
Rev. 71, 07/01, page 93 of 3 72 6. If the read data is not erased erased successfully, set erase mode a gain, and repeat the erase/erase-verify sequen ce as before. The maxim um numb er of repetitions o f th e erase/erase- verify seque nce is 100. 7.4.
Rev. 1.0, 0 7/01, page 94 of 372 Erase start Set EBR1 Enable WDT Wait 1 µ s Wait 100 µ s Set SWE bit in FLMCR1 to 1 n = 1 Set ESU bit in FLMCR1 to 1 Set E bit to 1 Wait 10 µ s Clear E bit to 0 Wait.
Rev. 71, 07/01, page 95 of 3 72 7.5 Program/Erase Protection There are three kin ds of flash memor y program/erase protecti on; hardware prot ection, software protection, a nd error protect ion.
Rev. 1.0, 0 7/01, page 96 of 372 7.6 Programmer Mode In programmer mo de, a PROM programmer ca n be used to perform progra mming/erasing vi a a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Hitachi 64-kbyte flas h memory (F-ZTAT64V 5).
Rev. 71, 07/01, page 97 of 3 72 H8/3694F FP-64A/FP-64E Socket Adapter (Conversion to 32-pin arrangement) Pin No. Pin Name P54 P76 P20 P80 P81 P82 P83 P84 P85 P86 P87 P10 P14 P15 P16 P17 P50 P51 P52 P53 P21 P55 P56 P57 P74 P75 P22 TEST PB3 AV CC V CC X1 V SS V CL PB2 PB1 PB0 OSC1, OSC2 (OPEN) HN28F101 (32 Pins) Pin No.
Rev. 1.0, 0 7/01, page 98 of 372 7.6.3 Mem ory Read Mode 1. After completio n of auto-program/auto-erase/status read operatio n s, a transition is made to the command wait state. When reading mem ory contents, a transition to memory read mode must first be made with a command write, after whic h the memory contents are read.
Rev. 71, 07/01, page 99 of 3 72 Table 7-9 AC Characteristics i n Transition from Memory Read Mode to Another Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25°C ±5 °C) Item Symbol Min M.
Rev. 1.0, 0 7/01, page 1 00 of 372 A15–A0 I/O7–I/O0 t acc t acc t oh t oh Address stable Address stable Figure 7-8 CE and OE Enab le State Read Tim ing Waveforms A15–A0 I/O7–I/O0 t acc t ce t oe t oe t ce t acc t oh t df t df t oh Address stable Address stable Figure 7-9 CE and OE Clock Sys tem Read Timin g Waveforms 7.
Rev. 71, 07 /01, page 10 1 of 372 7. Perform one auto-program operation for a 128-byte block fo r each address. Two or more additional pr ogramming operatio ns cannot be per formed on a previ ously programmed a ddress block. 8. Confirm normal end of auto-pr ogramming by c hecking I/O6.
Rev. 1.0, 0 7/01, page 1 02 of 372 A15–A0 I/O7 I/O6 I/O5–I/O0 t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc Address stable H'40 H'00 Data transfer 1 to 128 bytes Write operation end decision signal Write normal end decision signal Figure 7-10 Au to-Program Mode Timing Waveform s 7.
Rev. 71, 07 /01, page 10 3 of 372 Table 7-12 AC Characteristics in Au to-Erase Mode (Conditions : V CC = 5.0 V ±0.5 V, V SS = 0 V, T a = 25 °C ±5°C) Item Symbol Min Max Unit Notes Comm and write c.
Rev. 1.0, 0 7/01, page 1 04 of 372 7.6.6 Statu s Read Mode 1. Status read mode is pr ovided to ident ify the ki nd of abnormal e nd. Use this mode when an abnormal end occurs in auto-pr ogram mode or a uto-erase mode. 2. The return code is retained until a com m and write other than a status read mode comm and write is executed.
Rev. 71, 07 /01, page 10 5 of 372 Table 7-14 St a tus Read Mode Return Code s Pin Name Initial Value Indications I/O7 0 1: Abnormal en d 0: Normal end I/O6 0 1: Command error 0: Otherwi se I/O5 0 1: P.
Rev. 1.0, 0 7/01, page 1 06 of 372 7.6.8 Programm er Mode Trans ition Time Commands cannot be accepted during the oscillation s tabilization period or the pro grammer mode setup period. After the pro grammer mode setu p time, a transiti on is made to mem ory read mode.
Rev. 71, 07 /01, page 10 7 of 372 7.7 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the followin g states: • Normal operatin g mode The flash memory can be read and written to at high speed.
Rev. 1.0, 0 7/01, page 1 08 of 372.
Rev. 1.0, 0 7/01, page 1 09 of 372 Section 8 RAM This LSI has 2 kb yte, 1 kbyte o r 512 kbytes of on-chip hi gh-speed st atic RAM. The RAM i s connected to the CPU by a 1 6-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Rev. 1.0, 0 7/01, page 1 10 of 372.
Rev. 1.0, 0 7/01, page 1 11 of 372 Section 9 I/O Ports The series of t his LSI has twent y-nine general I/ O ports and eig ht input-only ports. Port 8 is a large current port, which ca n drive 20 mA (@V OL = 1. 5 V) when a low level si gnal is out put.
Rev. 1.0, 0 7/01, page 1 12 of 372 9.1.1 Port M ode Register 1(PMR1) PMR1 s witches the functions of pins i n port 1 and port 2. Bit B it Name Initial V alue R/W Description 7 IRQ3 0 R/W P17/ IRQ3 /TRGV Pin Function Swit ch This bit se lects wh ether pin P17/ IRQ 3 /TR GV i s us ed as P17 or as IRQ3 /TRGV.
Rev. 1.0, 0 7/01, page 1 13 of 372 9.1.2 Port Control Register 1(PCR1) PCR1 select s inputs/output s in bit units for pins to be used as general I/O ports of port 1.
Rev. 1.0, 0 7/01, page 1 14 of 372 9.1.4 Port Pull-Up Control Register 1(PUCR1) PUCR1 cont rols the pull- up MOS in bit units of the pins set as the input p orts.
Rev. 1.0, 0 7/01, page 1 15 of 372 P15/ IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 0 1 P15 output pin 1X IRQ1 input pin Legend X: Don't care.
Rev. 1.0, 0 7/01, page 1 16 of 372 P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 0 1 P10 output pin 1 X TMOW output pin Legend X: Don't care. 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin .
Rev. 1.0, 0 7/01, page 1 17 of 372 Bit B it Name Initial V alue R/W Description 7 6 5 4 3 − − − − − − − − − − − − − − − Reserve d 2 1 0 PCR22 PCR21 PCR20 0 0 0 W W W When.
Rev. 1.0, 0 7/01, page 1 18 of 372 P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 0 1 P21 output pin 1 X RXD input pin Legend X:Don't care.
Rev. 1.0, 0 7/01, page 1 19 of 372 Port 5 has the following registers. For details on re gister addresses and register states during each process, refer to s ection 19, Internal I/O Regist er. • Port mode re gister 5(PMR5) • Port control register 5(PCR5) • Port data regi ster 5(PDR5) • Port pull-up control regis ter 5(PUC R5) 9.
Rev. 1.0, 0 7/01, page 1 20 of 372 Bit B it Name Initial Value R/W Description 0 WKP0 0 R/W P50/ WKP0 Pin F unction Sw itch Selects wh ether pin P50/ WKP0 is used as P50 or as WKP0 . 0: P50 I/O port 1: WKP0 input pi n 9.3.2 Port Control Register 5(PCR5) PCR5 select s inputs/output s in bit units for pins to be used as general I/O ports of po rt 5.
Rev. 1.0, 0 7/01, page 1 21 of 372 9.3.4 Port Pull-up Control Register 5(PUCR5) PUCR5 cont rols the pull- up MOS in bit units of the pins set as the input p orts. Bit Bit Name Initial Value R/W Description 7 6 − − 0 0 − − Reserve d These bits ar e always read as 0 and cannot be modifie d.
Rev. 1.0, 0 7/01, page 1 22 of 372 P55/ WKP5 / ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 0 1 P55 output pin 1X WKP5 / ADTRG input pin Legend X: Don't care.
Rev. 1.0, 0 7/01, page 1 23 of 372 P51/ WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 0 P51 input pin 0 1 P51 output pin 1X WKP1 input pin Legend X: Don't care.
Rev. 1.0, 0 7/01, page 1 24 of 372 9.4.1 Port Control Register 7(PCR7) PCR7 select s inputs/output s in bit units for pins to be used as general I/O ports of po rt 7.
Rev. 1.0, 0 7/01, page 1 25 of 372 9.4.3 Pin Function s The corresponde nce between the regis ter specificati on and the port f unctions is s hown below.
Rev. 1.0, 0 7/01, page 1 26 of 372 9.5 Port 8 Port 8 is a general I/O port also functioning as a Timer W I/ O pin. Each pin of t he port 8 is shown in figure 9-5 . The register s etting of the timer W has priorit y for functio ns of the pi ns P84/FTIOD, P83/FTIOC , P82/FTIOB, and P81/ FTIOA.
Rev. 1.0, 0 7/01, page 1 27 of 372 9.5.2 Port Data Register 8(PDR8) PDR8 is a general I/O port data regi ster of port 8. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDR8 stores o utput data for port 8 pins.
Rev. 1.0, 0 7/01, page 1 28 of 372 P84/FTIOD pi n Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting Value 0 0 0 0 P84 input/FTIOD inp ut pin 0 0 0 1 P84 output/FTIOD input p in 0 0 1 X FTIOD output pin 0 1 X X FTIOD output pin 1 X X 0 P84 input/FTIOD input p in 1 X X 1 P84 output/FTIOD input p in Legend X: Don't care.
Rev. 1.0, 0 7/01, page 1 29 of 372 P81/FTIOA pi n Register TIOR0 PCR8 Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function Setting Value 0 0 0 0 P81 input/FTIOA inp ut pin 0 0 0 1 P81 output/FTIOA input p in 0 0 1 X FTIOA output pin 0 1 X X FTIOA output pin 1 X X 0 P81 input/FTIOA input p in 1 X X 1 P81 output/FTIOA input p in Legend X: Don't care.
Rev. 1.0, 0 7/01, page 1 30 of 372 9.6.1 Port Data Register B(PDRB) PDRB i s a general input-o nly port data register of port B. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 − − − − − − − − R R R R R R R R The input va lue of each pin is read by reading this register.
Rev. 1.0, 0 7/01, page 1 31 of 372 Section 10 Timer A Timer A is an 8-bit tim er with interv al timing and real-time clock tim e-b a se function s. Th e clo ck time-base function is available when a 32.768kHz crystal os cillator is connected. Figure 10-1 shows a block diag ram of timer A.
Rev. 1.0, 0 7/01, page 1 32 of 372 ø W TMOW ø ø W /32 ø W /16 ø W /8 ø W /4 ø W /32 ø W /16 ø W /8 ø W /4 ø/8192, ø/4096, ø/2048, ø/512, ø/256, ø/128, ø/32, ø/8 ø W /128 ø W /4 1/4.
Rev. 1.0, 0 7/01, page 1 33 of 372 10.3.1 T imer Mode Register A(T MA) Bit Bit Name Initial Value R/W Description 7 6 5 TMA7 TMA6 TMA5 0 0 0 R/W R/W R/W Clock Output Select 7 to 5 These bits select the clock outp ut at the TMO W pin.
Rev. 1.0, 0 7/01, page 1 34 of 372 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-co unter, which is incremented by internal clock input. The clock source for input t o this counter is selected by bi ts TMA3 to TMA0 in TMA. TCA values can be read by the CP U in active mode, but ca nnot be read i n subactive mode.
Rev. 1.0, 0 7/01, page 1 35 of 372 10.5 Usage Note When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system cl ock, so it i s synchronized b y a synchronizin g circuit.
Rev. 1.0, 0 7/01, page 1 36 of 372.
Rev. 1.0, 0 7/01, page 1 37 of 372 Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external e vents. Compare- match signals with two regist ers can also be used t o reset the count er, request an inter rupt, or output a pulse si gnal with an arbitrary duty c ycle.
Rev. 1.0, 0 7/01, page 1 38 of 372 TRGV TMCIV TMRIV TMO V ø T rigger control Clock select Clear control Output control PSS TCR V1 TCORB Comparator TCNTV Comparator TCORA TCR V0 Interrupt request cont.
Rev. 1.0, 0 7/01, page 1 39 of 372 11.3 Register Descrip tion s Time V has the followi ng registers. F or details on register addres ses and register s tates during each process, refer to section 19, I nternal I/O Registers.
Rev. 1.0, 0 7/01, page 1 40 of 372 11.3.3 Timer Control Register V0(TCRV0) TCRV0 selects the input clock s ignals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interr upt request.
Rev. 1.0, 0 7/01, page 1 41 of 372 Table 11- 2 C lo ck signals to input to TCNTV a nd the counting co nditions TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 CKS2 CKS1 CKS0 IC KS0 Description 000 − C lock inpu.
Rev. 1.0, 0 7/01, page 1 42 of 372 11.3.4 Timer Control/Status Register V(TCSRV) TCSRV indicates the status fl ag and controls output s by using a c ompare match.
Rev. 1.0, 0 7/01, page 1 43 of 372 OS3 and OS2 sel ect the output level for compare match B. OS1 and OS0 sel ect the output l evel for compare matc h A. The two output levels can be cont rolled inde pendently. Aft er a reset, the timer outpu t is 0 until the first compare match.
Rev. 1.0, 0 7/01, page 1 44 of 372 11.4 Operation 11.4.1 Timer V operation 1. According to ta ble 11-2, six i nternal/external cl ock signals output by pres caler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up.
Rev. 1.0, 0 7/01, page 1 45 of 372 N – 1 N + 1 N ø TMCIV (External clock input pin) TCNTV input clock TCNTV Figure 11-3 Increment Timing with External Clock H'FF H'00 ø TCNTV Overflo w s.
Rev. 1.0, 0 7/01, page 1 46 of 372 ø Compare match A signal Timer V output pin Figure 11-6 T MOV Output T iming N H'00 ø Compare match A signal TCNTV Figure 11-7 Clear Timing by Compare M atch N – 1 N H'00 ø Compare match A signal Timer V output pin TCNTV Figure 11-8 Clear Timing by TMRIV Input 11.
Rev. 1.0, 0 7/01, page 1 47 of 372 4. With these sett in gs, a waveform is output with ou t furth er software intervention, with a period determined by TC ORA and a pulse widt h determined by TC ORB. Counter cleared TCNTV H'FF TCORA TCORB H'00 TMOV Figure 11-9 Pu lse Output E xample 11.
Rev. 1.0, 0 7/01, page 1 48 of 372 Counter cleared TCNTV H'FF TCORA TCORB H'00 TRGV TMOV Compare match A Compare match B clears TCNTV and halts count-up Compare match B clears TCNTV and halts count-up Compare match A Figure 11-10 Ex ample of Pulse Output Sy nchronized to TRGV In put 11.
Rev. 1.0, 0 7/01, page 1 49 of 372 ø Address TCNTV address TCNTV write cycle by CPU Internal wr ite signal Counter clear signal TCNTV N H'00 T 1 T 2 T 3 Figure 11-11 Contention between TCNTV Wri.
Rev. 1.0, 0 7/01, page 1 50 of 372 Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11-13 I nternal Clock Sw itching and T CNTV Operation.
Rev. 1.0, 0 7/01, page 1 51 of 372 Section 12 Timer W Timer W has a 16-bit timer havin g output compare a nd input captu re functions. Ti mer W can count external events and out put pulses with an arbitrary duty c y cle by compare match between the timer counter an d four general registers.
Rev. 1.0, 0 7/01, page 1 52 of 372 Table 12-1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Count clock Internal clo cks: φ , φ /2, φ /4, φ /8 External clo ck: FTCI Gene.
Rev. 1.0, 0 7/01, page 1 53 of 372 Internal clock: External clock: FTCI FTIOA FTIOB FTIOC FTIOD IRRTW Control logic Clock selector Comparator TCNT Internal data bus Bus interface Legend : TMRW: Timer .
Rev. 1.0, 0 7/01, page 1 54 of 372 12.3 Register Descrip tion s Timer W has the fol lowing regist ers. For details on register addres ses and regi ster states during each process, refer to section 19, I nternal I/O Registers.
Rev. 1.0, 0 7/01, page 1 55 of 372 Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter o peration is halted wh en this bit is 0; while it can be perform ed when t his bit is 1. 6 − 1 − Reserve d This bit is always read as 1 and cann ot be modif ied.
Rev. 1.0, 0 7/01, page 1 56 of 372 12.3.2 Timer Control Register W(TCRW) TCRW selects the timer counter cloc k source, selects a clearing con dition, and specifies the timer initial outpu t levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT val ue is clear ed by com pare match A w hen this bit is 1.
Rev. 1.0, 0 7/01, page 1 57 of 372 12.3.3 Timer In terrupt Enabl e Register W(TIERW ) TIERW controls the timer W in terru pt request. Bit Bit Name Initial Value R/W Description 7 OVIE 0 R/W Timer Overflow Int errupt Enable When this bit is set to 1, FOVI interrupt re quested by O VF flag in TSRW is enable d.
Rev. 1.0, 0 7/01, page 1 58 of 372 Bit Bit Name Initial Value R/W Description 3 IMFD 0 R/W Input Capture/Compare M atch Flag D [Setting cond itions] • TCNT=G RD when GRD functions a s an output comp.
Rev. 1.0, 0 7/01, page 1 59 of 372 12.3.5 Timer I/O Con trol Register 0(TIOR0) TIOR0 selects the functions of GRA and GRB , and specifies the functi ons of the FTIOA and FTIOB pins . Bit Bit Name Initial Value R/W Description 7 − 1 − Reserve d This bit is always read as 1 and cann ot be modif ied.
Rev. 1.0, 0 7/01, page 1 60 of 372 12.3.6 Timer I/O Con trol Register 1(TIOR1) TIOR1 select s the functions of GR C and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 − 1 − Reserve d This bit is always read as 1 and canno t be modif ied.
Rev. 1.0, 0 7/01, page 1 61 of 372 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. T he clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA b y setting the CCLR of TCRW to 1.
Rev. 1.0, 0 7/01, page 1 62 of 372 12.4 Operation • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free -running or periodic counti ng operati ons. After a reset , TCNT is set as a free- running count er. When the CS T bit in TMRW is set to 1, TCNT start s incrementing the count .
Rev. 1.0, 0 7/01, page 1 63 of 372 TCNT value GRA H'0000 CST bit IMFA Time Flag cleared by software Figure 12-3 Periodic Counter Operation By setting a general register as an output compa re register, compare match A, B, C, or D can cause the outp ut at the FTIOA, FTIOB, F TIOC, or FTIOD pin to output 0, output 1, or t oggle.
Rev. 1.0, 0 7/01, page 1 64 of 372 TCNT value H'FFFF H'0000 FTIOA FTIOB Time GRA GRB Toggle output Toggle output Figure 12-5 T oggle Output E xample (TOA = 0, T OB = 1) Figure 12-6 s hows another exa mple of toggle output when TCNT ope rates as a periodic count er, cleared by compare match A.
Rev. 1.0, 0 7/01, page 1 65 of 372 TCNT value H'FFFF H'1000 H'0000 FTIOA GRA Time H'AA55 H'55AA H'F000 H'1000 H'F000 H'55AA GRB H'AA55 FTIOB Figure 12.
Rev. 1.0, 0 7/01, page 1 66 of 372 12.4.2 PWM Operation In PWM mode, PW M waveforms are generated by using GRA as the period regist er and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB , FTIOC, and FTIOD pins. Up to t hree-phase PW M waveforms can be output .
Rev. 1.0, 0 7/01, page 1 67 of 372 TCNT value GRA GRB GRC H'0000 FTIOB FTIOC FTIOD Time GRD Counter cleared by compare match A Figure 12-10 PWM Mode Example (2) Figure 12-11 s hows an example of buffer ope ration when the F TIOB pin is se t to PWM mode and GRD is set as the buffer register for GRB.
Rev. 1.0, 0 7/01, page 1 68 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously.
Rev. 1.0, 0 7/01, page 1 69 of 372 TCNT value GRA H'0000 FTIOB Time GRB Duty 100% Write to GRB TCNT value GRA H'0000 FTIOB Time GRB Duty 0% Write to GRB Write to GRB Output does not change when cycle register and duty register compare matches occur simultaneously.
Rev. 1.0, 0 7/01, page 1 70 of 372 12.5 Operation Timing 12.5.1 TCNT Co unt Timing Figure 12-14 s hows the TCNT count timing when the i n ternal clock source is selected.
Rev. 1.0, 0 7/01, page 1 71 of 372 Figure 12- 16 shows the out put compare t iming. GRA to GRD TCNT TCNT input clock φ N N N+1 Compare match signal FTIOA to FTIOD Figure 12-16 O utput Compare Output Timing 12.
Rev. 1.0, 0 7/01, page 1 72 of 372 12.5.4 Timing of Co unter Clearing by Co mpare Match Figure 12-18 shows the timing when the counter is cleared by compare match A.
Rev. 1.0, 0 7/01, page 1 73 of 372 GRA, GRB TCNT Input capture signal φ GRC, GRD N M M N+1 N N N+1 Figure 12-20 Buf f er Operation Timing (Input Ca pture) 12.
Rev. 1.0, 0 7/01, page 1 74 of 372 12.5.7 Timing of IMFA t o IMFD Setting at Input Capture If a general regis ter (GRA, GRB , GRC, or GRD) is us ed as an input capture regi ster, the corresponding IMFA, IMFB, IMFC, or IMF D flag is set to 1 when an input capture occurs.
Rev. 1.0, 0 7/01, page 1 75 of 372 12.6 Usage Notes The following t ypes of contenti on or operat ion can occur in t imer W operati on. 1. The pulse width o f the input cl ock signal and the input capture sig nal must be at least two system clock ( φ ) cycles; shor ter pu lses will not be de tected correctly.
Rev. 1.0, 0 7/01, page 1 76 of 372 TCNT Previous clock N N+1 N+2 N+3 New clock Count clock The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.
Rev. 1.0, 0 7/01, page 1 77 of 372 Section 13 Watchdog Timer The watchdog timer(WDT) is an 8 - bit tim er th at can generate an internal reset signal for this LSI if a system crash prev ents the CPU fro m writing to the timer counter, thus allowing it to overflow.
Rev. 1.0, 0 7/01, page 1 78 of 372 13.2.1 Timer Control/Status Register WD(TCSRWD) TCSRWD is a register that indi cates TCSRWD and TCW D write control, wat chdog timer operation c ontrol, and t he operati on status.
Rev. 1.0, 0 7/01, page 1 79 of 372 Bit Bit Name Initial Value R/W Description 0 WRST 0 R/W Watchdog Timer Reset [Setting cond ition] When TCWD ov erflows an d an interna l reset signal is generated [Clearing cond iti on] • Reset by RES pi n • When 0 is writte n to the WR ST bit while writ ing 0 to the B0WI bit when the TCSRWE bit=1 13.
Rev. 1.0, 0 7/01, page 1 80 of 372 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when TCS RWE in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD is required.
Rev. 1.0, 0 7/01, page 1 81 of 372 Section 14 Serial Communication Interface3 (SC I3) Serial Communication Inter face (SCI) can handle both asynchronous a nd clocked synchronous serial communicat ion.
Rev. 1.0, 0 7/01, page 1 82 of 372 Clock TXD RXD SCK 3 BRR SMR SCR3 SSR TDR RDR TSR RSR Transmit/receive control circuit Internal data bus Legend RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: Receive .
Rev. 1.0, 0 7/01, page 1 83 of 372 14.2 Input/Output Pins Table 14-1 s hows the SCI pi n configurati on. Table 14- 1 P in Co nfigurat io n Pin Name Abbrev. I/O Function SCI clock SCK3 I/O SCI clock input/output SCI receive data input RXD Input SCI receive dat a input SCI transmit dat a output TXD Output SCI transmit dat a output 14.
Rev. 1.0, 0 7/01, page 1 84 of 372 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is us ed to receive serial data input from the RxD pin a nd convert it into parallel data. When one frame of data has been received, it is transferred to R DR automatically.
Rev. 1.0, 0 7/01, page 1 85 of 372 14.3.5 Serial Mode Regis ter (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate ge nerator clock source.
Rev. 1.0, 0 7/01, page 1 86 of 372 Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W R/W Clock Sel ect 0 and 1 These bits select the clock so urce for the b aud rate generator.
Rev. 1.0, 0 7/01, page 1 87 of 372 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiproce ssor Interrupt E nable (enab led only when the M P bit in SMR i s 1 in asyn chronous mode) When th.
Rev. 1.0, 0 7/01, page 1 88 of 372 14.3.7 Serial Status Regi ster (SSR) SSR is a register containing status flags of the SCI and multiprocesso r b its for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PE R, and FER; they can only be cleared.
Rev. 1.0, 0 7/01, page 1 89 of 372 Bit Bit Name Initial Value R/W Description 4 FER 0 R/W Framing Error [Setting cond ition] • When a fram ing error oc curs in rec eption [Clearing cond iti on] • .
Rev. 1.0, 0 7/01, page 1 90 of 372 14.3.8 Bit Rate Register (BRR) BRR is an 8- b it register th at adjusts the b it r ate. The initial va lu e of BRR is H'FF. T a b le 13-2 shows the r e latio nship b e tween the N setting in BRR an d the n setting in bits CKS1 an d CKS0 of SMR in asynchronous mode.
Rev. 1.0, 0 7/01, page 1 91 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (1 ) Operating Frequenc y ø (MHz) 2 2.097152 2.457 6 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.
Rev. 1.0, 0 7/01, page 1 92 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (2 ) Operating Frequenc y ø (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.
Rev. 1.0, 0 7/01, page 1 93 of 372 Table 14- 2 Ex a mples of BRR Setting s for Va rious Bit Rate s ( Asynchronous Mode) (3 ) Operating Frequenc y ø (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) nN Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.
Rev. 1.0, 0 7/01, page 1 94 of 372 Table 14- 4 BRR Set t ing s for Vario us Bit Rates (Clo cked Sy nchrono us Mode) Operating Frequenc y ø (MHz) 2 4 8 10 16 Bit Rate (bit/s) nN nN nN n N n N 1 1 0 3 7 0 — —— —— — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
Rev. 1.0, 0 7/01, page 1 95 of 372 14.4 Operation in Asynchronous Mode Figure 14-2 s hows the general f ormat for async hronous seri al communication. One character (or frame) consists of a start b it (lo w level), followed by d ata (in LSB-first order), a parity bit (h igh or low level), and finally stop bits (high level).
Rev. 1.0, 0 7/01, page 1 96 of 372 14.4.2 SCI Initialization Before transmitting and receivin g data, you sh ould first clear th e TE and RE bits in SCR3 to 0 , then initialize the SCI as de scrib ed b elow.
Rev. 1.0, 0 7/01, page 1 97 of 372 14.4.3 Data Trans mission Figure 14-5 s hows an example o f operation for tra n smission in asynchr onous mode. In transmiss ion, the SCI operates as described below.
Rev. 1.0, 0 7/01, page 1 98 of 372 No Yes Start transmission Read TDRE flag in SSR [1] Write transmit data to TDR Yes No No Yes Read TEND flag in SSR [2] No Yes [3] Clear PDR to 0 and set PCR to 1 Cle.
Rev. 1.0, 0 7/01, page 1 99 of 372 14.4.4 Serial Data Reception Figure 14-7 s hows an example o f operation for rece ption in as ynchronous mode. In serial reception, the SCI operates as described bel ow.
Rev. 1.0, 0 7/01, page 2 00 of 372 Table 14-5 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF * OER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferr.
Rev. 1.0, 0 7/01, page 2 01 of 372 Yes No Start reception [1] No Yes Read receive data in SSR [3] Clear RE bit in SCR3 to 0 Read OER, PER, and FER flags in SSR Error processing [4] Read receive data in RDR Yes No OER+PER+FER = 1 RDRF = 1 All data received? [1] Read the OER, PER, and FER flags in SSR to identify the error.
Rev. 1.0, 0 7/01, page 2 02 of 372 (A) Start receive error processing Parity error processing Yes No Clear OER, PER, and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun err.
Rev. 1.0, 0 7/01, page 2 03 of 372 14.5 Operation in Clocked Synchronous Mode Figure 14-9 s hows the general f ormat for clocke d synchron ous communication . In clocked synchronou s mode, data is tran smitted or received synchronous with clock pulses.
Rev. 1.0, 0 7/01, page 2 04 of 372 14.5.3 Serial Data Tran smission Figure 14- 10 shows an example of SCI ope ration for trans mission i n clocked sync hronous mode.
Rev. 1.0, 0 7/01, page 2 05 of 372 No Yes Start transmission Read TDRE flag in SSR [1] Write transmit data to TDR No Yes No Yes Read TEND flag in SSR [2] Clear TE bit in SCR3 to 0 TDRE = 1 All data transmitted? TEND = 1 [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Rev. 1.0, 0 7/01, page 2 06 of 372 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14-12 s hows an example of SCI operati on for recepti on in clocked sy nchronous mode.
Rev. 1.0, 0 7/01, page 2 07 of 372 Yes No Start reception [1] [4] No Yes Read RDRF flag in SSR [2] [3] Clear RE bit in SCR3 to 0 Error processing (Continued below) Read receive data in RDR Yes No OER .
Rev. 1.0, 0 7/01, page 2 08 of 372 14.5.5 Simultaneous Serial Data Transmission an d Reception Figure 14-14 shows a sample flowchart f or simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous s erial data transmit and receive operations.
Rev. 1.0, 0 7/01, page 2 09 of 372 Yes No Start transmission/reception [3] Error processing [4] Read receive data in RDR Yes No OER = 1 All data received? [1] Read TDRE flag in SSR No Yes TDRE = 1 Wri.
Rev. 1.0, 0 7/01, page 2 10 of 372 14.6 Multiprocessor Communication Function Use of the multip rocessor co mmunication function enables d ata tran sfer between a number of processors s haring communicati on lines by asy nchronous se rial communication us ing the multiprocesso r format, in which a multipro cessor bit is added to the transfer data.
Rev. 1.0, 0 7/01, page 2 11 of 372 Transmitting station Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial transmission line.
Rev. 1.0, 0 7/01, page 2 12 of 372 14.6.1 Multip rocessor Serial Data T ransmiss ion Figure 14-16 sho ws a sample flowchart for multiprocesso r serial d a ta tran sm ission. For an ID transmission cy cle, set the MPBT bit in SSR to 1 before transmissio n.
Rev. 1.0, 0 7/01, page 2 13 of 372 14.6.2 Multiprocessor Serial Data Reception Figure 14-17 sho ws a sample flowchart for multiprocesso r serial d a ta reception . If the MPIE bit in SCR3 is set to 1 , d ata is skipped until data with a 1 multipro cessor bit is sent.
Rev. 1.0, 0 7/01, page 2 14 of 372 Yes No Start reception No Yes [4] Clear RE bit in SCR3 to 0 Error processing [5] Yes No FER+OER = 1 RDRF = 1 All data received? Read MPIE bit in SCR3 [1] [2] Read OE.
Rev. 1.0, 0 7/01, page 2 15 of 372 Start receive error processing Yes No Clear OER, and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing OER = 1 FER = 1 Break? [5].
Rev. 1.0, 0 7/01, page 2 16 of 372 1 frame Start bit Start bit Receive data (ID1) Receive data (Data1) MPB MPB Stop bit Stop bit Mark state (idle state) 1 frame 0 1D 0 D 1 D 7 1 1 1 1 0D 0 D 1 D 7 ID1.
Rev. 1.0, 0 7/01, page 2 17 of 372 14.7 Interrupts SCI creates the following six interrupt requests: transmission end, transmit data empty , receive data full, and receive errors ( overrun error , framing error, a nd parity error) . Table 14-6 shows the interrupt sources.
Rev. 1.0, 0 7/01, page 2 18 of 372 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing erro r detection is performed, a break can be detect ed by reading the RxD pi n value directly. In a break, the input from the R xD pin becomes all 0s , setting the F ER flag, and poss ibly the PER flag.
Rev. 1.0, 0 7/01, page 2 19 of 372 14.8.4 Receive Data Sampling Timing and Reception Margin in A synchronou s Mode In asynchron ous mode, the SC I operates on a bas ic clock with a fre quency of 16 t imes the transfe r rate.
Rev. 1.0, 0 7/01, page 2 20 of 372.
Rev. 1.0, 0 7/01, page 2 21 of 372 Section 15 I 2 C Bus Interface 2 (IIC2) The I 2 C bus interface conform s to and provides a subset of th e Philips I 2 C bus (inter-IC bus ) interface functions. The register con figuration that controls the I 2 C bus differs pa rtly from the Philips con f iguration , ho wever.
Rev. 1.0, 0 7/01, page 2 22 of 372 SCL ICCR1 Transfer clock generation circuit Address comparator Interrupt generator Interrupt request Bus state decision circuit Arbitration decision circuit Noise ca.
Rev. 1.0, 0 7/01, page 2 23 of 372 Vcc Vcc SCL in out SCL SDA in out SDA SCL (Master) (Slave 1) (Slave 2) SDA SCL in out SCL SDA in out SDA SCL in out SCL SDA in out SDA Figure 15-2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15-1 s ummarizes the input /output pi ns used by t he I 2 C bus inter face.
Rev. 1.0, 0 7/01, page 2 24 of 372 • I 2 C bus receive data register (ICDRR) • I 2 C bus s hift register (ICDR S) 15.3.1 I 2 C Bus Control Register 1 (ICCR1) ICCR1 is an 8-bit readable/writable re.
Rev. 1.0, 0 7/01, page 2 25 of 372 Table 15-2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock φ =5 MH z φ =8 MHz φ =10 MHz φ =16 MHz 0 φ /28 179 kH z 286 kHz 357 kH z 571 kHz 0 1 φ /40 125 kHz 200 kHz 250 kH z 400 kHz 0 φ /48 104 kH z 167 kHz 208 kH z 333 kHz 0 1 1 φ /64 78.
Rev. 1.0, 0 7/01, page 2 26 of 372 Bit Bit Name Initial Value R/W Description 6 SCP 1 W Start/Stop Issue C ondition Disabl e The SCP bit contro ls the is sue of start/ stop condit ions in master mode. To issue a start condition, write 1 in BBSY an d 0 in SCP.
Rev. 1.0, 0 7/01, page 2 27 of 372 15.3.3 I 2 C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, perfor ms master mode wait co ntrol, and s elects the trans fer bit count.
Rev. 1.0, 0 7/01, page 2 28 of 372 Bit Bit Name Initial Value R/W Description 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits specify th e number of bits to be tr ansferred ne xt. When read, the remaining number of tran sfer bits i s indicat ed.
Rev. 1.0, 0 7/01, page 2 29 of 372 Bit Bit Name Initial Value R/W Description 5 RIE 0 R/W Receive Interru pt Enable This bit ena bles or di sables the r eceive dat a full interr upt request (RXI) and .
Rev. 1.0, 0 7/01, page 2 30 of 372 Bit Bit Name Initial Value R/W Description 0 ACKBT 0 R/W Transmit Acknowledge In receive m ode, this b it specifies the bit to b e sent at the acknowle dge tim ing . 0: 0 is sent at the ack nowledge tim ing. 1: 1 is sent at the ack nowledge tim ing.
Rev. 1.0, 0 7/01, page 2 31 of 372 Bit Bit Name Initial Value R/W Description 5 RDRF 0 R/W Receive Data Register Full [Setting cond ition] • When a re ceive data is tran sferred from ICDRS to ICDRR .
Rev. 1.0, 0 7/01, page 2 32 of 372 Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recogni tion Flag In slave re ceive mod e, this flag is set to 1 if the first frame following a start conditi on matches bi ts SVA6 to SVA0 in SAR.
Rev. 1.0, 0 7/01, page 2 33 of 372 15.3.7 I 2 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. W hen ICDRT detects the space in the shift register (ICDRS), it tran sfers th e transmit data which is written in ICDRT to ICDRS and starts transferring d ata.
Rev. 1.0, 0 7/01, page 2 34 of 372 15.4 Operation The I 2 C bus interface can co mmunicate either in I 2 C bus mode or cl ocked sync hronous seri al mode by sett ing FS in S AR. 15.4.1 I 2 C Bus Format Figure 15-3 s hows the I 2 C bus formats. Figure 15 -4 shows the I 2 C bus timing.
Rev. 1.0, 0 7/01, page 2 35 of 372 P: Stop conditio n. The master device drives SDA fro m low to high while SCL is hig h . 15.4.2 Master T ransmit Operati on In master transmit m ode, the master device ou tputs th e tran smit clock and transmit d ata, and the slave device returns an acknowledge signal.
Rev. 1.0, 0 7/01, page 2 36 of 372 TDRE SCL (Master output) SDA (Master output) SDA (Slave output) TEND [5] Write data to ICDRT (third byte) ICDRT ICDRS [2] Instruction of start condition issuance [3].
Rev. 1.0, 0 7/01, page 2 37 of 372 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from t h e slave device, and returns an ack nowledge signal. For master receive mode operation timing, refer t o figures 15-7 and 1 5-8.
Rev. 1.0, 0 7/01, page 2 38 of 372 TDRE TEND ICDRS ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) [3] Read ICDRR 1 A 21 34 56 78 9 9 A TRS RDRF SCL (Master output) SDA (M.
Rev. 1.0, 0 7/01, page 2 39 of 372 15.4.4 Slave Tr ansmit Op eration In slave transmit mode, the slave device outp uts the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing , refer to figures 1 5-9 and 15-10 .
Rev. 1.0, 0 7/01, page 2 40 of 372 TDRE TEND ICDRS ICDRR 1 A 21 34 56 78 9 9 A TRS ICDRT SCL (Master output) Slave receive mode Slave transmit mode SDA (Master output) SDA (Slave output) SCL (Slave ou.
Rev. 1.0, 0 7/01, page 2 41 of 372 TDRE Data n TEND ICDRS ICDRR 1 9 23456789 TRS ICDRT A SCL (Master output) SDA (Master output) SDA (Slave output) SCL (Slave output) Bit 7 Slave transmit mode Slave r.
Rev. 1.0, 0 7/01, page 2 42 of 372 4. The last byte dat a is read by rea ding ICDR R. ICDRS ICDRR 12 1 34 56 78 9 9 A A RDRF Data 1 Data 2 Data 1 SCL (Master output) SDA (Master output) SDA (Slave out.
Rev. 1.0, 0 7/01, page 2 43 of 372 15.4.6 Clocked Syn chronous Serial Format This module can be operated with t h e clocked synchronous s erial format, by setting the FS bit in SAR to 1. Wh en the M ST bit in ICCR1 is 1, the tr ansfer c lock ou tpu t from SCL is sele c ted.
Rev. 1.0, 0 7/01, page 2 44 of 372 12 78 1 7 8 1 SCL TRS Bit 0 Data 1 Data 1 Data 2 Data 3 Data 2 Data 3 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 SDA (Output) TDRE ICDRT ICDRS User processing [3] Wri.
Rev. 1.0, 0 7/01, page 2 45 of 372 12 78 1 7 81 2 SCL MST TRS RDRF ICDRS ICDRR SDA (Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 15-15 Receive Mode Operation Timing 15.
Rev. 1.0, 0 7/01, page 2 46 of 372 15.4.8 Example of Us e Flowcharts in respective modes that use the I 2 C bus interface are shown in figures 15-17 t o 15-20. BBSY=0 ? No TEND=1 ? No Yes Start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] Initialize Set MST and TRS in ICCR1 to 1.
Rev. 1.0, 0 7/01, page 2 47 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Mater receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-re.
Rev. 1.0, 0 7/01, page 2 48 of 372 TDRE=1 ? Yes Yes No Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR Last byte? Write transmit data in ICDRT Read TEND in ICSR Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [1] Clear the AAS flag.
Rev. 1.0, 0 7/01, page 2 49 of 372 No Yes RDRF=1 ? No Yes RDRF=1 ? Last receive - 1? Slave receive mode Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR Read ICDRR Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR Read ICDRR End No Yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] Clear the AAS flag.
Rev. 1.0, 0 7/01, page 2 50 of 372 15.5 Interrupt Requ est There are six interrupt requests in this mod ule; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration los t/overrun. Table 15 -3 shows the contents of each interrupt request.
Rev. 1.0, 0 7/01, page 2 51 of 372 15.6 Bit Synchronous Circuit In master mode,th is m o dule has a possib ility that high lev e l p eriod may be short in th e two states described below.
Rev. 1.0, 0 7/01, page 2 52 of 372.
Rev. 1.0, 0 7/01, page 2 53 of 372 Section 16 A/D Converter This LSI include s a su ccessive approx imation type 1 0-bit A/D converter that allows u p to eight analog input chan nels to be select ed. The block di agram of the A/D con verter is shown in figure 16-1.
Rev. 1.0, 0 7/01, page 2 54 of 372 Module data bus Control circuit Internal data bus 10-bit D/A Comparator + Sample-and- hold circuit ADI interrupt Bus interface Successive approximations register Ana.
Rev. 1.0, 0 7/01, page 2 55 of 372 16.2 Input/Output Pins Table 16-1 summari zes the input pi ns used by t he A/D converter. T he 18 analog input pins are divided into two groups ; analog inpu t pins 0 t o 3 (AN0 to AN3) c omprising gro up 0, analo g input pins 4 to 7 (AN4 t o AN7) comprisi ng group 1.
Rev. 1.0, 0 7/01, page 2 56 of 372 16.3 Register Description The A/D converter has the following re gisters. F or details on re gister addresse s and regist er states during each processing, refe r to section 19, Internal I/O Registers.
Rev. 1.0, 0 7/01, page 2 57 of 372 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consi sts of the contr ol bits and convers ion end s tatus bits of t he A/D converter.
Rev. 1.0, 0 7/01, page 2 58 of 372 Bit Bit Name Initial Value R/W Description 2 1 0 CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Sel ect 2 to 0 Select analo g input cha nnels.
Rev. 1.0, 0 7/01, page 2 59 of 372 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes ; single mode an d scan mode. When cha nging the o perating mode or anal og input channel, in order to preven t incorrect operation, first clear th e bit ADST in ADCSR to 0.
Rev. 1.0, 0 7/01, page 2 60 of 372 16.4.3 Input Sampling and A/D Conv ersion Time The A/D converter has a b uilt-in sample-and-hold circuit. Th e A/D converter samples the analog input when t he A/D conversion s tart delay time (t D ) has passed after th e ADST bit is set to 1, then starts convers ion.
Rev. 1.0, 0 7/01, page 2 61 of 372 Table 16- 3 A /D Co nversion Ti me ( Sing le Mode) CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max A/D conver sion start de lay time t D 6— 9 4 — 5 Input sampling tim e t SPL — 3 1— — 1 5— A/D conver sion time t CO NV 131 — 134 69 — 70 Note: All values repre sent the num ber of state s.
Rev. 1.0, 0 7/01, page 2 62 of 372 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accurac y definitions are given below. • Resolution The number of A/ D converter digi tal output c odes • Quantization error The deviation i nherent in the A/D co nverter, given by 1/2 LSB (s ee figure 16-4) .
Rev. 1.0, 0 7/01, page 2 63 of 372 FS Digital output Ideal A/D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A/D conversion characteristic Full-scale error Figure 16-5 A/D Conversion Accuracy Definitions (2) 16.
Rev. 1.0, 0 7/01, page 2 64 of 372 20 pF 10 k C in = 15 pF Sensor output impedance up to 5 k This LSI Low-pass filter C to 0.1 F Sensor input A/D conv er ter equivalent circuit Figure 16-6 Analog Inpu.
Rev. 1.0, 0 7/01, page 2 65 of 372 Section 17 Power-on Reset and Low-Vo ltage Detection Circuits (Optional) This LSI incl udes a power-on res et circuit and l ow-voltage detecti on circuit.
Rev. 1.0, 0 7/01, page 2 66 of 372 PSS : L VDCR : L VDSR : Prescaler S Low-v oltage-detection control register Low-v oltage-detection status register Legend CK R PSS R S Q OV F Vreset Vint L VDCR L VD.
Rev. 1.0, 0 7/01, page 2 67 of 372 Bit Bit Name Initial Value R/W Description 7 LVDE 0 R/W LVD Enable 0: The low-voltage dete cti on cir c uit is not used. (In standb y mode) 1: The low-voltage dete cti on cir c uit is used. 6 to 4 − 1 − Reserved These bits ar e always read as 1, and cannot be modifie d.
Rev. 1.0, 0 7/01, page 2 68 of 372 17.2.2 Low-Voltage-Detection S tatus Regis ter (LVDSR) LVDSR is an 8-bi t readable/wri table register whic h indicates whet her or not the power-supply voltage has bec ome lower or hi gher than the respective specified values.
Rev. 1.0, 0 7/01, page 2 69 of 372 V CC V SS V SS OV F PSS-reset signal Internal reset signal PSS counter star ts Reset released 131,072 cycles t PWON Figure 17-2 Op erational Tim ing of the Power-on Res et Circuit 17.3.2 Low-Voltage Detection Ci rcuit Reset by Low Voltage Detect (LVDR): Figure 17-3 s hows the timing of the LVDR function.
Rev. 1.0, 0 7/01, page 2 70 of 372 V CC Vreset V SS OV F PSS-reset signal Internal reset signal PSS counter star ts Reset released 131,072 cycles Figure 17-3 Op erational Tim ing of LVDR Interrupt by Low Voltage Detect (LVDI) : Figure 17-4 s hows the timing of LVDI functions .
Rev. 1.0, 0 7/01, page 2 71 of 372 V CC Vint(D) Vint(U) V SS L VDDF L VDUE L VDUF IRQ0 interrupt generated IRQ0 interr upt generated L VDDE Figure 17-4 Op erational T iming of LVDI Procedures for Oper.
Rev. 1.0, 0 7/01, page 2 72 of 372 L VDRE L VDDE L VDUE t L VDON t L VDOFF L VDE Figure 17-5 Timing for Operation/Release of the L ow-Voltage Detection Circuit.
Rev. 1.0, 0 7/01, page 2 73 of 372 Section 18 Power Supply Circuit This LSI incorporates an internal power su pply step-down circuit. Use of this circuit enables the internal power su pply to be fix ed at a const ant level of appr oximately 3.0 V, regardless of the voltage of t he power supply con nected to the exte rnal V CC pin.
Rev. 1.0, 0 7/01, page 2 74 of 372 18.2 When Not Using the Internal Power Supply Step-Down Circuit When the internal p ower supply step-dow n circuit is not us ed, connect the ext ernal power suppl y to the V CL pin and V CC pin, as s hown in figure 18 -2.
Rev. 1.0, 0 7/01, page 2 75 of 372 Section 19 Internal I/O Registers 19.1 Register Addresses Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State —— — H'F000 .
Rev. 1.0, 0 7/01, page 2 76 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State Flash memory p ower control re gister FLPWCR 8 H'FF92 ROM 8 2 Erase blo ck r.
Rev. 1.0, 0 7/01, page 2 77 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State Timer mode re gister WD TMWD 8 H'FFC2 WDT * 3 82 —— — H'FFC3 —.
Rev. 1.0, 0 7/01, page 2 78 of 372 Register Name Abbre- viation Bit No Address Module Name Data Bus Width Access State —— — H'FFE6, H'FFE7 I/O port —— Port control reg ister 5 PCR5.
Rev. 1.0, 0 7/01, page 2 79 of 372 19.2 Register Bits Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me — ———————— — LVDCR LV DE — — — LVDS EL LVDRE .
Rev. 1.0, 0 7/01, page 2 80 of 372 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me TCRV0 CMI EB CMI EA O VIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V TCSRV CMFB CFMA OVF — OS3 O.
Rev. 1.0, 0 7/01, page 2 81 of 372 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Na me — ———————— — PUCR1 P UCR17 PUCR16 PUCR15 PUCR14 — PUCR12 PUCR11 PUCR.
Rev. 1.0, 0 7/01, page 2 82 of 372 19.3 Registers States in Each Operating Mode Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module LVDCR Initialize d −−−−− LVDC LVDSR Initi.
Rev. 1.0, 0 7/01, page 2 83 of 372 Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module TMA I nitialized −−−−− Timer A TCA Initi alized −−−−− SMR Init ialized −.
Rev. 1.0, 0 7/01, page 2 84 of 372 Register Name Reset Active Sl eep Subacti ve Subsleep Standby Module PCR5 Initialize d −−−−− I/O port PCR7 Initialize d −−−−− PCR8 Initialize d .
Rev. 1.0, 0 7/01, page 2 85 of 372 Section 20 Electrical Chara cteristics 20.1 Absolute Maximum Ratings Table 20- 1 A bso lute Maxim um Ratings Item Symbol Value Unit Note Power suppl y voltage V CC –0.3 to +7. 0 V * Analog power supply v oltage AV CC –0.
Rev. 1.0, 0 7/01, page 2 86 of 372 Power Supply Volta g e and Operating Frequency Range 10.0 1.0 16.0 3.0 4.0 5.5 V CC (V) ø (MHz) 16.384 3.0 4.0 5.5 V CC (V) ø SUB (kHz) 8.192 4.096 1250 78.125 2000 3.0 4.0 5.5 V CC (V) ø (kHz) • A V CC = 3.3 to 5.
Rev. 1.0, 0 7/01, page 2 87 of 372 20.2.2 DC Characteristics Table 20-2 DC Characteristics (1) V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated.
Rev. 1.0, 0 7/01, page 2 88 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Output high voltage V OH P10 to P12, P14 to P17, P20 to P22, V CC = 4 .0 to 5 .5 V –I OH = 1 .5 mA V CC – 1.0 — — V P50 to P55, P74 to P76, P80 to P87, –I OH = 0 .
Rev. 1.0, 0 7/01, page 2 89 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Input/ output leakage current | I IL |O S C 1 , NM I , WKP0 to WKP 5 , IRQ0 to IRQ3 , ADTRG , TRGV, TMRIV, TMCIV, FTCI, FT IOA to FTIOD, RXD , SCK3, SCL , SDA V IN = 0.
Rev. 1.0, 0 7/01, page 2 90 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Sleep mode current I SLEEP1 V CC Sleep mode 1 V CC = 5.0 V, f OSC = 16 MHz —T B D T B D m A * consump- tion Sleep mode 1 V CC = 3.0 V, f OSC = 10 MH z —T B D — * Reference value I SLEEP2 V CC Sleep mode 2 V CC = 5.
Rev. 1.0, 0 7/01, page 2 91 of 372 Note: * Pin states dur ing curr ent consumpti on measureme nt are given below (e xcluding current in the pull- up MOS transist ors and output b uffers).
Rev. 1.0, 0 7/01, page 2 92 of 372 Table 20-2 DC Characteristics (2) V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicab le Values Item Symbol Pins Test Condit ion Min Typ Max Unit Allowabl e output low current (per pin) I OL Output pins except port 8, SCL and SDA V CC = 4.
Rev. 1.0, 0 7/01, page 2 93 of 372 20.2.3 AC Characteristics Table 20-3 AC Characteristics V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e incicated. Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure Syste m clo ck oscilla tion f OSC OSC 1 , OSC 2 V CC = 4.
Rev. 1.0, 0 7/01, page 2 94 of 372 Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure RES pin l ow width t REL RES A t power-on and in modes other than those below .
Rev. 1.0, 0 7/01, page 2 95 of 372 Table 20-4 I 2 C Bus Interface Timing V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated.
Rev. 1.0, 0 7/01, page 2 96 of 372 Table 20-5 Serial Communication Interface (SCI) Timing V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated.
Rev. 1.0, 0 7/01, page 2 97 of 372 20.2.4 A/D Converter Characteristic s Table 20-6 A/D Converter Characteristics V CC = 3.0 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Analog power supply voltage AV CC AV CC 3.
Rev. 1.0, 0 7/01, page 2 98 of 372 Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion t ime (single mode) AV CC = 4 .0 to 5.5 V 134 — — t cyc Nonlinearit y error — — ±3.5 LS B Offset error — — ±3.
Rev. 1.0, 0 7/01, page 2 99 of 372 20.2.6 Flash Me mory Characteristics Table 20-8 Flash Memory Characteristi cs V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwis e indicated.
Rev. 1.0, 0 7/01, page 3 00 of 372 Test Values Item Sym bol Conditi on Min Typ Max Unit Erasing Wait time after S WE bit se tting * 1 x 1 ——µ s Wait time af ter ESU bit se tting * 1 y 100 — —.
Rev. 1.0, 0 7/01, page 3 01 of 372 20.2.7 Power-Supply- Voltage Det ect io n Circuit Characterist ics (Optional) Table 20-9 Po wer-Supply-Volt a ge Detection Circuit Cha racteristics V CC = 3.0 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwi se specified.
Rev. 1.0, 0 7/01, page 3 02 of 372 20.3 Electrical Characteristics ( Mask ROM Version) 20.3.1 Power Supply Volta g e and Operating Ra nges Power Supply Volta g e and Oscillatio n Frequency Ra nge 10.0 2.0 16.0 2.7 4.0 5.5 V CC (V) ø OSC (MHz) 32.768 2.
Rev. 1.0, 0 7/01, page 3 03 of 372 Analog Power Supply Vo lt a ge and A/D Converter Accura cy Guarantee Range 10.0 2.0 16.0 3.0 4.0 5.5 A V CC (V) ø (MHz) • V CC = 2.7 to 5.5 V • Active mode • Sleep mode 20.3.2 DC Characteristics Table 20-10 DC Characteristics (1) V CC = 2.
Rev. 1.0, 0 7/01, page 3 04 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Input low voltage V IL RES , NMI , WKP0 to WKP 5 , IRQ0 to IRQ3 , ADTRG ,T MRIV, V CC = 4.0 to 5.5 V –0. 3 — V CC × 0. 2 V TMCIV, FTCI, FTIOA to FTIO D, SCK3, TR GV –0.
Rev. 1.0, 0 7/01, page 3 05 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Note s Output low voltage V OL P10 to P12, P14 to P17, P20 to P22, V CC = 4 .0 to 5 .5 V I OL = 1 .6 mA —— 0 . 6 V P50 to P57, P74 to P76 I OL = 0.
Rev. 1.0, 0 7/01, page 3 06 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Not es Input capaci- tance C in All input pins except power supply pins f = 1 MH z, V IN = 0.0 V, T a = 25°C — — 15. 0 pF Acti ve mode current I OPE1 V CC Active mo de 1 V CC = 5.
Rev. 1.0, 0 7/01, page 3 07 of 372 Values Item Symb ol Applicable Pins Test Condit ion Min Typ Max Unit Notes RAM data retainin g voltage V RAM V CC 2.0 — — V Note: * Pin state s during curr ent consumption m easurement are given bel ow (excludi ng current in the pull- up MOS transist ors and output b uffers).
Rev. 1.0, 0 7/01, page 3 08 of 372 Table 20-10 DC Characteristics (2) V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicab le Values Item Symbol Pins Test Cond ition Min Typ Max Unit Allowabl e output low current (per pin) I OL Output pins except port 8, SCL and SDA V CC = 4 .
Rev. 1.0, 0 7/01, page 3 09 of 372 20.3.3 AC Characteristics Table 20-11 AC Characteristics V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. A pp licab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure Syste m clo ck oscilla tion f OSC OSC 1 , OSC 2 V CC = 4.
Rev. 1.0, 0 7/01, page 3 10 of 372 Applicab le Values Reference Item Symb ol Pins Test Cond ition Min Typ Max Unit Figure RES pin l ow width t REL RES A t power-on and in modes other than those below .
Rev. 1.0, 0 7/01, page 3 11 of 372 Table 20-12 I 2 C Bus Interface Timing V CC = 2.7 V to 5.5 V, V SS = 0. 0 V, T a = –20 t o +75°C, unles s otherwise speci fied.
Rev. 1.0, 0 7/01, page 3 12 of 372 Table 20-13 Serial Commu nication Interface (SCI) Timing A pp licab le Values Reference Item Symbol Pins Test Condition Min Typ Max U nit Figure Input clock As ynchro- nous t Scyc 4— — t cyc Figure 20-5 cycle Clo cked synchronous 6— — Input c lock pulse width t SCKW SCK3 0.
Rev. 1.0, 0 7/01, page 3 13 of 372 20.3.4 A/D Converter Characteristic s Table 20-14 A/D Converter Characteristics V CC = 2.7 to 5. 5 V, V SS = 0.0 V, T a = –2 0 to +75°C , unless otherwis e indicated. Applicable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Analog power supply voltage AV CC AV CC 3.
Rev. 1.0, 0 7/01, page 3 14 of 372 A pp licable Test Values Reference Item Symbol Pins Condition Min Typ Max Unit Figure Conversion t ime (single mode) AV CC = 4 .0 to 5.5 V 134 — — t cyc Nonlinearit y error — — ±3.5 LSB Offset error — — ± 3.
Rev. 1.0, 0 7/01, page 3 15 of 372 20.3.6 Power-Supply- Voltage Det ect io n Circuit Characterist ics (Optional) Table 20-1 6 Power-Supply-Vo ltage Detectio n Circuit Characterist ics V CC = 2.7 to 5.5 V, V SS = 0.0 V, T a = –20 to +75°C, u nless otherwi se specified.
Rev. 1.0, 0 7/01, page 3 16 of 372 V IH V IL t IL to to TMCI FTIOA to FTIOD TMCIV, TMRIV TRGV t IH Figure 20-3 Input Timing SCL V IH V IL t ST AH t BUF P * S * t Sf t Of t Sr t SCL t SDAH t SCLH t SCL.
Rev. 1.0, 0 7/01, page 3 17 of 372 t Scyc t TXD t RXS t RXH V OH V or V IH OH V or V IL OL * * * V OL * SCK3 TXD (transmit data) RXD (receive data) Note: * Output timing reference levels Output high: Output low: Load conditions are shown in figure 20-7.
Rev. 1.0, 0 7/01, page 3 18 of 372.
Rev. 1.0, 0 7/01, page 3 19 of 372 Appendix A Instruction Set A.1 Instruction List Condition Code Symbol Description Rd General destinatio n regist er Rs General source register Rn General register ER.
Rev. 1.0, 0 7/01, page 3 20 of 372 Condition Cod e Notation (cont) Symbol Description ↔ Changed a ccording to execution result * Undetermin ed (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not.
Rev. 1.0, 0 7/01, page 3 21 of 372 Table A.1 Instruct io n Set 1. Data Transfer Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — MOV.
Rev. 1.0, 0 7/01, page 3 22 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — MOV.W Rs, @–ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.
Rev. 1.0, 0 7/01, page 3 23 of 372 2. Arithmetic Instruction s Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — ADD.B #xx:8, Rd ADD.
Rev. 1.0, 0 7/01, page 3 24 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — DEC.L #1, ERd DEC.L #2, ERd DAS.Rd MULXU. B Rs, Rd MULXU.
Rev. 1.0, 0 7/01, page 3 25 of 372 Mnemonic Operation Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd EXTU.
Rev. 1.0, 0 7/01, page 3 26 of 372 3. Logic Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — AND.B #xx:8, Rd AND.B Rs, Rd AND.
Rev. 1.0, 0 7/01, page 3 27 of 372 4. Shift Instructions Mnemonic Operand Size No. of States * 1 Condition Code IH N Z V C SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.
Rev. 1.0, 0 7/01, page 3 28 of 372 5. Bit-Mani pulation Ins tructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, .
Rev. 1.0, 0 7/01, page 3 29 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@a.
Rev. 1.0, 0 7/01, page 3 30 of 372 6. Branching I nstructions — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — .
Rev. 1.0, 0 7/01, page 3 31 of 372 Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@a.
Rev. 1.0, 0 7/01, page 3 32 of 372 7. System C ontrol Inst ructions Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ER.
Rev. 1.0, 0 7/01, page 3 33 of 372 8. Block Tra nsfer Instructi ons Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) No. of States * 1 Condition Code IH N Z V C #xx Rn @ERn @(d, ERn) @–ERn/@ERn+ @aa @(d, PC) @@aa — EEPMOV. B EEPMOV.
Rev. 1.0, 0 7/01, page 3 34 of 372 A.2 Operation Cod e Map Table A.2 O pera tion Code Map (1 ) AH AL 0123 4567 89A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F NOP BRA MULXU BSET BRN DIVXU BNOT STC BHI MULXU BCLR LDC BLS DIVXU BTST ORC OR.B BCC RTS OR XORC XOR.
Rev. 1.0, 0 7/01, page 3 35 of 372 Table A.2 O pera tion Code Map (2 ) AH AL BH 0123 4567 89 A B C D E F 01 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 79 7A MOV INC ADDS DAA DEC SUBS DAS BRA MOV MOV BHI CMP .
Rev. 1.0, 0 7/01, page 3 36 of 372 Table A.2 O pera tion Code Map (3 ) AH ALBH BLCH CL 0123 4567 89A B C D E F 01406 01C05 01D05 01F06 7Cr06 7Cr07 7Dr06 7Dr07 7Eaa6 7Eaa7 7Faa6 7Faa7 MULXS BSET BSET B.
Rev. 1.0, 0 7/01, page 3 37 of 372 A.3 Number of Execution States The status of execution fo r each instruction of the H8/300H CPU and the met hod of calculating the number of states required fo r instructio n execution are show n below.
Rev. 1.0, 0 7/01, page 3 38 of 372 Table A.3 Number of Cycles in Each In struction Execution Status Access Location (Instruction Cycle) On-Chip M emory On-Chip Peripheral Module Instructi on fetch S I.
Rev. 1.0, 0 7/01, page 3 39 of 372 Table A.4 Number of Cycles in Each Instruction Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N ADD ADD.B #xx:8, Rd ADD.
Rev. 1.0, 0 7/01, page 3 40 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N Bcc BLT d:8 BGT d: .
Rev. 1.0, 0 7/01, page 3 41 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N BIOR BIOR #x x:8, R.
Rev. 1.0, 0 7/01, page 3 42 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N BTST BTST # xx:3, R.
Rev. 1.0, 0 7/01, page 3 43 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N INC INC.
Rev. 1.0, 0 7/01, page 3 44 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N MOV MOV.B R s, @aa: 16 MOV.B R s, @aa: 24 MOV.W #xx: 16, Rd MOV.W R s, Rd MOV.
Rev. 1.0, 0 7/01, page 3 45 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N MULXS MUL XS. B Rs, Rd MULXS.W Rs, ERd 2 2 12 20 MULXU MULXU.B Rs, Rd MULXU.
Rev. 1.0, 0 7/01, page 3 46 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd 1 1 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.
Rev. 1.0, 0 7/01, page 3 47 of 372 Inst ructio n Mnemon ic Inst ruct ion Fetc h I Branch Addr. Read J Stack Operati on K Byte Data Access L Word Data Access M Internal Operati on N SUBX SUBX #xx:8, Rd SUBX. Rs, Rd 1 1 TRAPA TRAPA #xx:2 2 1 2 4 XOR XOR.
Rev. 1.0, 0 7/01, page 3 48 of 372 A.4 Combinations of Instructions an d Addressing Mode s Table A.5 Co mbinations o f Instructions a nd Addressing Mo des Addressing Mode MO V POP , PUSH MO VFPE, MO V.
Rev. 1.0, 0 7/01, page 3 49 of 372 Appendix B I/O Port Block Diagrams B.1 I/O Port Block RES goes low in a reset, and SBY goes low in a rese t and in standby m ode. PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register TRGV Internal data bus Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 50 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 51 of 372 PDR PUCR PCR PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 52 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus TMOW Timer A Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 53 of 372 PDR PMR PCR PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus TxD SCI3 Legend Figure B.
Rev. 1.0, 0 7/01, page 3 54 of 372 PDR PCR PDR: Port data register PCR: Port control register RE Internal data bus RxD SCI3 Legend Figure B.6 Port 2 Block Diagram (P21).
Rev. 1.0, 0 7/01, page 3 55 of 372 PDR PCR PDR: Port data register PCR: Port control register SCKIE Internal data bus SCKI SCI3 SCK OE SCK O Legend Figure B.
Rev. 1.0, 0 7/01, page 3 56 of 372 PDR PCR ICE SD AO/SCLO SD AI/SCLI IIC2 PDR: Port data register PCR: Port control register Internal data bus Legend Figure B.
Rev. 1.0, 0 7/01, page 3 57 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 58 of 372 PDR PUCR PMR PCR PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Internal data bus Pull-up MOS Legend Figure B.
Rev. 1.0, 0 7/01, page 3 59 of 372 PDR PCR OS3 OS2 OS1 OS0 TMO V PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.
Rev. 1.0, 0 7/01, page 3 60 of 372 PDR PCR TMCIV PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.12 Port 7 Block Diagram (P75).
Rev. 1.0, 0 7/01, page 3 61 of 372 PDR PCR TMRIV PDR: Port data register PCR: Port control register Internal data bus Timer V Legend Figure B.13 Port 7 Block Diagram (P74).
Rev. 1.0, 0 7/01, page 3 62 of 372 PDR PCR PDR: Port data register PCR: Port control register Internal data bus Legend Figure B.14 Port 8 Block Diagram (P87 to P85).
Rev. 1.0, 0 7/01, page 3 63 of 372 PDR PCR PDR: Port data register PCR: Port control register Internal data bus FTIOA FTIOB FTIOC FTIOD Timer W Output control signals A to D Legend Figure B.
Rev. 1.0, 0 7/01, page 3 64 of 372 PDR PCR FTCI PDR: Port data register PCR: Port control register Internal data bus Timer W Legend Figure B.16 Port 8 Block Diagram (P80).
Rev. 1.0, 0 7/01, page 3 65 of 372 DEC V IN CH3 to CH0 A/D conv er ter Internal data bus Figure B.17 Port B Block Di agram (PB7 to PB0) B.2 Port States in Each Operating State Port Reset Sleep Subslee.
Rev. 1.0, 0 7/01, page 3 66 of 372 Appendix C Product Code Lineup Package (Hitachi Package Code) Product Type QFP-64 (FP-64A) LQFP-64 (FP-64E) LQFP-48 (FP-48F) Flash memory version Product with POR &a.
Rev. 1.0, 0 7/01, page 3 67 of 372 Appendix D Package Dimensions The package dimensi ons that are s hows in the Hitachi S emiconductor P ackages Data Book has priority. Hitachi Code JEDEC EIAJ Mass (reference value) FP-64E Conforms 0.4 g Unit: mm *Dimension including the plating thickness Base material dimension M 12.
Rev. 1.0, 0 7/01, page 3 68 of 372 Hitachi Code JEDEC EIAJ Mass (reference value) FP-64A Conforms 1.2 g Unit: mm *Dimension including the plating thickness Base material dimension 0.10 0.15 M 17.2 ± 0.3 48 33 49 64 1 16 32 17 17.2 ± 0.3 0.35 ± 0.06 0.
Rev. 1.0, 0 7/01, page 3 69 of 372 Index A/D Converter ........................................ 253 sample-and-hold circu it ...................... 260 Scan Mode .......................................... 259 Single Mode ..............................
Rev. 1.0, 0 7/01, page 3 70 of 372 large curren t ports ....................................... 1 Memory Map .............................................. 8 Module Standby Function......................... 79 On-Board Programm in g Modes.............
Rev. 1.0, 0 7/01, page 3 71 of 372 TCORA ....................... 139, 276, 279, 281 TCORB ....................... 139, 276, 279, 2 81 TCRV0........................ 140, 275, 279, 281 TCRV1........................ 143, 276, 279, 281 TCRW ..............
Rev. 1.0, 0 7/01, page 3 72 of 372.
H8/3694 Series Hardware Manual Publication Date: 1 st Edition, Ju ly 2001 Published by: Customer Service Divis ion Semiconductor & Integrated Ci rcuits Hitachi, Ltd. Edited by: Technical Documentation Grou p Hitachi Kodaira S emiconductor Co., Lt d.
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