Instruction/ maintenance manual of the product STK14C88-3 Cypress Semiconductor
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STK14C88-3 256 Kbit (32K x 8) AutoS tore nvSRAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-50592 Rev .
STK14C88-3 Document Number: 001-50592 Rev . ** Page 2 of 17 Pin Configurations Figure 1. Pin Diagram - 32-Pin SOIC/32- Pin PDIP T able 1. Pin Definitions - 3 2-Pin SOIC/32-Pin PD IP Pin Name Alt IO T ype Description A 0 –A 14 Input Address In pu ts.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 3 of 17 Device Operation The STK14C88-3 nvSRAM is made up of two functional compo - nents paired in the same physical cell. These ar e an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 4 of 17 Hardware STORE (HSB ) Operation The STK14C88-3 provide s the HSB pin for controll ing and acknowledging the STORE operations. The HSB pin is used to request a hardware ST ORE cycle. When the HSB pin is driven LOW , the STK14C88-3 conditionally initiates a STORE operation after t DELA Y .
STK14C88-3 Document Number: 001-50592 Rev . ** Page 5 of 17 Sof tware RECALL Data is transferred from the nonvola tile memory to the SRAM b y a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 6 of 17 Best Practices nvSRAM products have been used e ffectively for over 15 years. While ease-of-use is o ne of the product’s main system value.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 7 of 17 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user g uidelines are not tested. S torage T emperature ............. ... .. ... ............ –65 ° C to +150 ° C T emperature under bias .
STK14C88-3 Document Number: 001-50592 Rev . ** Page 8 of 17 Dat a Retention and Endurance Parameter Description Min Unit DA T A R Data Retention 100 Y ears NV C Nonvolatile STORE Operations 1,000 K Cap acit ance In the following table, the capacitance parameters are listed.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 9 of 17 AC Switching Characteristics SRAM Read Cycle Parameter Description 35 ns 45 ns Unit Min Max Min Max Cypress Parameter Alt t ACE t ELQV Chip .
STK14C88-3 Document Number: 001-50592 Rev . ** Page 10 of 17 T able 3. SRAM Write Cycle Parameter Description 35 n s 45 ns Unit Min Max Min Max Cypress Parameter Alt t WC t AVAV Write Cycle T ime 35 4.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 1 1 of 17 AutoS tore or Power Up RECALL Parameter Alt Description STK14C88-3 Unit Min Max t HRECALL [15] t RESTORE Power up RECALL Duration 550 μ s.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 12 of 17 Sof tware Controlled STORE/RECALL Cycle The software controlled ST ORE/RECALL cycle follows.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 13 of 17 Hardware STORE Cycle Parameter Alt Description STK14C88-3 Unit Min Max t PHSB t HLHX Hardware STORE Pulse Width 15 ns t DHSB [16, 20] t RECOVER, t HHQX Hardware STORE High to Inhibit Off 700 ns t HLBL Hardware STORE Low to ST ORE Bus y 300 ns Switching W aveforms Figure 13.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 14 of 17 Ordering Information Spe e d (ns) Ordering Code Package Diagra m Package T ype Operating Range 35 STK14C88-3NF35TR 51-85127 32-pin SOIC Co .
STK14C88-3 Document Number: 001-50592 Rev . ** Page 15 of 17 Package Diagrams Figure 14. 32-Pin (300 Mil) SOIC (51-85127) 51-85058 *A PIN 1 ID SEATING PLANE 1 16 17 32 DIMENSIONS IN INCHES[MM] MIN. MAX. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.
STK14C88-3 Document Number: 001-50592 Rev . ** Page 16 of 17 Figure 15. 32-Pin (60 0 Mil) PDIP (51-85018) Package Diagrams (continued) .
Document Number: 001-50592 Rev . ** Revised January 29, 20 09 Page 17 of 17 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this docum ent may be the trade marks of t heir respe ctive holders.
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