Instruction/ maintenance manual of the product STK11C68-5 Cypress Semiconductor
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STK1 1C68-5 (SMD5962-92324) 64 Kbit (8K x 8) Sof t S tore nvSRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-510 01 Rev .
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 2 of 15 Pinout s Pin Definitions Pin Name Alt I/O T ype Description A 0 –A 12 Input Address Inputs . Used to select one of the 8,192 bytes of the nvSRAM. DQ 0 -DQ 7 Input/Output Bidirectional Dat a I/O Lines .
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 3 of 15 Device Operation The STK1 1C68-5 is a versatile memory chip that provides several modes of operation.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 4 of 15 Low A verage Active Power CMOS technology provides th e STK1 1C 68-5 the benefit of drawing significantly less current when it is cycle d at times longer than 50 ns. Figure 3 and Figure 4 shows the relationship between I CC and Read or Write cycle time.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 5 of 15 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user guid elines are not tested. S torage T emperature ...........................
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 6 of 15 Thermal Resist ance In this table, t he thermal re sistance p arameters are listed.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 7 of 15 Figure 7. SRAM Read Cycle 2: CE and OE Co ntrolled [4] AC Switching Characteristics SRAM Read Cycle Parameter Descriptio n .
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 8 of 15 Figure 9. SRAM Write Cycle 2: CE and OE Controlled [7, 8] SRAM Write Cycle Parameter Description 35 n s 45 ns 55 ns Unit Mi.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 9 of 15 AutoStore INHIBIT or Power Up RECALL Parameter Alt Descriptio n STK1 1C68-5 Unit Min Max t HRECALL [9] t REST ORE Power up RECALL Duration 550 μ s t STORE t HLHZ STORE Cycle Dur ation 10 ms V SWITCH Low V olt age Trigger Level 4.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 10 of 15 Sof tware Controlled ST ORE/RECALL Cycle The software controlled ST ORE/RECALL cycle follows.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 1 1 of 15 S peed: 35 - 35 ns 45 - 45 ns Package: C = Ceramic 28-pin 300 mil DIP (gold le ad finish) Part Numbering Nomen clature ST.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 12 of 15 Ordering Information Spee d ( n s) Ordering Code Package Diagram Package T ype Operating Range 35 STK1 1C68-5C35M 001-5169.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 13 of 15 Package Diagrams Figure 12. 28-Pin (300-Mil) Side Braze DIL (001 -51695) 001-51695 ** [+] Feedback.
STK1 1C68-5 (SMD5962-92324) Document Number: 001-51001 Rev . *A Page 14 of 15 Figure 13. 28-Pad (350-Mil) LCC (001-51696) Package Diagrams (continued) 1. A LL DIM EN SI O N A R E IN IN C HE S AND M ILL IME TE R S [M IN /MA X ] 2. JEDEC 95 O UTLINE# M O-041 3.
Document Number: 001-51001 Rev . *A Revised April 07, 2009 Page 15 of 15 AutoS tore and Qua ntumTr ap are registered tr ademarks of Cypress Se miconductor Corpor ation. All produ cts and comp any names mentio ned in this document may be the trademarks of thei r respective holders.
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