Instruction/ maintenance manual of the product NoBL CY7C1471V25 Cypress Semiconductor
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72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture CY7C1471V25 CY7C1473V25 CY7C1475V25 Cypress Semiconductor Corpora tion • 198 Champion Court • San J ose , CA 95134-1709 • 408-943-2600 Document #: 38-05287 Rev .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 2 of 32 Logic Block Diagram – CY7C1471V25 (2 M x 36) Logic Block Diagram – CY7C1473V25 (4 M x 18) C MODE BW A BW B WE CE1 CE2.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 3 of 32 Logic Block Diagram – CY7C1475V25 (1 M x 72) A0, A1, A C MODE CE1 CE2 CE3 OE READ LOGIC DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 4 of 32 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 5 of 32 Pin Configurations (continued) 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD A A A A A A A NC NC V DDQ V SS.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 6 of 32 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V25 (2M x 36) 234 567 1 A B C D E F G H J .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 7 of 32 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 1 2 34 5 6 78 9 1 1 10 DQg DQg DQg DQg DQg DQg DQg D.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 8 of 32 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inpu ts used to select one of the address lo cations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 9 of 32 Functional Overview The CY7C1471V25, CY7 C1473V25, and CY7C1475 V25 are synchronous fl ow through burst SRAMs designed sp ecifically to eliminate wait states during write-read transitions.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 10 of 32 Because the CY7C1471V 25, CY7C1 473V25, and CY7C1475V25 are common IO devices, data must not be driven into the device while the outputs are active. Th e OE can be deasserted HIGH before pr esenting data to the DQs and DQP X inputs.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 1 1 of 32 T ruth T able The truth table for CY7C1471V25, CY7C1473V25, an d CY7C1475V25 follows.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 12 of 32 T ruth T able for Read/W rite The read-write truth table for CY7C1471V25 follows.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 13 of 32 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1471V25, CY7C1473V2 5, and CY7C1475V25 and incorporate a serial bo undary scan test access p ort (T AP). This port operates in accordance with IEEE S tandard 1 1 49.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 14 of 32 TA P R e g i s t e r s Registers are connected betwe en the TDI and TDO ball s and enable data to be scanned into and out of the SRAM test circuitry . Only one registe r can be selected at a time thro ugh the instruction register .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 15 of 32 signal while in tran sition (metastable state). This does not harm the device, but there i s no guarantee as to the value that is captured. Repeatable results may not be possible.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 16 of 32 T AP AC Switching Characteristics Over the Operatin g Range [10, 1 1] Parameter Description Min Max Unit Clock t TCYC TC.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 17 of 32 1.8V T AP AC T est Conditions Input pulse levels ............... ........ .............. 0.2V to V DDQ – 0.2 Input rise and fall time ........ ... ........ ........... .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 18 of 32 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 3.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 19 of 32 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C 1 2 1 R 3 .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 20 of 32 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 21 of 32 Maximum Ratings Exceeding maximum rati ngs may impair the useful life of the device. These user guid elines are not tested. S torage T emperature .. ................. ....
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 22 of 32 Cap acit ance T ested initially and after any design or proc ess change that may affect these parameters. Parameter Descr iption T est C onditions 100 TQFP Max. 165 FBGA Max.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 23 of 32 Switching Characteristics Over the Operating Range. Timing reference level is 1.25V when V DDQ = 2.5V and is 0.9V when V DDQ = 1.8V . T est conditions shown in (a) of “AC T est Loads and W aveforms” on page 22 unless otherwise note d.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 24 of 32 Switching W aveforms Figure 1 shows read-write timing waveform. [19, 20, 21] Figure 1.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 25 of 32 Figure 2 shows NOP , ST ALL and DESELECT Cycles waveform. [19, 20, 22] Figure 2.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 26 of 32 Figure 3 shows ZZ Mode timing waveform. [23, 24] Figure 3. ZZ Mode Timing Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZR E C AL L I NP U TS ( e xce p t ZZ) DO N’T CA R E I DDZ Z t ZZI t RZ Z I Ou t p ut s ( Q) Hig h- Z DES ELEC T or REA D O nly Notes 23.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 27 of 32 Ordering Information Not all of the speed, package and temper ature ranges are avail able. Please cont act your local sales representative or visit www .cypress.com for actual products of fered.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 28 of 32 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 29 of 32 Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 30 of 32 © Cypress Semico nductor Corpor ation, 2002- 2007. The inform ation contai ned herein is sub ject to change wi thout notice.
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 31 of 32 Document History Page Document Title: CY7C1471V25/CY7C1473V 25/CY7C1475V25, 72-Mb it (2M x 36/4M x 18/1 M x 72) Flow-Throug h SRAM with NoBL™ Architecture Document Number: 38-05287 REV .
CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev . *I Page 32 of 32 *H 472335 See ECN VKN Correcte d the typo in the pin configurati on for 209-Ball FBGA pinout (Corrected the ba ll name for H9 to V SS from V SSQ ). Added the Maximum Rating for Supply V oltage on V DDQ Relative to GND.
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