Instruction/ maintenance manual of the product FLEx18 CY7C0830AV Cypress Semiconductor
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FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchr onous Dual-Port RAM CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06059 Rev .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 2 of 28 Logic Block Diagram [2] A 0L –A 18L CLK L ADS L CNTEN L CNTRST L Tr u e RAM Array 19 Addr .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 3 of 28 Pin Configurations Figure 1. 144-Ball BGA (T op View) CY7C0837A V / CY7C0830A V / C.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 4 of 28 Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (T op View) CY7C0830A V / CY7C0831A V .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 5 of 28 Pin Definitions Lef t Port Right Port Description A 0L –A 18L [2] A 0R –A 18R [2] Address Inputs . ADS L [8] ADS R [8] Address Strobe Input .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 6 of 28 Master Reset The FLEx18 family devices und ergo a complete reset by taking its MRST input LOW . The MRST input can switch asynchro- nously to the clocks.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 7 of 28 Counter Reset Oper ation All unmasked bits of the counter are reset to ‘0.’ All maske d bits remain unchanged. The mirror register is loaded with the valu e of the burst counter .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 8 of 28 Retransmit Retransmit is a feature that allows the Re ad of a block of memory more than once without the nee d to reload the initial a ddress.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 9 of 28 Figure 3. Counter , Mask, and Mirr or Logic Block Diagram [1] From Mask Register Mi.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 10 of 28 IEEE 1 149.1 Serial Boun dary Scan (JT AG) [21] The FLEx18 family devices inco rporate an IEEE 1 149.1 serial boundary scan test access port (T AP).
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 1 1 of 28 Figure 5. Scan Chain for 9 Mb Device T a ble 4. Identification Register Definitions Instruction Field Va l u e D escription Revision Number (31:2 8) 0h Reserved for version number .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 12 of 28 Maximum Ratings Exceeding maximum ratings [23] may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 13 of 28 Figure 6. AC T est Load and Waveforms Switching Characteristics Over the Operating.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 14 of 28 t HCM CNT/MSK Hold T ime 0.6 0.6 NA NA ns t OE Output Enable to Data V alid 4.0 4.4 4.7 5.0 ns t OLZ [28,29] OE to Low Z 0 0 ns t OHZ [28,29] OE to High Z 0 4.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 15 of 28 JT AG Timing and Switching W aveforms Parameter Description CY7C0837A V/CY7C0830A .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 16 of 28 Switching W aveforms Figure 8. Master Re set Figure 9.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 17 of 28 Figure 10. Bank Select Read [34, 35] Figure 1 1 .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 18 of 28 Figure 12. Read-to-Write-to-Read (OE Controlled) [33, 36, 38, 39 ] Figure 13.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 19 of 28 Figure 14. Write with Address Counter Advan ce [39] Figure 15.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 20 of 28 Figure 16. Readback State of Address Counter or Mask Reg ister [43, 44, 45, 46 ] S.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 21 of 28 Figure 17. Lef t_Port (L_Port) Wr ite to Right_Port (R_Port) Read [47, 48, 49] Swi.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 22 of 28 Figure 18. Counter Interrupt and Retran smit [15, 42, 50, 51 , 52, 53] Switching W.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 23 of 28 Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58] T a ble 7.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 24 of 28 Ordering Information 512K × 18 (9M) 3.3V Synchronous CY7C08 33A V Dual-Port SRAM Spee d (MHz) Ordering Code Package Diagram Package T ype Operating Range 133 CY7C0833A V-133BBC 51-85141 144-Ball Grid Ar r ay (13 x 13 x 1.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 25 of 28 32K × 18 (512K) 3.3V Synchronous CY7C0837A V Dual-Port SRAM Spee d (MHz) Ordering Code Package Diagram Package T ype Operating Range 167 C Y 7C08 37A V-167BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 26 of 28 Figure 21. 120-Pin Thin Quad Flatp ack (14 x 14 x 1 .
CY7C0837A V, CY7C0830A V CY7C0831A V, CY7C0832A V CY7C0832BV, CY7C0833A V Document #: 38-06059 Rev . *S Page 27 of 28 Document History Page Document Title: CY7C0837A V/CY7C0 830 A V/CY7C0831A V/CY7C0832A V/CY7C0832BV/CY7C 0833A V, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 Rev .
Document #: 38-06059 Rev . *S Revised March 03, 2009 Page 28 of 28 FLEx18 is a tr ademark of Cypress Semiconductor Co rporation. Al l product and co mpany names me ntioned in this document may be the tradem arks of th ei r respec tive holder s.
An important point after buying a device Cypress Semiconductor FLEx18 CY7C0830AV (or even before the purchase) is to read its user manual. We should do this for several simple reasons:
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If you already are a holder of Cypress Semiconductor FLEx18 CY7C0830AV, but have not read the manual yet, you should do it for the reasons described above. You will learn then if you properly used the available features, and whether you have not made any mistakes, which can shorten the lifetime Cypress Semiconductor FLEx18 CY7C0830AV.
However, one of the most important roles played by the user manual is to help in solving problems with Cypress Semiconductor FLEx18 CY7C0830AV. Almost always you will find there Troubleshooting, which are the most frequently occurring failures and malfunctions of the device Cypress Semiconductor FLEx18 CY7C0830AV along with tips on how to solve them. Even if you fail to solve the problem, the manual will show you a further procedure – contact to the customer service center or the nearest service center
