Instruction/ maintenance manual of the product CY7C1364C Cypress Semiconductor
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CY7C1364C 9-Mbit ( 256K x 32 ) Pi p elined S y nc SRAM Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05689 Rev . *E Revised September 14, 2006 Features • Registered inp uts and outputs for pipelined op er ation • 256K × 32 common I/O architectur e • 3.
CY7C1364C Document #: 38-05689 Rev . *E Page 2 of 18 Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access T i me 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS S tandby Cu.
CY7C1364C Document #: 38-05689 Rev . *E Page 3 of 18 Pin Configuration (continued) A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A NC DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B.
CY7C1364C Document #: 38-05689 Rev . *E Page 4 of 18 Pin Definitions Name TQFP I/O Description A 0 , A 1 , A 37, 36, 32, 33, 34, 35, 43, 44, 45, 46, 47, 48, 49 , 50, 81, 82, 99, 100 Input- Synchronous Address In puts used to select one of the 256K ad dress locations .
CY7C1364C Document #: 38-05689 Rev . *E Page 5 of 18 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled b y the rising edge of the clock.
CY7C1364C Document #: 38-05689 Rev . *E Page 6 of 18 Burst Sequences The CY7C1364C provid es a two-bit wraparound counter , fed by A [1:0] , that implements either an interleaved or linear b urst sequence. The interleaved burst sequ ence is designed specif- ically to support Intel Pentium appli cations.
CY7C1364C Document #: 38-05689 Rev . *E Page 7 of 18 T ruth T able [3, 4, 5, 6, 7, 8] Next Cycle Address Used ZZ CE 3 CE 2 CE 1 ADSP ADSC ADV OE DQ Write Unselected None L X X H X L X X T ri-S tate X .
CY7C1364C Document #: 38-05689 Rev . *E Page 8 of 18 T ruth T able fo r Read/W rite [3, 4] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – DQ A H L HHH L Write By.
CY7C1364C Document #: 38-05689 Rev . *E Page 9 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature .............. ... ... .. ... ........ –65 ° C to +150 ° C Ambient T e mperature with Power Applied .
CY7C1364C Document #: 38-05689 Rev . *E Page 10 of 18 Cap acitance [1 1] Parameter Description T es t Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.
CY7C1364C Document #: 38-05689 Rev . *E Page 1 1 of 18 Switching Characteristics Over the Operating Range [12,13] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Ma x. t POWER V DD (T ypical) to the First Access [14] 1 11 ms Clock t CYC Clock Cycle T ime 4.
CY7C1364C Document #: 38-05689 Rev . *E Page 12 of 18 Switching W aveforms Read Cycle Timing [18] Note: 18. On this diagram, when CE is LOW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW.
CY7C1364C Document #: 38-05689 Rev . *E Page 13 of 18 Write Cycle T iming [18,19] Note: 19. Full width Write can be initiated by either GW LOW ; or by GW HIGH, BWE LOW and BW [A:D] LOW .
CY7C1364C Document #: 38-05689 Rev . *E Page 14 of 18 Read/Write Cycle Timing [18,20 , 21] Notes: 20. The data bus (Q) remains in High- Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed.
CY7C1364C Document #: 38-05689 Rev . *E Page 15 of 18 ZZ Mode T iming [22, 23] Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 23. DQs are in High-Z when exiting ZZ sleep mode.
CY7C1364C Document #: 38-05689 Rev . *E Page 16 of 18 Ordering Information Not all of the spe ed, package and temperature ran ges are available. Please contact your local sales r epresentative or visit www .
CY7C1364C Document #: 38-05689 Rev . *E Page 17 of 18 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1364C Document #: 38-05689 Rev . *E Page 18 of 18 Document History Page Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM Document Number: 38-05689 REV .
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