Instruction/ maintenance manual of the product CY7C1344H Cypress Semiconductor
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2-Mbit (64K x 36) Flow-Through Sync SRAM CY7C1344H Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 001-0021 1 Rev . *B Revised April 26, 2006 Features • 64K x 36 common I/O • 3.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 2 of 15 Selection Guide 133 MHz 100 MHz Unit Maximum Access T i me 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum S tandby Cu rrent 40 40 mA Pin.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 3 of 15 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address In puts used to select one of the 64K a ddress location s. Sampl ed at the rising edge o f the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are s ample d act ive.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 4 of 15 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 5 of 15 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 6 of 15 T ruth T able fo r Read/W rite [2, 3] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte (A, DQP A ) H L HHH L Write.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 7 of 15 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to + 150°C Ambient T e mperature with Power Applied .
CY7C1344H Document #: 001-0021 1 Rev . *B Page 8 of 15 Cap acit ance [9] Parameter Description T est Conditions 100 TQFP Max. Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 9 of 15 Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [12] 11 m s Clock t CYC Clock Cycle T ime 7.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 10 of 15 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 1 1 of 15 Write Cycle T iming [16, 17] Note: 17. Full width Write can be initiate d by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 12 of 15 Read/Write T iming [16, 18, 19] Notes: 18. The data bus (Q) remains in High- Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 13 of 15 ZZ Mode T iming [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descr iptions t able for all possible signal conditions to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 14 of 15 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.
CY7C1344H Document #: 001-0021 1 Rev . *B Page 15 of 15 Document History Page Document Title: CY7C1344H 2-Mbit (64K x 36) Flow-Through Sync SRAM Document Number: 00 1-0021 1 REV .
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