Instruction/ maintenance manual of the product CY7C1333H Cypress Semiconductor
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PRELIMINARY 2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture CY7C1333H Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 001-00209 Rev . ** Revised April 1 1, 2005 Features • Can support up to 133 -MHz bus operations with zero wait st ates.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 2 of 12 Selection Guide CY7C1333H-133 CY7C1333H-100 Unit Maximum Access T i me 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS S tandby Current 40 40 mA Shaded area cont ains advance inf ormation.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 3 of 12 Pin Definitions (100-pin TQFP Package) Name I/O Descriptio n A 0 , A 1 , A Input- Synchronous Address Inputs used to s elect one of the 64K address locations . Sampled at the rising edge of the CLK.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 4 of 12 Functional Overview The CY7C1333H is a synchronous flow-through burst SRAM designed specifically to el iminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 5 of 12 Linear Burst Address T able (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 1.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 6 of 12 T ruth T able for Read/Write [2, 3] Function WE BW A BW B BW C BW D R e a d H XXXX W r i t e N o B y t e s W r i t t e n L HHHH Wri t .
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 7 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied .
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 8 of 12 Cap acit ance [1 1] Parameter Description T est Condition s 100 TQFP Package Unit C IN Input Capacitance T A = 25° C, f = 1 MHz, V DD = 3.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 9 of 12 Hold Times t AH Address Hold after CLK Rise 0.5 0.5 ns t ALH ADV/LD Hold after CLK Rise 0.5 0.5 ns t WEH WE , BW [A:D] Hold after CLK Rise 0.5 0.5 ns t CENH CEN Hold after CLK Rise 0.5 0.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 10 of 12 NOP , ST ALL and DESELECT Cycles [18, 19 , 21 ] ZZ Mode T iming [22, 23] Switching W aveforms (continued) READ Q(A3) 456789 1 0 A3 A4.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 1 1 of 12 © Cypress Semi con duct or Cor po rati on , 20 04 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce.
PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 12 of 12 Document History Page Document Title: CY7C1333H 2-Mbit (64K x 32 ) Fl ow-Through SRAM with NoBL™ A rchitecture Document Numb er: 001-00209 REV .
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