Instruction/ maintenance manual of the product CY7C09089V Cypress Semiconductor
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CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port S t atic RAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06043 Rev .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 2 of 21 Functional Description The CY7C09079V/89V/99V a nd CY7C 09179V/89V/99V are high speed synchrono us CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. T wo ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 3 of 21 Pin Configurations (continued Figure 2. 100-Pin TQFP (T op View0 - CY7C09199V ( 128K x 9), CY7C09189 V (64K x 9),CY7C09.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 4 of 21 Notes 8. This pin is NC for CY7C09179V . 9. This pin is NC for CY7C09179V and CY7C09189V Selection Guide Description CY.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 5 of 21 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. [10] S torage T emperature .............. ....
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 6 of 21 Figure 4. AC T est Loads (Applicable to -6 and -7 only) [13] Figure 5. Load Deratin g Curve Figure 3. AC T est Lo ads (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C= 3 0 pF V TH =1 .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 7 of 21 Notes 14. T est conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production teste d.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 8 of 21 Switching W aveforms (continued) Figure 6. Re ad Cycle fo r Flow-Throug h Output (FT /PIPE = V IL ) [16, 17, 18, 19] Notes 16. OE is asynchronously controlled; all other inp uts are synchrono us to the rising clock edg e.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 9 of 21 Figure 7. Read Cycle for Pipe lined Operat ion (FT /PIPE = V IH ) [16, 17, 18, 19] Figure 8.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 10 of 21 Figure 9. Lef t Port Write to Flow-Through Right Port Read [22, 23, 24, 25] Notes 20. In this depth expansion example, B1 re pr esents B ank #1 and B2 is Bank #2; Each Ba nk consist s of one Cypress dual-port device from this dat asheet.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 1 1 of 21 Figure 10. Pipeline d Read-to-W rite-t o-Read (OE = V IL ) [19, 26, 27, 2 8] Switching W aveforms (continued) t CYC2 .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 12 of 21 Figure 1 1. Pipelined R ead-to-W rite-to-Read (OE Controlled) [19, 26, 27, 28] Notes 26. Output state (HIGH, LOW , or high-impedance) is determined by t he previous cycle con trol signals.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 13 of 21 Figure 12. Flow -Through Read-to-Write-to-Read (OE = V IL ) [17, 19, 26, 27, 28] Figure 13.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 14 of 21 Figure 14. Pipeli ned Read with Addre ss Counter Advance [29] Figure 15. Flow-Th rough Read with Add ress Counter Advance [29] Note 29. CE 0 and OE = V IL ; CE 1 , R/W and CNTRST = V IH .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 15 of 21 Figure 16. W rite with Address Co unter Advance (Flow-Thro ugh or Pipelined O utput s) [30, 31] Notes 30.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 16 of 21 Figure 17. Counter Reset (Pip elined Output s) [19, 26, 32, 33] Notes 32. CE 0 = V IL ; CE 1 = V IH . 33. No dead c ycle exists durin g counter reset. A READ or WRITE cycle ma y be coincidental wit h the counter reset.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 17 of 21 T able 1. Read/Write and Enable Operation [34, 35, 36] Input s Ou tputs OE CLK CE 0 CE 1 R/W I/O 0 – I/O 9 Operatio .
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 18 of 21 Ordering Information 32K x8 3.3V Synchronous Du al-Port SRAM Spee d ( ns) Ordering Co de Package Name Package T yp e Operating Range 6.5 [1] CY7C09079V -6AC A100 100-Pin Thin Quad Flat Pack Commercial 7.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 19 of 21 64K x9 3.3V Synchronous Du al-Port SRAM Speed (ns) Ordering Code Package Name Package T ype Operating Range 6.5 [1] CY7C09189V -6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189V -6AXC A100 100-Pin Pb-Free T hin Quad Flat Pack Commercial 7.
CY7C09079V/89V/99V CY7C09179V/89V/99V Document #: 38-06043 Rev . *C Page 20 of 21 Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pa ck (TQFP) A100 (51-8504 8) 51-85048-*B [+] Feedback.
Document #: 38-06043 Rev . *C Revised December 10, 2008 Page 21 of 21 All product s and company names ment ioned in thi s document may be the tra demarks of thei r respective h olders. CY7C09079V/89V/99V CY7C09179V/89V/99V © Cypress Semicondu ctor Corporati on, 2005-2008.
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