Instruction/ maintenance manual of the product CY7C0241AV Cypress Semiconductor
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CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V 3.3V 4K/8K/16K x 16/18 Dual-Port S tatic RAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06052 Rev .
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 2 of 19 Pin Configurations Figure 1. 100- P in TQ FP (T op View) Notes 6.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 3 of 19 Figure 2. 100- P in TQ FP (T op View) Notes 8. A 12L on the CY7C0251A V .
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 4 of 19 Figure 3. 100- P in TQ FP (T op View) Pin Configurations (continued) 100 99 97 98 96 2 3 1 42 41 59.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 5 of 19 Architecture The CY7C024A V/024BV/025A V/026A V and CY7C0241A V/0251A V/036A V consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, IO and address lines, and control signals (CE , OE , RW ).
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 6 of 19 3FFF for the CY7C026A V/36A V) is the mailbox for the right port and the second highest memory location (FFE for the CY7C024A V/024BV/41A V/1F FE for the CY7C0 25A V/51A V , 3FFE for the CY7C02 6A V/36A V) is the mailb ox for the left port.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 7 of 19 T able 1 . Non-Conten ding Read/W rite Inputs Outpu ts Operation CE R/W OE UB LB SEM IO 9 – IO 17.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 8 of 19 Maximum Ratings Exceeding maximum ratings [14] may shorten the useful life of th e device. User guidelines are not te ste d. S torage T emperature ...
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 9 of 19 Figure 4. AC T est Load s an d W aveforms 3.0V GND 90% 90% 10% 3n s 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 590 Ω 3.3V OUTPUT R2 = 435 Ω C= 3 0 pF V TH =1 .
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 10 of 19 Dat a Retention Mode The CY7C024A V/024BV/025A V/026A V and CY7C0241A V/0251A V/036A V are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 1 1 of 19 Switching W aveforms Notes 29. R/W is HIGH for read cycles. 30. Device is continuously selected C E = V IL and UB or LB = V IL . This waveform cann ot be used for semaph ore reads.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 12 of 19 Notes 34. R/W or CE must be HIGH during all address transitions. 35. A write occurs during the overlap (t SCE or t PWE ) of a LOW CE or SEM and a LOW UB or LB .
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 13 of 19 Notes 43. CE = HIGH for the duration of the above timing (both write and re ad cycle). 44. IO 0R = IO 0L = LOW (request semaphore); CE R = CE L = HIGH.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 14 of 19 Note 47. CE L = CE R = LOW . Switching W aveforms (continued) VA L I D t DDD t WDD MA TCH MA TCH R/W R DA T A IN R DA T A OUTL t WC ADDRESS R t PWE VA L I D t SD t HD ADDRESS L t PS t BLA t BHA t BDD BUSY L Figure 12.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 15 of 19 Note 48. If t PS is violated, the busy signal is asserted on one side or the ot her , but there is no guarantee to which side BUSY is asserted.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 16 of 19 Notes 49. t HA depends on which en able pin (CE L or R/W L ) is deasserted fir s t. 50. t INS or t INR depends on which enable pin (CE L or R/W L ) is assert ed la st.
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 17 of 19 Ordering Information 4K x16 3.3V Asynchronous Dual -Port SRAM Spee d (ns) Orderin g Co de Package .
CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V Document #: 38-06052 Rev . *J Page 18 of 19 Package Diagram Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (T QFP) A100 16K x18 3.
Document #: 38-06052 Rev . *J Revised December 10, 2008 Page 19 of 19 All products and c ompany names men tioned in th is document m ay be the tr ademarks o f t h eir respect i v e holders. CY7C024A V/024BV/025A V/026A V CY7C0241A V/0251A V/036A V © Cypress Semicondu ctor Corpor ation, 2001-200 8.
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