Instruction/ maintenance manual of the product CYD18S36V Cypress
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CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-06076 Rev .
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 2 of 28 Logic Block Diagram [1] FTSEL L PORTSTD[1: 0] L DQ [35:0] L BE [3:0] L CE 0 L CE1 L OE L R/W L F.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 3 of 28 Pin Configurations Figure 1. Pin Diagram - 256-Ball FBGA (T op View) CYD01S36V/CYD02S36V/36V A/C.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 4 of 28 Pin Definitions Left Port Right Port Description A 0L –A 18L A 0R –A 18R Address In puts .
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 5 of 28 Master Reset The FLEx36 family devices un dergo a complete reset by taking its MRST input LOW . The MRST input can switch asynchro- nously to the clocks.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 6 of 28 Counter enable (CNTEN ) inputs are provided to stall the operation of the address input and use the internal addre ss generated by the intern al counter for fast, interleaved me mory applications.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 7 of 28 Counter Increment Operat ion Once the address counter registe r is initially loaded with an external address, the counter can internally increment the address value, potentiall y addr essi ng the entire memo ry array .
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 8 of 28 From Mask Register Mirror Coun ter Address Decode RAM Array Wra p 1 0 Increment Logic 1 0 +1 +2 1 0 Wra p Detect From Mask From Counter To Counter Bit 0 Wra p Figure 2.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 9 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) [23] The FLEx36 fami ly devices incorporate an IEEE 1 149 .1 serial boundary scan test access port (T AP).
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 10 of 28 D2 TDI TDO TDO TDI D1 TDO TDI D4 TDO TDI D3 TDO TDI Figure 4. Scan Chain for 18-Mbit Device D2 TDO TDI D1 TDO TDI TDI TDO Figure 5. Scan Chain for 9-Mbit Device T able 4.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 1 1 of 28 T able 6. Instruction Identificatio n Codes Instruct ion Code Description EXTEST 0000 Captures the Input/Ou tput ring contents. Places the BSR between the TDI and TDO.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 12 of 28 Maximum Ratin gs Exceeding maximum ratings [25] may shorten the useful life of the device. User gui delines are no t tested. S torage T emperature .
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 13 of 28 Figure 6. AC T est Load and Waveforms Switching Characteristics Over the Operating Range Parame.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 14 of 28 t HCM CNT/MSK Hold T ime 0.6 0.6 NA NA ns t OE Output Enable to Data V alid 4.4 4.4 5.5 5.5 ns t OLZ [31, 32] OE to Low Z 0 0 0 0 ns t OHZ [31, 32] OE to High Z 0 4.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 15 of 28 JT AG Switching W aveform T est Clock T est Mode Select TCK TMS T est Data-In TDI Te s t D a t a - O u t TDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching W aveforms Figure 7.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 16 of 28 Figure 8. Read Cycle [14, 33, 34, 35, 36] Notes 33. OE is asynchronously controlled; all other inputs (excluding MRST and JT AG) are synchronous to the rising clock edge.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 17 of 28 Figure 9. Bank Select Re ad [37, 38] Figure 10.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 18 of 28 Figure 1 1. Read-to-Write-to-Read (OE Controlled) [36, 39, 41 , 42] Figure 12.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 19 of 28 Figure 13. Write with Address Counter Advance [42] Switching W aveforms (continued ) t CH2 t CL.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 20 of 28 Figure 14. Counter Reset [4 3, 44] Notes 43. CE 0 = BE0 – BE3 = L OW; CE 1 = MRS T = CNT/MSK = HIGH. 44. No dead cycle exists during counter reset.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 21 of 28 Figure 15. Readback St ate of Address Counter or Mask Reg ister [46, 47, 48 , 49] Notes 46. CE 0 = OE = BE 0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 22 of 28 Figure 16. Lef t_Port (L_Port) W r ite to Right_Port (R_Port) Read [50, 51, 52 ] Notes 50. CE 0 = OE = ADS = CNTEN = BE0 – BE 3 = LOW; CE 1 = CNTRST = MRST = CNT/MSK = HIGH.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 23 of 28 Figure 17. Counter Inter rupt and Retransmit [17, 45, 53, 54, 55, 56] Notes 53. CE 0 = OE = BE 0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 24 of 28 Figure 18. MailBox In terrupt T iming [57, 58, 59, 60, 61] Switching W aveforms (continued ) t .
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 25 of 28 Ordering Information 512K × 36 (18-Mbit) 3.3V Synchro nous CYD18S36V Dual-Port SRAM Speed( MHz) Ordering Code Package Name Package T ype Operating Range 133 CYD18S36V - 133BBC BB256B 256-ball Grid Arr ay 23 mm × 23 mm with 1.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 26 of 28 Package Diagrams BOTTOM VIEW TOP VIEW 1 0 987654 32 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø 0 . 2 5MCAB Ø0.05 M C Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.
CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 27 of 28 Package Diagrams (continued) TOP VIEW 15.00 1.00 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø0.25 M C A B Ø0.05 M C 0.
Document Number: 38-06076 Rev . *G Revised Decenber 09, 2008 Page 28 of 28 FLEx36 and FLEx3 6-E are tradem arks of Cypress Se miconductor Corporation. All other t rademarks or reg istered trad emarks referen c ed herein a re property o f the respec tive corporat ions.
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