Instruction/ maintenance manual of the product CY7C67300 Cypress
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CY7C67300 EZ-Host™ Programmable Em bedded USB Host and Peripheral Controller with Automotive AEC Grade Support Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-08015 Rev .
CY7C67300 Document #: 38-08015 Rev . *J Page 2 of 99 Introduction EZ-Host™ (CY7C67300) is Cypress Semiconductor ’s first full-speed, low cost multipo rt hos t/peripheral controller. EZ-Host is designed to easily i nterface to most high performance CPUs to add USB host functionality .
CY7C67300 Document #: 38-08015 Rev . *J Page 3 of 99 USB Interface EZ-Host has two built in Host/Peripheral SIEs and four USB tran sceivers that meet the USB 2.
CY7C67300 Document #: 38-08015 Rev . *J Page 4 of 99 USB Features ■ USB 2.0-compliant for full and low speed ■ Up to four downstream USB host ports ■ Up to two upstream USB peripheral ports ■ .
CY7C67300 Document #: 38-08015 Rev . *J Page 5 of 99 External Memory Interface EZ-Host provides a robust interface to a wide variety of external memory arrays. All available ex ternal memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF .
CY7C67300 Document #: 38-08015 Rev . *J Page 6 of 99 External Memory Interface Pins External Memory Interface Block Diagrams Figure 2 illustrates how to connect a 64k × 8 memory array (SRAM/ROM) to the EZ-Host ex ternal memory interface.
CY7C67300 Document #: 38-08015 Rev . *J Page 7 of 99 Figure 4 illustrates the int erface for conne cting an 8-bit ROM or 8-bit RAM to th e EZ-Host ex ternal mem ory interface. In 8-bit mode, up to 512 K bytes of externa l ROM or RAM are supported. General Purpose IO Inte rface (GPIO) EZ-Host has up to 32 GPIO signals available.
CY7C67300 Document #: 38-08015 Rev . *J Page 8 of 99 SPI Pins The SPI port has a few different pin location optio ns as shown in Ta b l e 9 . The port location is selectable via t he GPIO control register [0xC006]. High-Spee d Serial Interface EZ-Host provides an HSS i nterface.
CY7C67300 Document #: 38-08015 Rev . *J Page 9 of 99 Host Port Interface EZ-Host has an HPI interface . The HPI inte rface provide s DMA access to the EZ-Host internal memory by an external host, plus a bidirectional mailbox register for supporting h igh level commu- nication protocols.
CY7C67300 Document #: 38-08015 Rev . *J Page 10 of 99 IDE Features ■ Programmable IO mod e 0–4 ■ Block mode transfers ■ Direct memory access to/from internal memory through the IDE data register IDE Pins Charge Pump Interface VBUS for the USB OTG po rt can be produced by EZ-H ost using its built in charge pump and some external compon ents.
CY7C67300 Document #: 38-08015 Rev . *J Page 1 1 of 99 Booster Inte rface EZ-Host has an on chip p ower booster circuit for use with power supplies that ra nge between 2.7V and 3 .6V . The booster circuit boosts the power to 3. 3V nominal to supply powe r for the entire chip.
CY7C67300 Document #: 38-08015 Rev . *J Page 12 of 99 Boot Configuration Inte rfa ce EZ-Host can boot i nto any one of four modes. Th e mode it boots into is determine d by the TTL voltage l evel of GPIO[31:3 0] at the time nRESET is deasserted . Ta b l e 1 9 shows the different boot pin combinations possibl e.
CY7C67300 Document #: 38-08015 Rev . *J Page 13 of 99 Minimum Hardware Require ments for St andalone Mode – Pe ripheral Only Power Savings and Reset Description This sections describes t he different modes for resetting t he chip and ways to save power .
CY7C67300 Document #: 38-08015 Rev . *J Page 14 of 99 External (R emote) Wakeup Source There are several possible events availabl e to wake EZ-Host from Sleep mode as shown in T able 20 . These may also be used as remote wakeup options for USB applica tions.
CY7C67300 Document #: 38-08015 Rev . *J Page 15 of 99 Figure 10. Memory Map HW INT's SW INT's 0x0000 - 0x00FF Primary Registers Swap Registers USB Registers HPI Int / Mail box Slave Setup Pa.
CY7C67300 Document #: 38-08015 Rev . *J Page 16 of 99 Registers Some registers have different functions for a read vs. a write access or USB host vs. USB de vi ce mode. Therefore , registe rs of this type ha ve multiple definitions for the same address.
CY7C67300 Document #: 38-08015 Rev . *J Page 17 of 99 Bank Register [0xC002] [R /W ] Register Descrip tion The Bank register maps registers R0–R15 into RAM. The elev en M SBs of this register are used as a base address for registers R0–R15. A register add ress is automatically gene rat ed by: 1.
CY7C67300 Document #: 38-08015 Rev . *J Page 18 of 99 CPU Speed Register [0xC008] [R/W] Register Descrip tion The CPU S peed regist er allows the processor to operate at a user selected speed. This register onl y affects the CPU, all other peripheral timing is still based on the 48 MHz system clock (unle ss otherwise noted).
CY7C67300 Document #: 38-08015 Rev . *J Page 19 of 99 Power Control Register [0xC00A] [R/W] Register Descrip tion The Power Control register co nt rols the power d own and wakeup options. Either t he sleep mode or t he halt mode opt ions can be selected.
CY7C67300 Document #: 38-08015 Rev . *J Page 20 of 99 Boost 3V OK (Bit 2) The Boost 3V OK bit i s a read only bit that return s the status of the OTG Boost circuit. 1: Boost circuit not ok and internal voltage rails are below 3.0V 0: Boost circuit ok and in ternal vo ltage rails are at or above 3.
CY7C67300 Document #: 38-08015 Rev . *J Page 21 of 99 HSS Interrupt Enable (Bit 7) The HSS Interrupt Enable bit enables or disabl es the following High-speed Serial Inte rface hardware interrupts: HSS Block Done and HSS RX Full.
CY7C67300 Document #: 38-08015 Rev . *J Page 22 of 99 USB Diagnostic Register [0xC03C] [R/W] Register Descrip tion The USB Diagnostic register provide s control of diagnostic modes. It is inte nded for use by devi ce characterization t ests, not for normal operations.
CY7C67300 Document #: 38-08015 Rev . *J Page 23 of 99 Memory Diagnostic Register [0xC03E] [W] Register Descrip tion The Memory Diagnostic register p rovides control of diagnostic modes. Memory Arbitr ation Select (Bits[10:8]) The Memory Arbitration Sele ct field is defined in Ta b l e 3 4 .
CY7C67300 Document #: 38-08015 Rev . *J Page 24 of 99 Extended Page n Map Register [R/W] ■ Extended Page 1 Map Register 0xC018 ■ Extended Page 2 Map Register 0xC01A Register Descrip tion The Extended Page n Map register contains the Page n high-order address bits.
CY7C67300 Document #: 38-08015 Rev . *J Page 25 of 99 External Memory Control R egister [0xC03A] [R/W] Register Descrip tion The External Memory Control register provides control of Wait S tates for the external SRAM or ROM. All wait states are b ased off of 48 MHz.
CY7C67300 Document #: 38-08015 Rev . *J Page 26 of 99 Watchdog Timer Register [0xC00C] [R/W] Register Descrip tion The W atchdog Timer register provides status and control over the W atchdog timer. The W atchdog timer can al so interrupt the processor .
CY7C67300 Document #: 38-08015 Rev . *J Page 27 of 99 Timer n Register [R/W] ■ T imer 0 Register 0xC010 ■ T imer 1 Register 0xC012 Register Descrip tion The T imer n Register sets the Timer n count. Both Timer 0 and T imer 1 decrement by one every 1 µs clock ti ck.
CY7C67300 Document #: 38-08015 Rev . *J Page 28 of 99 Port B D– St atus (Bit 14 ) The Port B D– S tatus bit is a read only bit that indicates the value of DA T A– on Port B. 1: D– is HIGH 0: D– is LOW Port A D+ St atus (Bit 13) The Port A D+ S tatus bit is a read only bit that indica tes the value of DA T A+ on Port A.
CY7C67300 Document #: 38-08015 Rev . *J Page 29 of 99 Port A SOF/EOP Enable (Bit 0) The Port A SOF/EOP Enable bit is only applica ble in host mode. In device mode this bit must be written as ‘0’. In host mode this bit enables or disables SOFs or EOPs for Port A.
CY7C67300 Document #: 38-08015 Rev . *J Page 30 of 99 Sequence Se le ct (Bit 6) The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receivin g data packet s; sequence checking must be hand led in firmware.
CY7C67300 Document #: 38-08015 Rev . *J Page 31 of 99 Register Descrip tion The Host n Count registe r is used to hold the numbe r of bytes (packet length) for the current transaction.
CY7C67300 Document #: 38-08015 Rev . *J Page 32 of 99 Sequence Status (Bit 3) The Sequence S tatus bit indicates the state of t he last re ceived data toggle from the device. Fi rmware is responsible for monitoring and han dling the sequence status. The Seque nce bit is only valid if the ACK bit is set to ‘1’ .
CY7C67300 Document #: 38-08015 Rev . *J Page 33 of 99 Register Descrip tion The Host n PID register is a writ e only register th at provides the PID and Endpoint information to the USB SI E to be used in the next transaction . PID Select (Bits [7:4]) The PID Select field is defined in T able 5 4 .
CY7C67300 Document #: 38-08015 Rev . *J Page 34 of 99 Host n Device Addr ess Register [W] ■ Host 1 Device Address Register 0xC088 ■ Host 2 Device Address Register 0xC0A8 Register Descrip tion The Host n Device Address register is a wri te only register that contains the USB Device Address that the host wants to commu- nicate with.
CY7C67300 Document #: 38-08015 Rev . *J Page 35 of 99 SOF/EOP Interrupt Enable (Bit 9) The SOF/EOP Interrupt En able bi t ena bles or disables the SOF/EOP timer interrupt 1: Enable SOF/EOP timer inter.
CY7C67300 Document #: 38-08015 Rev . *J Page 36 of 99 SOF/EOP Interrupt Flag (Bit 9) The SOF/EOP In terrupt Flag bit ind icates the s tatus of th e SOF/EOP T imer interrupt.
CY7C67300 Document #: 38-08015 Rev . *J Page 37 of 99 Host n SOF/EOP Counter Register [R] ■ Host 1 SOF/EOP Cou nter Register 0xC094 ■ Host 2 SOF/EOP Cou nter Register 0xC0B4 Register Descrip tion The Host n SOF/EOP Count er register contains the current value of the SOF/EOP down counte r .
CY7C67300 Document #: 38-08015 Rev . *J Page 38 of 99 USB Device Only Registers There are eleven sets of USB Device Only registers. All sets consist of at least two regist ers, one for Device Port 1 and one f or Device Port 2. In addition, each Device port has eight possible endpoin ts.
CY7C67300 Document #: 38-08015 Rev . *J Page 39 of 99 Sequence Se le ct (Bit 6) The Sequence Select bit determines whether a DA T A0 or a DA T A1 i s sent f or the ne xt data togg le. This bit ha s no effect on receiving data packets; sequence checking must be handled in firmware.
CY7C67300 Document #: 38-08015 Rev . *J Page 40 of 99 Register Descrip tion The Device n Endpoint n Address register is used as the base pointer into m emory sp ace for th e current Endpoin t transaction . There are a total of eight endpoints for each of the two ports.
CY7C67300 Document #: 38-08015 Rev . *J Page 41 of 99 Device n Endpoint n S tatus Register [R/W] ■ Device n Endpoint 0 S tatus Register [ Device 1: 0x0206 Device 2: 0x0286] ■ Device n Endpoint 1 S.
CY7C67300 Document #: 38-08015 Rev . *J Page 42 of 99 underflow and the Overf low and Underflow flags (bi ts 1 1 and 10 respectively) must be checked t o determine which event occurred.
CY7C67300 Document #: 38-08015 Rev . *J Page 43 of 99 The Device n Endpoint n Count Result register is a memory-based register tha t must be initialized to 0 x0000 before USB Device operations are ini tiated. After initializa tion, do not write to this re gister again.
CY7C67300 Document #: 38-08015 Rev . *J Page 44 of 99 supported in Port 1A). This bit is only available for Device 1 and is a reserved bi t in Device 2. 1: Enable VBUS interrupt 0: Disable VBUS interrupt ID Interrupt Enable (Bit 14 ) The ID Interrupt Enable bi t enables or disables th e OTG ID interrupt.
CY7C67300 Document #: 38-08015 Rev . *J Page 45 of 99 Error , or OUT Excep tion Error . In addition, the N AK Interrupt Enable bit in the Device n Endpoint Control registe r can also be set so that NAK responses trigger thi s interrupt.
CY7C67300 Document #: 38-08015 Rev . *J Page 46 of 99 Register Descrip tion The Device n S tatus register provide s status information for device operati on. Pending interrupts can be cl eared by writing a ‘1’ to the correspon ding bit. This register can be accessed by the HPI interface .
CY7C67300 Document #: 38-08015 Rev . *J Page 47 of 99 EP2 Interrupt Flag (Bit 2) The EP2 Interrupt Flag bit i ndicates if the en dpoint two (EP2) T ransaction Done in terrupt trigge red.
CY7C67300 Document #: 38-08015 Rev . *J Page 48 of 99 Device n SOF/EOP Count Register [W] ■ Device 1 SOF/EOP Count Register 0xC094 ■ Device 2 SOF/EOP Count Register 0xC0B4 Register Descrip tion The Device n SOF/EOP Count regi ster is written with t he time expected between receiving a SOF/EOP .
CY7C67300 Document #: 38-08015 Rev . *J Page 49 of 99 Receive Disable (Bit 12) The Receive Disable bi t enabl es or powers down (disables) t he OTG receiver section. 1: OTG receiver powered down and disabled 0: OTG receiver enabled Charge Pump Enable (Bit 1 1) The Charge Pump Enable bit enable s or disables the OTG VBus charge pump.
CY7C67300 Document #: 38-08015 Rev . *J Page 50 of 99 GPIO Control Register [0xC006] [R/W] Register Descrip tion The GPIO Control registe r configures the GPIO pins for various interface optio ns. It also controls t he polarity of the GPI O interrupt on IRQ1 (GPIO2 5) and IRQ0 (GPIO24).
CY7C67300 Document #: 38-08015 Rev . *J Page 51 of 99 Interrupt 0 Polarity Select (Bit 1) The Interrupt 0 Polarity Select bit selects the polarity for IRQ0. 1: Sets IRQ0 to rising edge 0: Sets IRQ0 to falling edge Interrupt 0 Enable (Bit 0) The Interrupt 0 Enable bit enable s or disabl es IRQ0.
CY7C67300 Document #: 38-08015 Rev . *J Page 52 of 99 GPIO n Direction Register [R/W] ■ GPIO 0 Direction Register 0xC022 ■ GPIO 1 Direction Register 0xC028 Register Descrip tion The GPIO n Direction register co ntrols the direction of the GPIO data pins (input/outpu t).
CY7C67300 Document #: 38-08015 Rev . *J Page 53 of 99 Reserved Write all reserved bit s with ’0’. IDE S tar t Address Register [0xC04A] [R/W] Register Descrip tion The IDE S tart Address register holds the start address f or an IDE block transfer .
CY7C67300 Document #: 38-08015 Rev . *J Page 54 of 99 IDE S top Address Register [0xC04C] [R/ W] Register Descrip tion The IDE S top Address register holds the stop address for an ID E block transfer . This register is byt e addressed and IDE block transfers are 16-bit words, the refore the LSB of the stop address is ignored.
CY7C67300 Document #: 38-08015 Rev . *J Page 55 of 99 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] All IDE PIO Port regist ers [0xC050 - 0xC06F] in Ta b l e 8 8 are defined in detail in the Informa tion T ech nology-A T Attachment -4 with Packet Interface Extension (A T A/A T API-4) Specification, T13/ 1 153 D Rev 18.
CY7C67300 Document #: 38-08015 Rev . *J Page 56 of 99 HSS Control Register [0xC070 ] [R /W] Register Descrip tion The HSS Control register p rovides high level status and cont rol over the HSS port. HSS Enable (Bit 15) The HSS Enable bit enables or disables HSS operat ion.
CY7C67300 Document #: 38-08015 Rev . *J Page 57 of 99 T ransmit Re ady (Bit 4) The T ransmit Ready bit is a read only bit that indicat es if the HSS T ransmit FIFO is ready f or the CPU to load ne w data for trans- mission.
CY7C67300 Document #: 38-08015 Rev . *J Page 58 of 99 HSS T ransmit Gap Register [0xC074] [R/W] Register Descrip tion The HSS T ran smit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted, thu s overwriting th e One S top Bit in the HSS Control register .
CY7C67300 Document #: 38-08015 Rev . *J Page 59 of 99 HSS Receive Address Register [0xC078] [R/W] Register Descrip tion The HSS Receive Address regist er is used as the base pointer address for the next HSS block receive transfer . Address (Bits [15:0]) The Address fiel d sets the base point er address for the next HSS block receive tran sfer .
CY7C67300 Document #: 38-08015 Rev . *J Page 60 of 99 HSS T ransmit Address Regi ster [0xC07C] [R/W] Register Descrip tion The HSS T ransmit Address register is used as th e base pointer address for the next HSS block transmit transf er .
CY7C67300 Document #: 38-08015 Rev . *J Page 61 of 99 HPI Registers There are five re gisters dedicated to HPI operation. In addition, there is an HPI status port which can be addressed over HPI. Each of these registers is cove red in this section and are summa- rized in T able 98 .
CY7C67300 Document #: 38-08015 Rev . *J Page 62 of 99 ID to HPI Enable (Bit 14) The ID to HPI Enable bit routes the OTG I D i nt errupt t o the HPI port instead of the on-chip CPU.
CY7C67300 Document #: 38-08015 Rev . *J Page 63 of 99 SIEXmsg Register [W] ■ SIE1msg Register 0x0144 ■ SIE2msg Register 0x0148 Register Descrip tion The SIEXmsg register allows an in t errupt to be generat ed on the HPI port.
CY7C67300 Document #: 38-08015 Rev . *J Page 64 of 99 HPI S tat us Port [] [HPI: R] Register Descrip tion The HPI S tatus Port provides the external host processor wi th the MailBox status bits plus several SIE status bits. This register is not accessible from the on-chip CPU.
CY7C67300 Document #: 38-08015 Rev . *J Page 65 of 99 Done1 Flag (Bit 2) In host mode the Done 1 Flag bit is a read only bit t hat indicates if a host packet done interrupt o ccurs on Host 1. In device mode this read only bi t indicates if an any of the endpoint inte rrupts occur on Device 1.
CY7C67300 Document #: 38-08015 Rev . *J Page 66 of 99 SPI Configuration Registe r [0xC0C8] [R/W] Register Descrip tion The SPI Configuration regist er controls the SPI port.
CY7C67300 Document #: 38-08015 Rev . *J Page 67 of 99 SPI Control Register [0xC0C A] [R/W] Register Descrip tion The SPI Control reg ister controls the SPI port.
CY7C67300 Document #: 38-08015 Rev . *J Page 68 of 99 Receive Bit Length (Bits [2:0]) The Receive Bit Length fi eld controls whether a ful l byte or partial byte is received.
CY7C67300 Document #: 38-08015 Rev . *J Page 69 of 99 Receive Interrupt Flag (Bit 2) The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt triggere d.
CY7C67300 Document #: 38-08015 Rev . *J Page 70 of 99 CRC Enable (Bit 13) The CRC Enable bit enable s or disables the CRC operation. 1: Enables CRC operation 0: Disables CRC operation CRC Clear (Bit 12) The CRC Clear bit clears t he CRC with a load of al l ones.
CY7C67300 Document #: 38-08015 Rev . *J Page 71 of 99 SPI Data Register [0xC0D6] [R/W] Register Descrip tion The SPI Data register contains data received on the SPI port when read.
CY7C67300 Document #: 38-08015 Rev . *J Page 72 of 99 SPI T ransmit Count Reg ister [0xC0DA] [R /W] Register Descrip tion The SPI Transmit Count register designates the block byte length for t he SPI transmit DMA transfer . Count (Bits [10:0]) The Count field sets the count for t he SPI transmit DMA t ransfer .
CY7C67300 Document #: 38-08015 Rev . *J Page 73 of 99 Register Descrip tion The SPI Receive Count regi ster designates the block by te length for the SPI receive DMA transfer . Count (Bits [10:0]) The Count field se ts the count for the SPI receive DMA transf er .
CY7C67300 Document #: 38-08015 Rev . *J Page 74 of 99 UART S tatus Register [0xC0E2] [R] Register Descrip tion The UART S tatus regist er is a re ad only register that indica tes the status of the UART buffer . Receive Full (Bit 1) The Receive Full bit indicates whether t he receive buffer is full.
CY7C67300 Document #: 38-08015 Rev . *J Page 75 of 99 PWM Registers There are eleven registe rs dedicated to PWM o peration. Each of these registers are covered in this section and summarized in T able 124 .
CY7C67300 Document #: 38-08015 Rev . *J Page 76 of 99 Mode Select (Bit 8) The Mode Select bit selects between cont inuous PWM cycling and one shot mode. The default is cont inuous repeat. 1: Enable One Shot mode. The mode runs the number of counter cycles set in the PWM Cycle Count register and then stops.
CY7C67300 Document #: 38-08015 Rev . *J Page 77 of 99 PWM n St art Register [R/W] ■ PWM 0 S tart Reg ister 0xC0EA ■ PWM 1 S tart Reg ister 0xC0EE ■ PWM 2 S tart Reg ister 0xC0F2 ■ PWM 3 S tart.
CY7C67300 Document #: 38-08015 Rev . *J Page 78 of 99 PWM Cycle Count R egister [0xC0F A] [R /W] Register Descrip tion The PWM Cycle Count register de signates the number of cycles to run when in one shot mode. One shot mode is enabled by setting the Mode Select bit of the PWM Control register to ‘1’.
CY7C67300 Document #: 38-08015 Rev . *J Page 79 of 99 Pin Diagram Pin Descriptions 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GPIO24/INT/IORDY /IRQ0 GND A10 XTALOUT XTA.
CY7C67300 Document #: 38-08015 Rev . *J Page 80 of 99 71 D1 1/MOSI IO D1 1: External Memory Data Bus MOSI: SPI MOSI 72 D10/ SCK I O D10: External Memory Data Bus SCK: SPI SCK 73 D9/n SSI IO D9: Extern.
CY7C67300 Document #: 38-08015 Rev . *J Page 81 of 99 41 GPIO29/O TGID IO GPIO29: General Purpose IO OTGID: Input for OTG ID pin. When used as OTGID, tie th is pin high through an external pull up resistor. Assuming V CC = 3.0V , a 10K to 40K resistor must be used.
CY7C67300 Document #: 38-08015 Rev . *J Page 82 of 99 60 GPIO1 1 /D1 1/MOSI IO GPIO1 1: Gene ral Purpose IO D1 1: D1 1 for HPI or IDE MOSI: SPI MOSI 61 GPIO10/D 10/SCK IO GPIO10: General Purpose IO D1.
CY7C67300 Document #: 38-08015 Rev . *J Page 83 of 99 Absolute Maximum Ratings This section lists the absolute maximum ra tings. S tresses above those listed can cause permanent damag e to the device. Exposure to maxi mum rated conditions f or extended periods can affect device operation a nd reliability .
CY7C67300 Document #: 38-08015 Rev . *J Page 84 of 99 USB T ransceiver USB 2.0 certified in full- an d low-speed modes. I SLEEP Sleep Current USB Peripheral: i ncludes 1.5K internal pu ll up 210 500 μ A Without 1.5K internal pul l up 5 30 μ A I SLEEPB Sleep Current with Booster Enabled USB Peripheral: includes 1.
CY7C67300 Document #: 38-08015 Rev . *J Page 85 of 99 AC Timing Characteristics Reset T iming Clock T iming Notes 1 1. Clock is 12 MHz nominal. 12. v XI NH is required to be 3.
CY7C67300 Document #: 38-08015 Rev . *J Page 86 of 99 SRAM Read Cycle [15] Notes 13. 0 wait state cycle. 14. t AC External SRAM access time = 12 ns for zero and one wait stat es. T he External SRAM access ti me = 12 ns + (n – 1)*T for wait st a tes = n, n > 1, T = 48 MHz clock period.
CY7C67300 Document #: 38-08015 Rev . *J Page 87 of 99 SRAM Write Cycle [17] Notes 16. t WPW The write pulse width = 18.8 n s min. for zero and one wait st ates. The write pulse = 18.8 ns + (n – 1)*T f or wait st ates = n, n > 1, T = 48 MHz clock period.
CY7C67300 Document #: 38-08015 Rev . *J Page 88 of 99 I2C EEPROM Timing-Serial IO T able 13 9. I2C EEPROM Timing Parameters Parameter Descript ion Min T y pical Max Unit f SCL Clock Frequency 400 kHz .
CY7C67300 Document #: 38-08015 Rev . *J Page 89 of 99 HPI (Host Port Int erface) W rite Cycle T iming Notes 18. T = system clock period = 1/48 MHz. T able 14 0.
CY7C67300 Document #: 38-08015 Rev . *J Page 90 of 99 HPI (Host Port Interface) Read Cy cle T iming T ab le 141. HPI Read Cy cle Timing Parameters Parameter Description Min Ty p i c a l Ma x Unit t AS.
CY7C67300 Document #: 38-08015 Rev . *J Page 91 of 99 IDE Timing The IDE interface supports PIO mode 0-4 as specified in the Inform at ion T echnology-A T Attachment–4 with Packet Interface Exte nsion (A T A/A T API-4) S pecification, T13/1 153D Re v 18.
CY7C67300 Document #: 38-08015 Rev . *J Page 92 of 99 Hardware CTS/RTS Handshake t CTSsetup : HSS_CTS setup time before HSS_R TS = 1.5T min. t CTShold : HSS_CTS hold time af ter ST ART bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is en abled, transmission can be help off by deassertin g HSS_CTS at least 1.
CY7C67300 Document #: 38-08015 Rev . *J Page 93 of 99 R/W 0xC00C W atchdog Timer Reserved... 0000 0000 ...Reserved T imeout Flag Period Select Lo ck Enable WDT Enable Reset St r o b e 0000 0000 R/W 0x.
CY7C67300 Document #: 38-08015 Rev . *J Page 94 of 99 R/W 0xC07E HSS Tran smit Counter Reserved Counter ... 0000 0000 ...Counter 0000 000 0 R/W 0xC080 0xC0A0 Host n Co ntrol Reserved 0000 0000 Preamble Enable Seque nce Select Sync Enable ISO Enable Reser ved Arm Enable 0000 0000 R/W 0xC082 0xC0A2 Host n Address Address.
CY7C67300 Document #: 38-08015 Rev . *J Page 95 of 99 R/W 0xC0AC Device 2 Interrupt Enable Reserved SOF/EOP T imeout Interrupt Enable Wa k e Interrupt Enable SOF/EOP Interrupt Enable Reset Interrupt E.
CY7C67300 Document #: 38-08015 Rev . *J Page 96 of 99 R/W 0: 0xC0EC 1: 0xC0F0 2: 0xC0F4 3: 0xC0F8 PWM n S t op Reserved Address... 0000 0000 ...Address 0000 0000 R/W 0xC0F A PWM Cycle Count Count.
CY7C67300 Document #: 38-08015 Rev . *J Page 97 of 99 Ordering Information Package Diagrams Figure 12. 100-Pin T hin Plastic Quad Flat Pa ck (TQFP) A100SA T ab le 14 3.
CY7C67300 Document #: 38-08015 Rev . *J Page 98 of 99 Document History Page Document Title: CY7C67300 EZ-Host™ Programmable Embe dded USB Host and Periph eral Controller with Automotive AEC Grade Support Document Number: 38-08015 REV . ECN NO. Orig.
Document #: 38-08015 Rev . *J Revised July 28, 2008 Page 99 of 99 EZ-Host is a register ed trademark of Cypr ess Semiconductor Corp. All ot her trademarks or reg istered trademar ks referenced herei n are property of the respe ctive corporat ions.
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